ΗΜΥ 312 -- ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΗΛΕΚΤΡΟΝΙΚΩΝ ΥΠΟΛΟΓΙΣΤΩΝ ΔΙΑΛΕΞΕΙΣ 12-13: CPU Datapath Design – Intro to ALU Διδάσκων: Χάρης Θεοχαρίδης, ΗΜΜΥ ([email protected]) [Προσαρμογή από Computer Architecture, Computer Organization and Design, Patterson & Hennessy, © 2005 και Superscalar Microprocessor Design, Johnson, © 1992 ] The Stored Program Computer • 1943: ENIAC – Presper Eckert and John Mauchly -- first general electronic computer (or was it John V. Atananasoff in 1939?) – Hard-wired program -- settings of dials and switches • 1944: Beginnings of EDVAC – among other improvements, includes program stored in memory • 1945: John von Neumann – wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC • The basic structure proposed in the draft became known as the “von Neumann machine” (or model). – a memory, containing instructions and data – a processing unit, for performing arithmetic and logical operations – a control unit, for interpreting instructions ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.2 Von Neumann Model MEMORY MAR MDR INPUT OUTPUT Keyboard Monitor PROCESSING UNIT Mouse Printer Scanner LED Disk, etc. ALU REG FILE Disk, etc. CONTROL UNIT PC IR ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.3 Data Path Components • Global bus – Set of wires that carry n-bit signals to many components – Inputs to bus are controlled by triangle structure called tri-state devices » Place signal on bus when enabled » Only one (n-bit) signal should be enabled at a time » Control unit decides which signal “drives” the bus – Any number of components can read bus » Register only captures bus data if write-enabled by the control unit • Memory and I/O – Control signals and data registers for memory and I/O devices – Memory: LW, SW – Input (keyboard): Interrupt, DMA – Output (text display): Interrupt, DMA ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.4 Data Path Components (cont.) • ALU/FPU – Input: register file or sign-extended bits from IR (immediate field) – Output: bus; used by… » Condition code registers » Register file » Memory and I/O registers • Register File – Two read addresses, one write address – Input: n-bits from bus » Result of ALU operation or memory (or I/O) read – Outputs: two n-bit » Used by ALU, PC, memory address » Data for store instructions passes through ALU ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.5 Instructions (ISA) • Fundamental unit of work • Constituents – Opcode: operation to be performed – Operands: data/locations to be used for operation • Encoded as a sequence of bits (just like data!) – Sometimes have a fixed length (e.g., 16 or 32 bits) – Atomic: operation is either executed completely, or not at all ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.6 Instruction Processing FETCH instruction from mem. DECODE instruction EVALUATE ADDRESS FETCH OPERANDS EXECUTE operation STORE result ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.7 Instruction Processing: FETCH • Idea – Put next instruction in IR & increment PC F • Steps D – Load contents of PC into MAR – Increment PC – Send “read” signal to memory EA – Read contents of MDR, store in IR OP EX S ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.8 Instruction Processing: DECODE • Identify opcode F – In LC-3, always first four bits of instruction – 4-to-16 decoder asserts control line corresponding D to desired opcode EA • Identify operands from the remaining bits – Depends on opcode e.g., for LDR, last six bits give offset OP e.g., for ADD, last three bits name source operand #2 EX S ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.9 Instruction Processing: EVALUATE ADDRESS • Compute address F – For loads and stores – For control-flow instructions D • Examples EA – Add offset to base register (as in LDR) – Add offset to PC (as in LD and BR) OP EX S ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.10 Instruction Processing: FETCH OPERANDS • Get source operands for operation F D • Examples – Read data from register file (ADD) – Load data from memory (LDR) EA OP EX S ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.11 Instruction Processing: EXECUTE • Actually performs operation F D • Examples – Send operands to ALU and assert ADD signal – Do nothing (e.g., for loads and stores) EA OP EX S ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.12 Instruction Processing: STORE • Write results to destination F – Register or memory D • Examples – Result of ADD is placed in destination reg. EA – Result of load instruction placed in destination reg. – For store instruction, place data in memory OP » Set MDR » Assert WRITE signal to memory EX S ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.13 Datapath and Control Unit ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.14 Tracking Control Signals - Cycle 1 LW ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.15 Tracking Control Signals - Cycle 2 SW LW ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.16 Tracking Control Signals - Cycle 3 1 0 01 ADD SW LW ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.17 Tracking Control Signals - Cycle 4 0 0 1 SUB ADD SW LW ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.18 Tracking Control Signals - Cycle 5 1 1 SUB ADD SW LW ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.19 Changing the Sequence of Instructions • In the FETCH phase, we incremented the Program Counter by 1 (address) • What if we don’t want to always execute the instruction that follows this one? – examples: loop, if-then, function call • Need special instructions that change the contents of the PC. • These are called jumps and branches. – jumps are unconditional -- they always change the PC – branches are conditional -- they change the PC only if some condition is true (e.g., the contents of a register is zero) ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.20 Instruction Processing Summary • Instructions look just like data -- it’s all interpretation. • Three basic kinds of instructions: – computational instructions (ADD, AND, …) – data movement instructions (LD, ST, …) – control instructions (JMP, BRnz, …) • Six basic phases of instruction processing: F ® D ® EA ® OP ® EX ® S – not all phases are needed by every instruction – phases may take variable number of machine cycles ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.21 Driving Force: The Clock • The clock is a signal that keeps the control unit moving – At each clock “tick,” control unit moves to the next machine cycle -- may be next instruction or next phase of current instruction. • Clock generator circuit: – Based on crystal oscillator – Generates regular sequence of “0” and “1” logic levels – Clock cycle (or machine cycle) -- rising edge to rising edge “1” “0” Machine time® Cycle ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.22 Instructions vs. Clock Cycles • MIPS vs. MHz – MIPS = millions of instructions per second – MHz = millions of clock cycles per second • These are not the same -- why? ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.23 The Control Unit • Program is stored in memory – as machine language instructions, in binary • The task of the control unit is to execute programs by repeatedly: – Fetch from memory the next instruction to be executed. – Decode it, that is, determine what is to be done. – Execute it by issuing the appropriate signals to the ALU, memory, and I/O subsystems. – Continues until the HALT instruction ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.24 von Neumann Architecture ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.25 (c) Yngvi Bjornsson The Von Neumann Architecture Bus Processor (CPU) Memory Input-Output Control Unit ALU Communicate with Store data and program "outside world", e.g. • Screen Execute program • Keyboard • Storage devices • ... Do arithmetic/logic operations requested by program ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.26 The ALU Subsystem • The ALU (Arithmetic/Logic Unit) performs – mathematical operations (+, -, x, /, …) – logic operations (=, <, >, and, or, not, ...) • In today's computers integrated into the CPU • Consists of: – Circuits to do the arithmetic/logic operations. – Registers (fast storage units) to store intermediate computational results. – Bus that connects the two. ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.27 Structure of the ALU • Registers: – Very fast local memory cells, that store R0 operands of operations and R1 intermediate results. – CCR (condition code register), a special R2 purpose register that stores the result of <, = , > operations • ALU circuitry: – Contains an array of circuits to do Rn mathematical/logic operations. • Bus: – Data path interconnecting the registers ALU circuitry to the ALU circuitry. GT EQ LT ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.28 28 ALU and its importance qArithmetic and Logic Unit (ALU) ● It is a functional box designed to perform basic arithmetic, logic, and shift operations on the data. ● Implementation of the basic operations such as logic, program control, and data transfer operations are easier than arithmetic and I/O operations. Therefore, in this section we concentrate on arithmetic operations. ΗΜΥ 312 Δ12-13 CPU Datapath Design – Intro to ALU.29 Why do we need to improve the ALU? qArithmetic and Logic Unit (ALU) ● In an attempt to improve the performance, this section will talk about the Arithmetic Logic Unit. ● In regard to our previous mentions about CPU time (T), we are looking at techniques to reduce p. T = Ic * CPI * t = Ic * (p+m*k)* t Instruction Count Clock Processor Memory Latency (+ Cache) ΗΜΥ 312 Δ12-13 CPU Datapath Design