JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 173

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies (Invited paper)

J. M. Portal, M. Bocquet, M. Moreau, H. Aziza, D. Deleruyelle, Y. Zhang, W. Kang, J.-O. Klein, Y.-G. Zhang, C. Chappert, and W.-S. Zhao

Abstract⎯Low power consumption is a major issue consumption becomes a major issue in nowadays in nowadays electronics systems. This trend is pushed by electronics systems. In all application domains, memories the development of center related to cloud services remain a major contributor to power consumption. On one and soon to the (IoT) deployment. hand, server nodes are based on a classical memory Memories are one of the major contributors to power hierarchy going from the register and in high consumption. However, the development of emerging performance central processing unit (CPU), through the memory technologies paves the way to low-power design, dynamic random access memory (DRAM) as the primary through the partial replacement of the dynamic random memory to the (HDD) for massive storage. access memory (DRAM) with the non-volatile On the other hand, IoT autonomous objects are built around stand-alone memory in servers or with the embedded or the micro controller unit (MCU), where the memory distributed emerging non- in IoT hierarchy is divided in the core memory (register), memory objects. In the latter case, non-volatile flip-flops (NVFFs) for data (static random access memory (SRAM)), and seem a promising candidate to replace the retention instruction (electrically erasable programmable read-only latch. Indeed, IoT objects present long sleep time and memory (EEPROM), flash). NVFFs offer to save data in registers with zero power In this context, emerging memory solutions could open when the application is idle. This paper gives an the way to new design architectures with full or partial overview of NVFF architecture flavors for various replacement of existing memories. A clear target to bring emerging memory technologies. emerging memories in the is lowering

the systems power. This assumption is based on [1] for Index Terms⎯Emerging memory technology, . Indeed technologies like the phase ferroelectric RAM, low power, magnetic RAM, non-volatile flip-flops, phase change RAM, resistive change RAM (PCRAM), spin-transfer torque magnetic RAM RAM (STT-MRAM), and resistive RAM (ReRAM) or ferroelectric RAM (FeRAM) present performances (programming time, voltage, and current and/or endurance 1. Introduction and retention) that could bring significant advantages versus dynamic RAM (DRAM) or flash. With the development of data center related to cloud Server consumption could be lowered with the services and the Internet of Things (IoT), low power introduction of the flash as a bridge between DRAM and HDD, this trend could be even improved with the Manuscript received March 3, 2014; revised May 13, 2014. This work introduction of PCRAM[2]. In the same way, non-volatile was supported by the ANR project DIPMEM under Grant No. (NV) flash memories embedded in MCU can be replaced ANR-12-NANO-0010-04. [3] [4] J. M. Portal, M. Bocquet, M. Moreau, H. Aziza, and D. Deleruyelle are by emerging memories such as FeRAM or MRAM for with Aix-Marseille University and Institut Matériaux Microélectronique the low power purpose. Nanosciences de Provence, CNRS UMR7334, Marseille, France Regarding IoT autonomous objects, power (Corresponding author e-mail: [email protected]). consumption is a key point for their deployments. The Y. Zhang, J.-O. Klein, C. Chappert, and W.-S. Zhao are with Institut d’Electronique Fondamentale, University Paris-Sud 11 and CNRS introduction of emerging memories offers the capability to UMR8622, Orsay 91405, France. bring non-volatility memories through distributed W. Kang and Y.-G. Zhang are with Electronics and Information memories in logic. This concept allows to completely Engineering School, Beihang University, Beijing 100191, China. power down the system, while saving the MCU state and W.-S. Zhao is also with with Electronics and Information Engineering School, Beihang University, Beijing 100191, China. data in the non-volatile memory point. In this context, the Digital Object Identifier: 10.3969/j.issn.1674-862X.2014.02.007 aim of this paper is to give an overview of the non-volatile

174 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 flip-flops (NVFFs) architecture flavors based on emerging (set and reset operations are performed with the positive non-volatile memory technologies. voltage pulse). Reset current reduction and temperature The remainder of this paper is composed as follows. stability still have to be enhanced for this technology. Section 2 summarizes the emerging memory technologies. 2.3 ReRAM Technologies Section 3 introduces the classical retention flip-flop solution used to save data through power gating techniques. In its simplest form, the ReRAM device relies on Section 4 is devoted to the presentation of the general metal/insulator/metal (MIM) structures whose conductivity architecture and operating phase of NVFF. Section 5 can be electrically switched between high and low resistive presents several architectures based on different states. Regarding the polarity of the programming voltage, technologies. Finally, Section 6 concludes the paper. a classification can be drawn with unipolar memories and bipolar memories. In unipolar oxide resistive RAM 2. Emerging Memory Technologies (OxRAM), reversible switching is achieved thanks to reproducible formation/dissolution of conductive filaments This section is devoted to the overview of the emerging [5],[6] within the resistive oxide. A typical resistive switching memory technologies used to develop NVFF based on a thermal effect shows a unipolar current-voltage architectures. characteristic. During the set operation, a partial 2.1 FeRAM Technology breakdown occurs in the material and conductive filaments FeRAM is the most mature technology among the are formed. In contrast, they are thermally disrupted during emerging memory technologies. This technology is widely the reset operation because of the high power density used for embedded applications requiring low power since generated locally, similar to a traditional house fuse. its main feature is low-voltage and low-current Bipolar technologies are the conductive bridge RAM programming. FeRAM memory cells are based on a (CBRAM) and programmable metallization cells (PMC) or ferroelectric (1C) structure, which limit the the bipolar OxRAM. CBRAM and PMC belong to scaling below the 65 nm or 45 nm node. FeRAM utilizes the “nanoionic” memories. MIM-like memory elements consist positive and negative polarization directions corresponding of an inert electrode (W, Pt, etc.), an ionic conductor used to “1” and “0” states for stored data. The memorization as the solid electrolyte (WO3, MoO3, GeSe, AgGeSe, etc.), mechanism is based on the loop of the and an active electrode (Ag, Cu, etc.), through an polarization versus the applied voltage. To change the state electrochemical reaction, ions (Ag+, Cu+, etc.) diffusing of the FeRAM capacitor, a bipolar voltage needs to be within the electrolyte. In bipolar OxRAM, the memory applied to switch domains from a positive remnant effect occurs in specific transition metal oxides (TiOx, polarization to a negative remnant polarization. Positive HfOx) due to a migration of ions (oxygen ions), which are and negative remnant polarizations are defined when the typically described by the motion of the corresponding linear polarization is equal to 0, i.e., the applied voltage is vacancies. null. 2.4 MRAM Technologies 2.2 PCRAM Technology MRAM is one of the most promising technologies for PCRAM, also known as the PCM or PRAM technology, the future logic and memory applications[7]. It is built in a is used mainly for stand-alone memories and is seen as a hybrid architecture composed of basic storage elements and potential candidate to be introduced in the memory complementary metal-oxide-semiconductor hierarchy as the mass-storage memory. The is (CMOS) parts. The basic storage element of MRAM is based on a capacitor like (1C) structure, where generally referred to the magnetic tunnel junction (MTJ) chalcogenide alloys are sandwiched between two metal nanopillar that is mainly based on the “sandwich” structure: electrodes. The memorization mechanism is based on the a thin oxide barrier separated by two ferromagnetic layers. resistance change between a low resistance state (set As the consequence of the tunnel magneto resistance (TMR) operation) and a high resistance state (reset operation). The effect, the MTJ resistances, Rp and Rap, depend on the low resistance state corresponds to the crystal phase of the relative magnetization orientation of two ferromagnetic chalcogenide alloys whereas the high resistance state layers. With respect to the array architecture, there are two corresponds to the amorphous phase. The phase change is basic types: one transistor with one MTJ (1T-1MTJ) and the obtained by applying a high current through the cell from cross point[7],[8]. The 1T-1MTJ architecture is the most the bottom electrode to the top, to heat the chalcogenide easy-understanding form where each MTJ is connected in alloys above the melting temperature (amorphous phase) or series with an MOS transistor that operates the selecting between the melting point and crystallization temperature function. However, its density potential is limited. The (crystal phase). Thus programming is a unipolar process cross-point array architecture is able to provide prominent

PORTAL et al.: An Overview of Non Volatile Flip-Flops Based on Emerging Memory Technologies 175 density efficiency; however, it also involves a lot of performance challenges, such as the low data access speed and sneak currents, which lead to write/read performance degradation. According to the different switching mechanisms, MRAM can be classified into diverse categories or generations, for example, field induced magnetic switching (FIMS) MRAM[9], thermally assisted switching (TAS) MRAM[10], spin transfer torque (STT) MRAM[11], and TAS-STT MRAM[12]. Among them, STT-MRAM is considered as the most promising one due to its high power efficiency and high switching speed. As it only requires a bi-directional spin polarized current, the [13] switching process can be greatly simplified . Recent material progress demonstrates perpendicular magnetic anisotropy (PMA) structures (e.g. CoFeB/MgO) allow the higher energy barrier than in-plane anisotropy, which can [14],[15] Fig. 1. Architecture of a classical balloon latch used with power- overcome the thermal stability issue . gating technique[20]. 3. Retention Flip-Flop and Power Gating Technique The mainstream of power reduction has been driven for many years by transistor downscaling and concomitant voltage reduction. A side effect of this reduction is the increase of leakage current in the sub-threshold regime with more than 40% of active mode energy dissipation due to the power leakage of idle [16],[17]. To overcome this issue, solutions based on process changes have been proposed, such as the high-κ oxide associated with a metal gate[18]. Another well-known solution to save power is to power down sub-circuits of system on chip (SoC) during the idle state. However, when sub-circuits are power-down, Fig. 2. NVFF are designed around four architecture flavors the data saved in the flip-flops are lost and a subsequent (modified master stage, modified slave stage, and pre/post NV high power budget is required for saving/restoring their balloon insertion). content with the sub-threshold leakage current. Numerous design solutions have been proposed to 4. NVFF General Architecture maintain flip-flop contents, such as multi-threshold voltages MOS transistors used with power gating In power-down applications, the flip-flop with the NV techniques[19]. The basic principle to save the flip-flop’s capability might be an alternative solution to power gating content during the power-down relies on a retention circuit technique. The main idea relying on this solution is to also known as a balloon circuit[20]. The scheme of a replace the balloon latch with an NV balloon. Doing so, the retention flip-flop with a balloon latch is reproduced in Fig. virtual ground or VDD is not any longer necessary, while the 1. By using this technique, the master-slave flip-flop is flip-flop state is saved in an NV memory. During connected either to the virtual ground or VDD while a power-down, the flip-flop content is stored in the NV balloon latch is connected to the real ground and VDD. balloon while the real ground or VDD is disconnected (store During the power-down, the data of the slave latch in the phase). The flip-flop content is restored from the NV flip-flop is memorized in the balloon latch while the balloon after power up (restore phase). Thus, the use of NV flip-flop is disconnected from the ground or VDD thanks to a balloon allows achieving zero power consumption at the switch inserted between the real and the virtual ground line. flip-flop level during the idle state. The data is restored from the balloon latch to the slave NVFF solutions are often defined for a given NV stage of the flip-flop after power up. memory technology. However, some common architecture In conclusion, the retention flip-flop with power-gating features can be summarized. As presented in Fig. 2, a technique is a massively deployed solution, but leakage classification of NVFF can be established regarding the power remains a real challenges. connection of the NV balloon to the flip-flop.

176 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 flip-flop during the store/restore phase and to disconnect the NV balloon during the normal operation mode. Depending on the memory technology, the writing circuit might be necessary to program or erase the NV when the flip-flop state is stored in the NV balloon. During the restore phase, a sensing block is used to read the NV block and restore the state in the flip-flop. Finally, the NV block is built around the NV cell that keeps the state of the flip-flop during the power-down.

5. Example of Demonstrated NVFF

Fig. 3. Schematic of NV balloon based on four elements: Solutions connection switches, writing block, sensing block, and NV block. NVFF solutions have been demonstrated by using several architectures and memory technologies. The aim of FeRAM NV this section is to give an example of a solution developed balloon with each architecture flavor. Moreover, the presented MS Flip‐Flop examples cover also the different NV technologies, namely FeRAM, PCRAM, STT-MRAM, and ReRAM (unipolar Q and bipolar). 5.1 NVFF with Post-Insertion NV Balloon Based on FeRAM Technology An NVFF has been demonstrated using a back-up module inserted post flip-flop using a FeRAM technology [21]−[23] QB to store the flip-flop state . The scheme of the FeRAM based NVFF is given in Fig. 4. The FeC NV balloon is connected to the outputs Q and

Fig. 4. Flip-flop architecture with an NV balloon based on QB of the slave stage of the flip-flops. The connection FeRAM memory for energy harvesting application[21]. switch is presented to isolate the NV block during the normal operation mode and to connect the two FeRAM PCRAM NV balloon cells during the store/restore operation. None writing block is necessary, since the FeRAM technology used in this solution is compatible with CMOS voltages. Finally, a differential voltage-sensing scheme is used assuming that the two FeRAM cells store complementary values. The voltage difference on the two FeRAM cell is amplified by the slave latch feedback loop. The proposed structure is successfully implemented in a checkpoint processor by using a 0.18 µm CMOS core process. Since the ferroelectric material lifetime remains a great challenge with the endurance about 1012 cycles to 1014 cycles, an additional circuit that check the FeRAM state might be added to only program FeRAM cells in case of state change. The last MS Flip‐Flop point is the limited shrinking capability of the FeRAM Fig. 5. Flip-flop architecture with an NV balloon based on capacitor, which could limit the introduction of this solution

PCRAM memory[24]. for the CMOS node bellow 65 nm. In the same way, the architecture of the NV balloon 5.2 NVFF with Post-Insertion NV Balloon Based on presents some common features whatever the memory PCRAM Technology technology involved. Fig. 3 presents a schematic view of An NVFF has been demonstrated using an NV balloon the NV balloon with usually four parts: the NV block, inserted post flip-flop using a PCRAM technology to store sensing block, writing block, and connection switches. The the flip-flop state[24]. The scheme of this solution is connection switches allow to connect the NV balloon to the illustrated in Fig. 5.

PORTAL et al.: An Overview of Non Volatile Flip-Flops Based on Emerging Memory Technologies 177 Here also, the PCRAM NV balloon is connected at the technology node under 1.2 V, which exhibits fast writing output Q and QB of the master-slave flip-flop during the time (100 ps) and does not impact significantly the flip-flop store phase and to the input of the slave stage during the delay (set-up time, hold time, and propagation delay). restore phase, through a tri-state buffer (I0). NV connection However, the writing current remains important for this switches are designed with an AND gate connected to Q emerging technology (few hundreds µA) and the tunnel and QB and tri-state inverters connected to the master stage magneto-resistance (120%) remains low, making this input. A single PCRAM cell is used in the NV block. The technology prone to variability. PCRAM cell is unipolar, so a writing scheme is necessary 5.4 NVFF with Pre-Insertion NV Balloon Based on to apply different current levels to perform the set or reset ReRAM Unipolar Technology operation on the PCRAM cell. The sensing circuit compares the voltage on the PCRAM for a given read In [28], an NVFF has been shown by using a current with a reference voltage, depending on the PCRAM pre-inserted NV balloon in front of a flip-flop based on a resistor value, a logic ‘0’ or a logic ‘1’ is obtain on the unipolar ReRAM technology. The scheme of this solution comparator output. The proposed structure is simulated by is illustrated in Fig. 7. using 180 nm, 90 nm, and 45 nm CMOS core processes The NV balloon is connected at the input of the respectively to study the minimal sleeping time allowed to flip-flop through a multiplexer and to the data input by a save power versus the programming current. Indeed, the tri-state inverter. The tri-state inverter is activated during PCRAM technology needs high currents to change the the store phase, whereas the multiplexer allows to by-pass resistor state through set and reset processes. In the the NV-balloon in the normal operation mode and to select the NV balloon during the restore phase. The ReRAM proposed architecture, Rreset=200 kΩ is achieved with a being unipolar, so a writing circuit is mandatory to reset the writing current of 1250 µA and Rset=7 kΩ with a writing current of 600 µA, respectively. This large amount of memory cell through a resistor bridge divider. The set is writing current limit the store process to a single NV performed using the tri-state inverter when necessary. The balloon at a time, this is why a circuit is added to the ReRAM value is sensed by using the resistor bridge divider structure to select in which NV flip-flop the state has to be which is also used for reset. Considering that the output saved. multiplexer may be mixed with a scan multiplexer, the area overhead introduced by the structure is one tri-states 5.3 NVFF with Master-Stage NV Balloon Based on inverter and a 2T/1R branch. STT-MRAM Technology Vdda An NVFF has been proposed using a modified Vdd master-stage flip-flop with a STT-MRAM technology to Slave Latch MP1 MP3 MP2 MP0 [25]−[27] CLK store the flip-flop state . The scheme of this solution CLK is illustrated in Fig. 6. Qm Output MN1 MN0 The NV balloon, based on a couple of complementary MP5 MP4 CLK CLK B B STT-MRAM cells, is introduced in the master latch of the flip-flop. By doing so, since the master latch relies MTJ0 MTJ1 completely on MTJ elements, connection switches can be A=CLK & EN & In avoided. Configuring a state in the MTJ elements of the MN3 MN2 A A B=CLK & EN & In master stage is controlled by an extra logic gate to set MN4 properly A and B inputs. Depending on the CLK, data in Gnd (IN), and EN signals, a current can flow in a bidirectional Fig. 6. Flip-flop architecture with a modified master-stage to manner through both MTJ elements, setting one MTJ and introduce NV capability based on STT-MRAM[25]. resetting the other. The sensing operation is performed with Unipolar ReRAM NV balloon the master-stage latch in two phases. In the first phase, RESET_EN CLK is equal to ‘1’ for pre-charging both MTJ nodes to the MP1 same potential. In the second phase, when CLK is equal to READ_EN MP2 ‘0’, potentials are discharged and the master latch switches IN MEM 0 OUT depending on the resistance values of the right and left MTJ D Q RRAM 1 elements, while the logic value is captured in the slave latch. SAVE_EN Flip‐Flop Unlike FeRAM or PCRAM solutions, STT-MRAM stores (Master – slave) all the data during the normal mode of operations, thanks to

STT-MRAM’s nearly infinite endurance, writing voltage CLK compatibility with the CMOS process, and fast writing time. Fig. 7. Flip-flop architecture with an NV balloon based on [28] The proposed NVFF is simulated by using a 65 nm unipolar ReRAM memory for power-down application .

178 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 The application of this solution to the advanced CMOS process node may need: for this ReRAM technology features, some design adaptation since CMOS nominal voltage is around 1 V; for this design architecture, the improvement of the ReRAM technology to reduce the forming and programming voltages below 1.5 V.

6. Conclusions

In this paper, an overview of NVFFs based on emerging memory technologies is presented. The features of FeRAM, PCRAM, MRAM, and ReRAM memory cells are summarized. The different possible architectures of NVFFs are discussed depending on the balloon latch position and balloon latch structure. The architectural review is proposed Fig. 8. Flip-flop architecture with a modified slave stage based on in a context of power-down applications, where the content bipolar ReRAM memory for power-down application[29]. of the flip-flop is saved in an NV balloon before power down and is restored after power up. The use of such The proposed NVFF is simulated on a 65 nm CMOS structure does not require any biasing during the power-off core process under 1.2 V. It is important to note that the set in comparison to the retention flip-flop employing a volatile and reset voltages are compatible with CMOS voltages and balloon latch. The development of such solutions could be the write process can be performed with currents around a few tens of µA in less than 10 ns. A remaining issue when of the prime interest for deploying IoT. dealing with this technology is the forming step that requires high voltages regarding set/reset voltages. Acknowledgment Knowing that this technology is still in its infancy, the Authors thank all participants of the project “Design and development on forming free devices could overcome this Demonstration of Digital IP Based on Emerging Non-Volatile problem. Memories” (Agence Nationale de la Recherche funding) for 5.5 NVFF with Modified Slave Stage Based on ReRAM fruitful discussions on the distributed emerging memory in logic concept. Bipolar Technology An NVFF has been proposed by using a modified slave References stage based on a unipolar ReRAM technology[29]−[31]. The scheme of this solution is illustrated in Fig. 8. [1] International technology roadmap for semiconductors. The NV balloon is introduced in the slave stage of the [Online]. Available: http://www.nist.gov/pml/div683/ flip-flop on the foot node of both latch inverters. The NV conference/upload/Diebold_final.pdf. block is composed of two ReRAM cells that store opposite [2] D. Roberts, T. Kgil, and T. Mudge, “Using non-volatile states. The write circuit is designed with tri-state inverters memory to save energy in servers,” in Proc. of the Conf. on Design, Automation and Test in Europe, Nice, 2009, pp. connected to the flip-flop outputs Q and Q that are only 743–748. activated during the store phase. The restore phase is [3] M. Zwerg, A. Baumann, R. Kuhn, M. Arnold, R. Nerlich,M. performed using a differential current sensing on the both Herzog, R. Ledwa, C. Sichert, V. Rzehak, P. Thanigai, and branches of the latch. Sensing is performed in two phases: B. O. Eversmann, “An 82μA/MHz with one phase consists in pre-charging the internal nodes of the embedded FeRAM for energy-harvesting applications,” in slave latch to VDD and during the second phase internal Digest. of Solid-State Circuits Conf. Technical Papers, San nodes are discharged to the ground through the resistive Francisco, 2011, pp. 334–336. cells, with the slave latch performing the amplification. It is [4] M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. important to note that forming, programming, and reading Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, voltages are handle with a dynamic VDD. S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, “Nonvolatile The proposed solution is simulated on a 180 nm CMOS logic-in-memory array processor in 90 nm MTJ/MOS core process with a 1.8 V nominal voltage. Forming and achieving 75% leakage reduction using cycle-based power programming voltages are achieved rising VDD to 2.4 V, gating,” in Digest. of Solid-State Circuits Conf. Technical whereas read and normal operations can be performed Papers, San Francisco, 2013, pp. 194–195. under the nominal voltage of 1.8 V and can be reduced to [5] Y. Fujisaki, “Review of emerging new solid-state

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Robertson, “High dielectric constant gate oxides for metal 23, pp. 235203-235203-6. oxide Si transistors,” Reports on Progress in Physics, vol. 69, no. 2, pp. 327–396, 2006. [19] H. Jiao and V. Kursun, “Low-leakage and compact registers Jean-Michel Portal was born in France in with easy-sleep mode,” Journal of Low Power Electronics, 1972. He received his Master and Ph.D. vol. 6, no. 2, pp. 263−279, 2010. degrees in 1995 and 1999, respectively, both [20] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. from University Montpellier 2. From 1999 to Yamada, “A 1-V high-speed MTCMOS circuit scheme for 2000, he was a temporary researcher at power-down application circuits,” IEEE Journal of University Montpellier 2 in the field of FPGA Solid-State Circuits, vol. 32, no. 6, pp. 861–869, 1997. design and test. From 2000 to 2008, he was [21] J. Wang, Y.-P. Liu, H.-Z. Yang, and H. Wang, “A an assistant pprofessor at the University of compare-annd-write ferroelectric nonvolatile flip-flop for Provence, Polytech’Marseille (microelectronic design and test)

180 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 and conducted research activities in L2MP in the field of memory Damien Deleruyelle received his M.S. and testing and diagnosis, test structure design, and design for Ph.D. degrees in electrical engineering booth manufacturing. In this position he participates in an industrial from the University of Grenoble, France in prroject on non-volatile memory testing and diagnosis 2001 and 2004, respectively. He is currently (L2MP/ST-microelectronics research project). In 2008, he became an associate professor at IM2NP, a full professor and since 2009 he has heaaded the “Memories Aix-Marseille University, France. His Team” of the Microelectronics and Nano-Sciences of Provence research interests include emerging memories (IM2NP). His research fields cover the design for manufacturing model, andphysical, and electrical and memory design, test, and reliability. He has (co)-authored characterizations. more than 100 papers in international conferences and journals, including ITC, DATE, ESSDERC, ISCAS and is the (co)inventor Yue Zhang was born in China in 1986. He of 3 patents. received the B.S. degree in optoelectronics from Huazhong University of Science and Technology, Wuhan, China in 2009, the M.S. Marc Bocquet received his M.S. and Ph.D. degree in electronic systems for integrated degrees in electrical engineering in 2006 sensors from University of Paris-Sud 11, and in 2009, respectively, both from the France, in 2011. He is currently working University of Grenoble, France. He is towards the Ph.D. degree at the Institut currently an associate professor with the d’Electronique Fondamentale (IEF), University of Paris-Sud 11. Institute of Materials, IM2NP, Aix- His research project involves electrical modeling of nano- Marseille University, France. His research spintronic components and evaluation of new integrated interests include memory model; memory architectures of integrated circuits. design, characterization, and reliability. Wang Kang was born in China in 1987. He received the B.S. degree in electronic and

information engineering from Beihang Mathieu Moreau received the M.S and University, Beijing, China in 2009. He is Ph.D. degrees in micro and nanoelectronics currently working for the co-supervision Ph.D. from Aix-Marseille University, France in degree in microelectronics at Beihang 2007 and 2010, respectively. His doctoral University and University of Paris-Sud 11. research at IM2NP covered numerical His current research interests include both the simulation and compact modeling of theoretical and experimental reliability design for the future VLSI advanced nano-devices, like FinFET, based systems, especially for the emerging storage memory and on new materials (high-κ and III-V computing systems. semiconductors). From 2010 to 2011, he was a teaching assistant at Polytech’Marseille and worked on compact modeling of Jacques-Olivier Klein was born in France organic thin film transistors (OTFT). Since 2012, he has been an in 1967. He received the Ph.D. degree and associate professor with Aix-Marseille University and conducts the Habilitation in electronic engineering his research at IM2NP in the field of circuit design based on from the University of Paris-Sud 11, Orsay, emerging non-volatile memories. France in 1995 and 2009, respectively. He is currently a professor at Institut Hassen Aziza received his B.S. and M.S. d’Electronique Fondamentale, University of degrees in electrical engineering in 1998 and Paris-Sud 11, Orsay, France, where he leads 2001, both from the Aix-Marseille University, the nanocomputing research group focusing on the architecture of France. He received his Ph.D. degree in circuits and systems based on emerging nanocomponents in the electrical engineering in 2004 from the field of nanomagnetism and bio-inspired nanonoelectronics. Dr. University of Marseille, France. In 2005, he Klein is the author of 70 technical papers including 7 invited joined IM2NP, Marseille, France, where he is communications. He served on the conference program committee currently an associate professor. His research like DTIS and GLSVLSI, and served as a reviewer for IEEE Trans. fields cover design, test, and reliability of conventional on Mag., Solid State Electronics, and conferences. He coordinated non-volatile memories (flash & EEPROM) as well as emerging the project ANR-PANINI funded by the French Research Agency memories. He is the co-author of more than 50 papers in and he leads, with Cristell Maneux, the topic “emerging international conferences and journals, including ITC, DATE, technologies” of the research group dedicated to the system on ESSDERC, ISCAS and is the co-inventor of 2 patents. chip and system in package (CNRS GDR SoC-SiP).

PORTAL et al.: An Overview of Non Volatile Flip-Flops Based on Emerging Memory Technologies 181 You-Guang Zhang was born in China in interaction, magnetization reversal in ultrathin films and dot 1963. He received the M.S degree in arrays, ion irradiation patterning of magnetic materials, and now mathematics from Peking University, spin transfer induced GHz magnetization dynamics of MRAM Beijing, China in 1987 and the Ph.D. degree cells and magnetic logic circuits. He has co-authored more than in communication and electronic systems 250 papers, co-holds 6 patents, and was awarded in 2000 the from BUAA, China in 1990, where he is Silver Medal of CNRS for his research achievements. After being currently a professor and director. His the director of IEF in 2010, he is now the executive manager of current research interests include micro- the foundation that is in charge of the Paris-Saclay Excellence electronics and wireless communication. He has participated in Initiative. several projects of NSF and 973 and published a number of papers. In particular, he recently focuses on the wireless channel capacity and network coding using the advanced mathematics. He is also Wei-Sheng Zhao was born in China in 1980. an expert on system-level algorithm and architecture design for He received the Ph.D. degree in physics storage and computing systems. from the University of Paris-Sud 11, France in 2007. From 2004 to 2008, he investigated Claude Chappert received his spintronic logic circuits and designed “Docteurd’Etat” diploma in 1985 from prototypes for hybrid spintronic/CMOS University of Paris-Sud 11, after graduating chips in cooperation with STMicro- from the “Ecole Normale Supérieure de Saint electronics and French Atomic Agency Cloud”. He is now the research director at (CEA). From 2009 to 2014, he led the group of spintronics The French National Center for Scientific integration as a tenured CNRS research scientist and his interests Research (CNRS), with over 30 years include the hybrid integration of nano-devices with CMOS experience in research on magnetic ultrathin circuits and new non-volatile memories (40 nm technology node films and nanostructures, and their applications on ultra high and below) like MRAM circuits and architecture design. Since density recording. One year was spent as a visiting scientist at the 2014, he has been a professor at Beihang University and leads IBM Almaden Research Center, San José, USA. He then started a spintronics research programs. Dr. Zhao has authored or research group on “Nanospintronics” within IEF, University of co-authored more than 100 scientific papers (e.g. Nature Paris-Sud 11 and CNRS. His major interests have been on Communications, Advanced Materials, Nanotechnology, APL, and perpendicular interface anisotropy materials, oscillating interlayer IEEE/ACM Transactions) and he is a senior member of IEEE.