Development of Ferroelectric RAM (FRAM) for Mass Production
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Multilevel-Cell Phase-Change Memory - Modeling and Reliability Framework
MULTILEVEL-CELL PHASE-CHANGE MEMORY - MODELING AND RELIABILITY FRAMEWORK THÈSE NO 6801 (2016) PRÉSENTÉE LE 14 JANVIER 2016 À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEUR LABORATOIRE DE SYSTÈMES MICROÉLECTRONIQUES PROGRAMME DOCTORAL EN GÉNIE ÉLECTRIQUE ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCES PAR Aravinthan ATHMANATHAN acceptée sur proposition du jury: Prof. G. De Micheli, président du jury Prof. Y. Leblebici, Dr M. Stanisavljevic, directeurs de thèse Dr E. Eleftheriou, rapporteur Dr R. Bez, rapporteur Dr J. Brugger, rapporteur Suisse 2016 All birds find shelter during a rain . But eagle avoids rain by flying above the clouds . Problems are common, but attitude makes the difference . — Dr. A. P.J. Abdul Kalam To my parents and wife. Acknowledgements This accomplishment would not have been possible without the wonderful people who have inspired me on my journey towards the PhD. This PhD challenge would have been more of an academic title than a great adventure if not for them. I consider myself fortunate to have spent the last four years of my life in a great research atmosphere for learning, and also working with some exceptional individuals during the course of my doctoral studies. I am greatly indebted to my supervisor, Prof. Yusuf Leblebici, who gave me the independence to pursue my ideas freely, while at the same time mentoring by example. I am especially grateful to my manager, Dr. Evangelos Eleftheriou, for giving me this wonderful opportunity to pursue my PhD thesis with IBM Research. His energy and enthusiasm have been an inspiration for me to aim ever higher in my pursuits. -
Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
ROSS: a Design of Read-Oriented STT-MRAM Storage for Energy
ROSS: A Design of Read-Oriented STT-MRAM Storage for Energy-Efficient Non-Uniform Cache Architecture Jie Zhang, Miryeong Kwon, Chanyoung Park, Myoungsoo Jung, and Songkuk Kim School of Integrated Technology, Yonsei Institute Convergence Technology, Yonsei University [email protected], [email protected], [email protected], [email protected], [email protected] Abstract high leakage power. With increasing demand for larger caches, SRAM is struggling to keep up with the density Spin-Transfer Torque Magnetoresistive RAM (STT- and energy-efficiency requirements set by state-of-the- MRAM) is being intensively explored as a promis- art system designs. ing on-chip last-level cache (LLC) replacement for Thanks to the device-level advantages of STT-MRAM SRAM, thanks to its low leakage power and high stor- such as high-density structure, zero leakage current, and age capacity. However, the write penalties imposed by very high endurance, it comes out as an excellent candi- STT-MRAM challenges its incarnation as a successful date to replace age-old SRAM for LLC design. However, LLC by deteriorating its performance and energy effi- the performance of STT-MRAM is critically sensitive to ciency. This write performance characteristic unfortu- write frequency due to its high write latency and energy nately makes STT-MRAM unable to straightforwardly values. Therefore, an impulsive replacement of SRAM substitute SRAM in many computing systems. with high-density STT-MRAM, simply for increasing In this paper, we propose a hybrid non-uniform cache LLC capacity, can deteriorate cache performance and in- architecture (NUCA) by employing STT-MRAM as a troduce poor energy consumption behavior. -
Non-Volatile Memory Databases
15-721 ADVANCED DATABASE SYSTEMS Lecture #24 – Non-Volatile Memory Databases Andy Pavlo // Carnegie Mellon University // Spring 2016 @Andy_Pavlo // Carnegie Mellon University // Spring 2017 2 ADMINISTRIVIA Final Exam: May 4th @ 12:00pm → Multiple choice + short-answer questions. → I will provide sample questions this week. Code Review #2: May 4th @ 11:59pm → We will use the same group pairings as before. Final Presentations: May 9th @ 5:30pm → WEH Hall 7500 → 12 minutes per group → Food and prizes for everyone! CMU 15-721 (Spring 2017) 3 TODAY’S AGENDA Background Storage & Recovery Methods for NVM CMU 15-721 (Spring 2017) 4 NON-VOLATILE MEMORY Emerging storage technology that provide low latency read/writes like DRAM, but with persistent writes and large capacities like SSDs. → AKA Storage-class Memory, Persistent Memory First devices will be block-addressable (NVMe) Later devices will be byte-addressable. CMU 15-721 (Spring 2017) 5 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor (ca. 1745) (ca. 1827) (ca. 1831) CMU 15-721 (Spring 2017) 6 FUNDAMENTAL ELEMENTS OF CIRCUITS In 1971, Leon Chua at Berkeley predicted the existence of a fourth fundamental element. A two-terminal device whose resistance depends on the voltage applied to it, but when that voltage is turned off it permanently remembers its last resistive state. TWO CENTURIES OF MEMRISTORS Nature Materials 2012 CMU 15-721 (Spring 2017) 7 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor Memristor (ca. 1745) (ca. 1827) (ca. 1831) (ca. 1971) CMU 15-721 (Spring 2017) 8 MERISTORS A team at HP Labs led by Stanley Williams stumbled upon a nano-device that had weird properties that they could not understand. -
MRAM (Magnetoresistive Random Access Memory)
MRAM (MagnetoResistive Random Access Memory) By : Dhruv Dani 200601163 Shitij Kumar 200601084 Team - N Flow of Presentation Current Memory Technologies Riddles Introduction Principle, Structure and Working Working Modes Schematic Overview MRAM v/s Other Memory Elements Applications in Embedded Systems Case Studies Supported Microcontrollers and Companies Constraints References Current Memory Technologies Volatile When the power is switched off the information is lost. Restarting: programs and data need to be reloaded resulting in increase of idle time. Non -Volatile Can retain stored information permanently Stores information that does not require frequent changing. Read/Write/Erase cycles consume a lot of time. Commonly Known Memories Volatile – Static RAM (SRAM), Dynamic RAM (DRAM) Non –Volatile – Flash, EEPROM Riddle - 1 A car component manufacturing company ‘X’ has to built Air Bag systems for a range of cars. The requisites of building such a system are that it has to interact with the various sensors which detect and record passenger weight and are employed in other safety devices on the vehicle which perform various crucial tasks like detecting the impact of the possible collision. Such a real time system requires the memory to be susceptible to continuous reads, writes and overwrites in each clocked interval. As an embedded engineer for this company X which kind of memory would you use to implement such a system? Riddle - 2 The Defense Research and Development Organization of a nation ‘C’ has to build a system which can be employed by them for their military and aerospace applications. These systems at present require constant power supply to maintain various kinds databases consisting of confidential information. -
Non-Volatile Memory Technology Continue to Scale Up
MEMORY Non-volatile Memory Technology Continue to Scale Up The emergence of new Non-Volatile memory technology promises to improve performance, efficiency that matches with ideal characteristics. The article reviews some of new non-volatile memory technologies. PADAM RAO RAM, DRAM and Flash are three Landscape dominating memory technologies and With respect to ideal characteristics of memory each technology has some advantages technology described above, till now all known and disadvantages. The ideal memory S memory/storage technologies address only some technology should have low power of the characteristics. Static RAM (SRAM) is very consumption, high performance, high reliability, fast, but it's expensive, has low density and is not high density, low cost, and the ability to be used in any semiconductor memory application. persistent. Dynamic RAM (DRAM) has better Besides computers, today’s portable electronics densities and is cheaper (but still expensive) at the have become computationally intensive devices as cost of being a little slower, and it's not persistent as the user interface has migrated to a fully well. Disks are cheap, highly dense and persistent, multimedia experience. To provide the but very slow. Flash memory is between DRAM and performance required for these applications, the disk; it is a persistent solid-state memory with higher portable electronics designer uses multiple types of densities than DRAM, but its write latency is much memories: a medium-speed random access higher than the latter. memory for continuously changing data, a high- Fortunately, it is possible to design a memory system speed memory for caching instructions to the CPU, that incorporates all these different technologies in and a slower, non-volatile memory for long-term a single memory hierarchy. -
Eighth Edition (2006) Core Level
International Patent Classification Eighth Edition (2006) Core Level Volume 4 Section H Electricity World Intellectual Property Organization BASIC INFORMATION ON IPC REFORM The eighth edition (2006) of the Classification represents its first publication after the basic period of IPC reform which was carried out from 1999 to 2005. The following major changes were introduced in the Classification in the course of the reform: (a) the Classification was divided into a core and an advanced level, in order to better satisfy the needs of different categories of users; (b) different revision methods were introduced for the core and the advanced level, namely, a three-year revision cycle for the core level and continuous revision for the advanced level; (c) when the Classification is revised, patent documents are reclassified according to the amendments to the core and the advanced levels; (d) additional data illustrating classification entries or explaining them in more detail, such as classification definitions, structural chemical formulae and graphic illustrations, were introduced in the electronic layer of the Classification; (e) general principles of classification and classification rules were reconsidered and revised where appropriate. Industrial property offices are required to classify their published patent documents either at the core level or at the advanced level. The core level represents a relatively small and stable part of the eighth edition. It includes approximately 20,000 entries at hierarchically high levels of the Classification: sections, classes, subclasses, main groups and, in some technical fields, subgroups with a small number of dots. Revision amendments are not included in the core level of the IPC until its next edition. -
A Survey of Circuit Innovations in Ferroelectric Random-Access Memories
A Survey of Circuit Innovations in Ferroelectric Random-Access Memories Ali Sheikholeslami, MEMBER, IEEE, AND P. Glenn Gulak, SENIOR MEMBER, IEEE This paper surveys circuit innovations in ferroelectric memo- and low power consumption and the emergence of new ries at three circuit levels: memory cell, sensing, and architecture. applications such as contactless smart cards and digital A ferroelectric memory cell consists of at least one ferroelectric ca- cameras. pacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its content for Table 1 compares ferroelectric memories with elec- a read operation. Once a cell is accessed for a read operation, its trically erasable and programmable read-only memories data are presented in the form of an analog signal to a sense ampli- (EEPROM’s) and Flash memories, two types of floating-gate fier, where it is compared against a reference voltage to determine memories, in terms of density, read-access time, write-access its logic level. time, and the energy consumed in a 32-bit read/write. En- The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip joying a mature process technology, EEPROM’s and Flash and the device imperfections of ferroelectric capacitors. We review memories [1], [2] are superior to ferroelectric memories in six methods of generating a reference voltage, two being presented terms of density. Also, they require less power compared to for the first time in this paper. These methods are discussed and ferroelectric memories for read operations, a factor that will evaluated in terms of their accuracy, area overhead, and sensing keep them popular in applications that demand numerous complexity. -
Evaluation of Ferroelectric Materials for Memory Applications
Calhoun: The NPS Institutional Archive Theses and Dissertations Thesis Collection 1990-06 Evaluation of ferroelectric materials for memory applications Josefson, Carl Elof Monterey, California: Naval Postgraduate School http://hdl.handle.net/10945/27767 NAVAL POSTGRADUATE SCHOOL Monterey, California k ?' AT)'0p D T I C I I ELECTE1 '- ' TH SI EVALUATION OF FERROELECTRIC MATERIALS FOR MEMORY APPLICATIONS by Carl Elof Josefson June 1990 Thesis Advisor: R. Panholzer Approved for public release; distribution is unlimited. 91 2 28 056 SECURITY CLASSIFICATION OF THIS PAGE RPRDOUETA I Form Approved REPORT DOCUMENTATION PAGE No. 0704-0188 la. REPORT SECURITY CLASSIFICATION lb. RESTRICTIVE MARKINGS Unclassified 2a. SECURITY CLASSIFICATION AUTHORITY 3. DISTRIBUTION /AVAILABILITY OF REPORT Approved for public release; 2b. DECLASSIFICATION /DOWNGRADING SCHEDULE distribution is unlimited. 4. PERFORMING ORGANIZATION REPORT NUMBER(S) 5. MONITORING ORGANIZATION REPORT NUMBER(S) 6a. NAME OF PERFORMING ORGANIZATION C.j. OFFICE SYMBOL 7a. NAME OF MONITORING ORGANIZATION (If appicable) Naval Postgraduate School 9 Naval Postgraduate School 6c. ADDRESS (City, State, and ZIP Code) 7b. ADDRESS (City, State, and ZIP Code) Monterey, CA 93943-5000 Monterey, CA 93943-5000 Ba. NAME OF FUNDING /SPONSORING 8b. OFFICE SYMBOL 9. PROCUREMENT INSTRUMENT IDENTIFICATION NUMBER ORGANIZATION I (If applicable) 8c. ADDRESS (City, State, and ZIP Code) 10. SOURCE OF FUNDING NUMBERS PROGRAM PROJECT TASK WORK UNIT ELEMENT NO. NO. NO. ACCESSION NO. 11. TITLE (Include Security Classification) Evaluation of Ferroelectric Materials for Memory Applications 12. PERSONAL AUTHOR(S) Carl E. Josefson 13a. TYPE OF REPORT 13b. TIME COVERED 14. DATE OF REPORT (YearMonthDay) 15. PAGE COUNT Master's Thesis FROM TO 1990 June I 97 16. -
Phase Change Materials and Phase Change Memory Simone Raoux , Feng Xiong , Matthias Wuttig , and Eric Pop
Phase change materials and phase change memory Simone Raoux , Feng Xiong , Matthias Wuttig , and Eric Pop Phase change memory (PCM) is an emerging technology that combines the unique properties of phase change materials with the potential for novel memory devices, which can help lead to new computer architectures. Phase change materials store information in their amorphous and crystalline phases, which can be reversibly switched by the application of an external voltage. This article describes the advantages and challenges of PCM. The physical properties of phase change materials that enable data storage are described, and our current knowledge of the phase change processes is summarized. Various designs of PCM devices with their respective advantages and integration challenges are presented. The scaling limits of PCM are addressed, and its performance is compared to competing existing and emerging memory technologies. Finally, potential new applications of phase change devices such as neuromorphic computing and phase change logic are outlined. Introduction Properties of phase change materials Novel information storage concepts have been continuously Phase change materials exist in an amorphous and one or developed throughout history, from cave paintings to print- sometimes several crystalline phases, and they can be rapidly ing, from phonographs to magnetic tape, dynamic random and repeatedly switched between these phases. The switching access memory (DRAM), compact disks (CDs), and fl ash is typically induced by heating through optical pulses or elec- memory, just to name a few. Over the last four decades, silicon trical (Joule) heating. The optical and electronic properties technology has enabled data storage through charge retention can vary signifi cantly between the amorphous and crystalline on metal-oxide-silicon (MOS) capacitive structures. -
FUJITSU LIMITED 7-1, Nishishinjuku 2-Chome, Shinjuku-Ku, Tokyo 163-0721 Tel : +81-3-5322-3353 Fax : +81-3-5322-3386
• FRAM is a registered trademark of Ramtron International Corporation. Other company names and brand names are the trademarks or registered trademarks of their respective owners. Japan Marketing Div., Electronic Devices Shinjuku Dai-ichi Seimei Bldg. FUJITSU LIMITED 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721 http://edevice.fujitsu.com/ Tel : +81-3-5322-3353 Fax : +81-3-5322-3386 North and South America Europe Asia Pacific Korea FUJITSU MICROELECTRONICS FUJITSU MICROELECTRONICS FUJITSU MICROELECTRONICS FUJITSU MICROELECTRONICS AMERICA, INC. EUROPE GmbH ASIA PTE LTD. KOREA LTD. 1250 E. Arques Avenue, M/S 333 Pittlerstrasse 47, #05-08, 151 Lorong Chuan, 1702 KOSMO TOWER, Sunnyvale, CA 94088-3470, USA D-63225 Langen, New Tech Park, 1002 Daechi-Dong, Tel : +1-408-737-5600 Germany Singapore 556741 Kangnam-Gu, Seoul Fax : +1-408-737-5999 Tel : +49-6103-690-0 Tel : +65-6281-0770 135-280, Korea http://www.fma.fujitsu.com/ Fax : +49-6103-690-122 Fax : +65-6281-0220 Tel : +82-02-3484-7100 http://www.fme.fujitsu.com/ http://www.fmal.fujitsu.com/ Fax : +82-02-3484-7111 http://www.fmk.fujitsu.com/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. -
A Study About Non-Volatile Memories
Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 29 July 2016 doi:10.20944/preprints201607.0093.v1 1 Article 2 A Study about Non‐Volatile Memories 3 Dileep Kumar* 4 Department of Information Media, The University of Suwon, Hwaseong‐Si South Korea ; [email protected] 5 * Correspondence: [email protected] ; Tel.: +82‐31‐229‐8212 6 7 8 Abstract: This paper presents an upcoming nonvolatile memories (NVM) overview. Non‐volatile 9 memory devices are electrically programmable and erasable to store charge in a location within the 10 device and to retain that charge when voltage supply from the device is disconnected. The 11 non‐volatile memory is typically a semiconductor memory comprising thousands of individual 12 transistors configured on a substrate to form a matrix of rows and columns of memory cells. 13 Non‐volatile memories are used in digital computing devices for the storage of data. In this paper 14 we have given introduction including a brief survey on upcoming NVMʹs such as FeRAM, MRAM, 15 CBRAM, PRAM, SONOS, RRAM, Racetrack memory and NRAM. In future Non‐volatile memory 16 may eliminate the need for comparatively slow forms of secondary storage systems, which include 17 hard disks. 18 Keywords: Non‐volatile Memories; NAND Flash Memories; Storage Memories 19 PACS: J0101 20 21 22 1. Introduction 23 Memory is divided into two main parts: volatile and nonvolatile. Volatile memory loses any 24 data when the system is turned off; it requires constant power to remain viable. Most kinds of 25 random access memory (RAM) fall into this category.