JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 173 An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies (Invited paper) J. M. Portal, M. Bocquet, M. Moreau, H. Aziza, D. Deleruyelle, Y. Zhang, W. Kang, J.-O. Klein, Y.-G. Zhang, C. Chappert, and W.-S. Zhao Abstract⎯Low power consumption is a major issue consumption becomes a major issue in nowadays in nowadays electronics systems. This trend is pushed by electronics systems. In all application domains, memories the development of data center related to cloud services remain a major contributor to power consumption. On one and soon to the Internet of Things (IoT) deployment. hand, server nodes are based on a classical memory Memories are one of the major contributors to power hierarchy going from the register and cache in high consumption. However, the development of emerging performance central processing unit (CPU), through the memory technologies paves the way to low-power design, dynamic random access memory (DRAM) as the primary through the partial replacement of the dynamic random memory to the hard disk drive (HDD) for massive storage. access memory (DRAM) with the non-volatile On the other hand, IoT autonomous objects are built around stand-alone memory in servers or with the embedded or the micro controller unit (MCU), where the memory distributed emerging non-volatile memory in IoT hierarchy is divided in the core memory (register), memory objects. In the latter case, non-volatile flip-flops (NVFFs) for data (static random access memory (SRAM)), and seem a promising candidate to replace the retention instruction (electrically erasable programmable read-only latch. Indeed, IoT objects present long sleep time and memory (EEPROM), flash). NVFFs offer to save data in registers with zero power In this context, emerging memory solutions could open when the application is idle. This paper gives an the way to new design architectures with full or partial overview of NVFF architecture flavors for various replacement of existing memories. A clear target to bring emerging memory technologies. emerging memories in the memory hierarchy is lowering the systems power. This assumption is based on [1] for Index Terms⎯Emerging memory technology, emerging technologies. Indeed technologies like the phase ferroelectric RAM, low power, magnetic RAM, non-volatile flip-flops, phase change RAM, resistive change RAM (PCRAM), spin-transfer torque magnetic RAM RAM (STT-MRAM), and resistive RAM (ReRAM) or ferroelectric RAM (FeRAM) present performances (programming time, voltage, and current and/or endurance 1. Introduction and retention) that could bring significant advantages versus dynamic RAM (DRAM) or flash. With the development of data center related to cloud Server consumption could be lowered with the services and the Internet of Things (IoT), low power introduction of the flash as a bridge between DRAM and HDD, this trend could be even improved with the Manuscript received March 3, 2014; revised May 13, 2014. This work introduction of PCRAM[2]. In the same way, non-volatile was supported by the ANR project DIPMEM under Grant No. (NV) flash memories embedded in MCU can be replaced ANR-12-NANO-0010-04. [3] [4] J. M. Portal, M. Bocquet, M. Moreau, H. Aziza, and D. Deleruyelle are by emerging memories such as FeRAM or MRAM for with Aix-Marseille University and Institut Matériaux Microélectronique the low power purpose. Nanosciences de Provence, CNRS UMR7334, Marseille, France Regarding IoT autonomous objects, power (Corresponding author e-mail: [email protected]). consumption is a key point for their deployments. The Y. Zhang, J.-O. Klein, C. Chappert, and W.-S. Zhao are with Institut d’Electronique Fondamentale, University Paris-Sud 11 and CNRS introduction of emerging memories offers the capability to UMR8622, Orsay 91405, France. bring non-volatility memories through distributed W. Kang and Y.-G. Zhang are with Electronics and Information memories in logic. This concept allows to completely Engineering School, Beihang University, Beijing 100191, China. power down the system, while saving the MCU state and W.-S. Zhao is also with with Electronics and Information Engineering School, Beihang University, Beijing 100191, China. data in the non-volatile memory point. In this context, the Digital Object Identifier: 10.3969/j.issn.1674-862X.2014.02.007 aim of this paper is to give an overview of the non-volatile 174 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 12, NO. 2, JUNE 2014 flip-flops (NVFFs) architecture flavors based on emerging (set and reset operations are performed with the positive non-volatile memory technologies. voltage pulse). Reset current reduction and temperature The remainder of this paper is composed as follows. stability still have to be enhanced for this technology. Section 2 summarizes the emerging memory technologies. 2.3 ReRAM Technologies Section 3 introduces the classical retention flip-flop solution used to save data through power gating techniques. In its simplest form, the ReRAM device relies on Section 4 is devoted to the presentation of the general metal/insulator/metal (MIM) structures whose conductivity architecture and operating phase of NVFF. Section 5 can be electrically switched between high and low resistive presents several architectures based on different states. Regarding the polarity of the programming voltage, technologies. Finally, Section 6 concludes the paper. a classification can be drawn with unipolar memories and bipolar memories. In unipolar oxide resistive RAM 2. Emerging Memory Technologies (OxRAM), reversible switching is achieved thanks to reproducible formation/dissolution of conductive filaments This section is devoted to the overview of the emerging [5],[6] within the resistive oxide. A typical resistive switching memory technologies used to develop NVFF based on a thermal effect shows a unipolar current-voltage architectures. characteristic. During the set operation, a partial dielectric 2.1 FeRAM Technology breakdown occurs in the material and conductive filaments FeRAM is the most mature technology among the are formed. In contrast, they are thermally disrupted during emerging memory technologies. This technology is widely the reset operation because of the high power density used for embedded applications requiring low power since generated locally, similar to a traditional house fuse. its main feature is low-voltage and low-current Bipolar technologies are the conductive bridge RAM programming. FeRAM memory cells are based on a (CBRAM) and programmable metallization cells (PMC) or ferroelectric capacitor (1C) structure, which limit the the bipolar OxRAM. CBRAM and PMC belong to scaling below the 65 nm or 45 nm node. FeRAM utilizes the “nanoionic” memories. MIM-like memory elements consist positive and negative polarization directions corresponding of an inert electrode (W, Pt, etc.), an ionic conductor used to “1” and “0” states for stored data. The memorization as the solid electrolyte (WO3, MoO3, GeSe, AgGeSe, etc.), mechanism is based on the hysteresis loop of the and an active electrode (Ag, Cu, etc.), through an polarization versus the applied voltage. To change the state electrochemical reaction, ions (Ag+, Cu+, etc.) diffusing of the FeRAM capacitor, a bipolar voltage needs to be within the electrolyte. In bipolar OxRAM, the memory applied to switch domains from a positive remnant effect occurs in specific transition metal oxides (TiOx, polarization to a negative remnant polarization. Positive HfOx) due to a migration of ions (oxygen ions), which are and negative remnant polarizations are defined when the typically described by the motion of the corresponding linear polarization is equal to 0, i.e., the applied voltage is vacancies. null. 2.4 MRAM Technologies 2.2 PCRAM Technology MRAM is one of the most promising technologies for PCRAM, also known as the PCM or PRAM technology, the future logic and memory applications[7]. It is built in a is used mainly for stand-alone memories and is seen as a hybrid architecture composed of basic storage elements and potential candidate to be introduced in the memory complementary metal-oxide-semiconductor transistor hierarchy as the mass-storage memory. The memory cell is (CMOS) parts. The basic storage element of MRAM is based on a capacitor like (1C) structure, where generally referred to the magnetic tunnel junction (MTJ) chalcogenide alloys are sandwiched between two metal nanopillar that is mainly based on the “sandwich” structure: electrodes. The memorization mechanism is based on the a thin oxide barrier separated by two ferromagnetic layers. resistance change between a low resistance state (set As the consequence of the tunnel magneto resistance (TMR) operation) and a high resistance state (reset operation). The effect, the MTJ resistances, Rp and Rap, depend on the low resistance state corresponds to the crystal phase of the relative magnetization orientation of two ferromagnetic chalcogenide alloys whereas the high resistance state layers. With respect to the array architecture, there are two corresponds to the amorphous phase. The phase change is basic types: one transistor with one MTJ (1T-1MTJ) and the obtained by applying a high current through the cell from cross point[7],[8]. The 1T-1MTJ architecture is the most the bottom electrode to the top, to heat the chalcogenide easy-understanding form where each MTJ is connected in alloys above the melting temperature (amorphous phase) or series with