TPU 2735 Teletext Processor ITT Semiconductors

TPU 2735 Teletext Processor

Edition Jan. 13, 1993 6251-312-4E ITT Semiconductors TPU 2735

Contents

Page Section Title

4 1. Introduction

5 2. Functional Description

6 3. Specifications 6 3.1. Outline Dimensions 6 3.2. Pin Connections 6 3.2.1. 40-Pin DIL Plastic Package 7 3.2.2. 44-Pin PLCC Package 8 3.3. Pin Descriptions 10 3.4. Pin Circuits 11 3.5. Electrical Characteristics 11 3.5.1. Absolute Maximum Ratings 11 3.5.2. Recommended Operating Conditions 13 3.5.3. Characteristics of the Digital Section 13 3.5.4. Characteristics, RGB Interface 14 3.5.5. Characteristics of the External RAM

15 4. Various Operation Modes of the TPU 2735 15 4.1. The Menu Mode 15 4.2. Teletext Display without Interlaced Lines 15 4.3. The Effect of Errors in the Transmission of Teletext Data 15 4.3.1. Errors in the Hamming-Code Protected Data 15 4.3.2. Errors in Data with Parity Check 15 4.4. Multipage Conflict Situation

16 5. RAM Organization

17 6. Controlling the TPU 2735 with the CCU 2030, CCU 2050 or CCU 2070 17 6.1. The Address Commands 18 6.2. The Data Transfer Command 18 6.3. The Status Test Command 18 6.4. The IM Bus Hardware Test/Configuration Register

19 7. The Control Registers of Register Chain 2 19 7.1. The Page Request Registers, R-PRx 20 7.2. The Page Selection Register, R-PS 20 7.3. The Subcode Register, R-SC 21 7.4. The Display Selection Register, R-DS 21 7.5. The Data Acquisition Control Register, R-DAC 22 7.6. The Status Indicator Register, R-SI 23 7.7. The Display Control Registers, R-DC1 to R-DC6 27 7.8. The Memory Control Register, R-MC

28 8. The Control Registers of Register Chain 1 28 8.1. The Page Identification Register, R-PI 28 8.2. The Control Bit Register 1, R-CB1 28 8.3. The Control Bit Register 2, R-CB2 28 8.4. The Control Bit Register 3, R-CB3 29 8.5. The Row Flag Register, R-RFx 29 8.6. The Timing of the Register Chains

2 TPU 2735

Contents, continued

Page Section Title

29 9. Two Ways to Select a Page for Display

29 10. Reset of the TPU 2735 Teletext Processor

30 11. Application Notes

33 12. Description of the IM Bus

3 TPU 2735

Teletext Processor for Level 1 Teletext

Note: Tuner IF VCU 2133 or to CRT If not otherwise designated the pin numbers men- Amplifier VCU 2134 tioned refer to the 40-pin DIL package. 64

1. Introduction Teletext Adapter 64 kBit TPU 2735 MCU 2600 256 kBit Teletext MAIN The TPU 2735 is specified to handle Level-1-Teletext in- D RAM Processor Clock Gen. formation (in Germany: Videotext) as it is transmitted to- day by the TV broadcast stations in Great Britain, Ger- many and other European countries. The TPU 2735 is 3 part of the DIGIT 2000 digital TV system and works in CCU 20XX or conjunction with the other VLSI circuits and processors CCU 3000 of this system. This makes the Teletext adapter de- Keyboard Central signed with the TPU 2735 very simple and economic Control Unit (see Fig. 1–1).

The TPU 2735 is an N-channel VLSI MOS circuit, SAA 1250 TBA 2800 housed in a 40-pin Dil plastic package and contains on IR Trans– IR mitter Preamplifier a single silicon chip the following functions:

– one-chip solution of the Teletext processing (except Fig. 1–1: Teletext application block diagram for external RAM) – ghost compensation to eliminate the effects of ghost pictures due to reflections – reduced access time is provided for the Teletext pages by receiving and storing up to eight pages in one go – up to 32 stored pages – automatic language-dependent character selection – switchover facility PAL/NTSC/D2MAC – full level one features (FLOF) support – level 1.5 Spanish Teletext support – largely compatible to the TPU 2732/33

4 TPU 2735

2. Functional Description eight pages for display. The 8-bit character words are transformed into a 6 x 10 dot matrix with PAL or 6 x 8 dot The TPU 2735 whose block diagram is shown in Fig. matrix with NTSC by a character generator (ROM) of 96 2–1, operates according to a rigid timing determined by programmed characters and are displayed in 24 rows of the vertical cycle of the TV receiver. The data acquisition 40 characters each. Optionally, 25 rows can be dis- period starts at line 7 with PAL or line 10 with NTSC and played in PAL/D2MAC. Different character sets are ends at line 22 with PAL or line 21 with NTSC. During this available for eight languages under CCU or transmitter period, the input data is processed by a ghost filter which control, the required character set being selected auto- is able to compensate reflections with short delay time matically by the control bits C12 to C14 of row 0 of the of 0 to 0.8 µs for PAL or 0 to 1 µs for NTSC. In the D2MAC Teletext page displayed. Every tenth line with PAL or mode the acquisition is active from line 1 to 22 and line every eighth line with NTSC a new Teletext row is loaded 313 to 334. from the DRAM into the RAM buffer. When the RAM is not accessed by the TPU 2735, the memory control re- In the Data Acquisition Unit the Teletext information is freshes the memory and handles CCU requests for RAM synchronized and identified. A comparator preselects access. the pages with page numbers that are requested by the CCU 2000 or CCU 3000 Central Control Unit and loads them into the RAM. To eliminate speed problems of the Via the IM bus the CCU can access all RAM locations external Dynamic RAM, the data is buffered in an inter- and controls the TPU 2735 by loading the appropriate nal RAM buffer (Fig. 2–1). The comparator contained in registers in the RAM, so that the TPU 2735 can be used the data acquisition unit decides into which sector of the to display text from other sources. The TPU 2735 can DRAM the data is stored. display a list of contents of the stored eight pages (menu) all by itself.The TPU 2735 can use either one 64 The display period starts at line 48 with PAL or line 50 Kx1 bit Dynamic RAM or one 256 Kx1 bit Dynamic RAM. with NTSC and ends at line 286 with PAL or line 242 with So, RAM capacity is flexible to store up to 32 pages. The NTSC. The display control unit selects one of the stored DRAMs can be standard types (see section 3.).

A017 18 19 21 22 23 24 25 A7 TPU 2735 26 39 A8 V1 Data 27 40 Data Memory 28 1 Acquisition R/W RAM Buffer Unit Control 29 2 CAS 3 Unit 30 Ghost RAS 4 V6 Compensation

38 88 D2– Data Bus 1 Data Bus 2 6 DATA 35 VSUP 5 8 8 GND Start Address Bus

10 Bl. Display Control Central 34 R IM Bus Unit and Timing and G 33 Interface 32 Character Gen. Control B

6 7 8 9 11 12 13 36 31 14 15 16

R G B Bl. H V Res.FM DSD IM Bus Fig. 2–1: Block diagram of the TPU 2735

5 TPU 2735

3. Specifications

3.1. Outline Dimensions

Fig. 3–1: TPU 2735 in 40-pin DIL package Weight approx. 6 g, Dimensions in mm

2.4 10 x 1.27 = 12.7± 0.1 1.2 x 45° 1.27± 0.1 1.2 x 45° 6 140 +0.1

2 2.4

7 39 0.45 ± ± 1.27 0.1 ± 17.4+0.25 0.711 16.5 0.1 10 x 1.27 = 12.7 0.1

17 29 0.254

18 28 1.9 1.5 4.05 17.4+0.25 16.5± 0.1 4.75 ±0.15 0.1

Fig. 3–2: TPU 2735 in 44-pin PLCC package, Weight approx. 2.2 g, Dimensions in mm

3.2. Pin Connections 8 B Output 9 Fast Blanking Output 3.2.1. 40-Pin Dil Plastic Package 10 Fast Blanking Input 1. V3 Video Input 11 Horizontal Blanking Pulse Input/D2SYNC Input 2 V4 Video Input 12 Vertical Blanking Pulse Input 13 Reset Input 3 V5 Video Input 14 IM Bus Data Input/Output 4 V6 Video Input (MSB) 15 IM Bus Ident Input 5 GND 16 IM Bus Clock Input 6 R Output 17 A0 RAM Address Output 7 G Output 18 A1 RAM Address Output

6 TPU 2735

19 A2 RAM Address Output 11 Fast Blanking Output 20 N.C. 12 Fast Blanking Input 21 A3 RAM Address Output 13 Horizontal Blanking Pulse Input / D2SYNC Input 22 A4 RAM Address Output 14 Reset Input 23 A5 RAM Address Output 15 IM Bus Data Input/Output 24 A6 RAM Address Output 16 IM Bus Ident Input 25 A7 RAM Address Output 17 IM Bus Clock Input 26 A8 RAM Address Output 18 A0 RAM Address Output 27 Data Input/Output 19 Leave Vacant 28 Read/Write Output 20 Leave Vacant 29 CAS Output 21 A1 RAM Address Output 30 RAS Output 22 A2 RAM Address Output 31 Skew Data Input 23 Vertical Blanking Pulse Input 32 B Input 24 A3 RAM Address Output 33 G Input 25 A4 RAM Address Output 34 R Input 26 A5 RAM Address Output

35 VSUP 27 A6 RAM Address Output 36 ΦM Main Clock Input 28 A7 RAM Address Output 37 N.C. 29 A8 RAM Address Output 38 D2Data Input 30 Data Input/Output 39 V1 Video Input (LSB) 31 Read/Write Output 40 V2 Video Input 32 CAS Output 33 RAS Output 3.2.2. 44-Pin PLCC Package 34 Skew Data Input 1 V2 Video Input 35 B Input 2 Leave Vacant 36 G Input 3 V3 Video Input 37 R Input 4 V4 Video Input 38 GND 5 V5 Video Input 39 VSUP 6 V6 Video Input (MSB) 40 ΦM Main Clock Input 7 GND 41 Leave Vacant 8 R Output 42 D2 Data Input 9 G Output 43 Leave Vacant 10 B Output 44 V1 Video Input (LSB)

7 TPU 2735

3.3. Pin Descriptions (for 40-pin DIL package) Video from VCU Chroma and Luma from VPU or CVPU Pin 1 to 4 and 39, 40 – Video Inputs V1 to V6 (Fig. 3–4) TPU 2735 VCU Inputs for the digitized composite video signal from the VCU 213x or VAD 2150. The video signal uses a parallel Teletext Gray code, input V6 is the most significant bit (MSB). RGB Bl RGB to CRT 6, 7, 26, Pin 5 – Ground, 0 V 8 27, 32, 28 33, 30, 34 31, 32 Pins 6 to 9 – R, G, B and Fast Blanking Outputs (Fig. 3–6 Ext. and 3–7) RGB 10 9 The R, G and B outputs deliver the Teletext RGB signal Logic 33 to the additional RGB inputs (pins 30 to 32) of the VCU IM Bus 2133 or VCU 2134 in the case of Teletext operation. The 14, RGBE Flag 15, fast blanking output serves for switching the video chan- 16 nel between normal TV and Teletext operation. It must be connected to the fast blanking input (pin 33) of the Fig. 3–3: Signal paths for RGB signals in TPU 2735 VCU. and VCU 2133 or VCU 2134

Pin 10 – Fast Blanking Input (Fig. 3–10) This pin is used to switch over to an external RGB source. The external RGB signal is connected to pins 32 to 34 of the TPU 2735. A low level at pin 10 switches the external RGB signal to the RGB outputs of the TPU 2735 and enables the Fast Blanking Output (pin 9 high). Pin 10 floats to a high level if not connected. The RGBE control bit sets the priority to the external RGB inputs if Insert Mode = FBL (Pin 10) active Low both, teletext and external RGB are active. Two bits in the IM Bus Hardware test/configuration register (see On-Scr . section 6.4.) allow to select the polarity of pin 10 and On- SCART Screen overwrite the fast blank signal.Boxes of TPU text can be (ext. RGB) Display cut into an external RGB signal. The RGB and blanking SCART (Text) ext.RGB outputs are controlled according to the table below. The Display TV TV settings TTM=1 and RGBE=0 are recommended for normal Teletext. For on-screen display, TTM=1 and a) TTM = 1, RGBE= 0 b) TTM = 1, RGBE = 1 RGBE=1 are recommended. For clarification, the connections are shown in Fig. 3–2 and the TV display ap- Fig. 3–4: Priorities on the screen, depending on pearance in Fig. 3–3. TTM and RGBE

TTM RGBE Ext. Fast Internal TPU Fast Blank- RGB Output Screen* Blanking Text Blank- ing Output Pins 6 to 8 Pin 10 ing Pin 9

0 0 1 0 0 pins 32 to 34 Video 0 1 x 0 1 pins 32 to 34 SCART 0 0 0 0 1 pins 32 to 34 SCART

1 0 1 0 0 Text Video 1 0 1 1 1 Text Text 1 0 0 x 1 pins 32 to 34 SCART

1 1 x 1 1 Text Text 1 1 1 0 0 pins 32 to 34 Video 1 1 0 0 1 pins 32 to 34 Scart x = don’t care * = see Fig. 3–2 and 3–3

8 TPU 2735

Pin 11 – Undelayed Horizontal Blanking Pulse/ D2SYNC Pin 29 – CAS Output (Fig. 3–7) Input (Fig. 3–8) This output supplies the Column Address Select (CAS) This pin is connected to the undelayed horizontal blank- signal for the external DRAM. ing output of the deflection processor DPU25xx. For D2MAC teletext mode this pin is also connected to the Pin 30 – RAS Output (Fig. 3–7) D2SYNC output of the D2MAC processor DMA2270. This output supplies the Row Address Select (RAS) sig- (Both pins are tristate outputs). nal for the external DRAM.

Pin 12 – Vertical Blanking Pulse (Fig. 3–8) Pin 31 – Deflection Skew Data Input (Fig. 3–11) This pin is connected to the “combined delayed horizon- This pin can be connected to pin 7 of the DPU 25xx De- tal and vertical blanking pulse” output of the DPU25xx. flection Processor. When DSEN = 1 (see R-DAC of register chain 2) this input controls the horizontal position of Pin 13 – Reset Input (Fig. 3–8) the Teletext RGB signal. Provided a clock is present at pin 36, a low level at pin 9 resets the internal circuitry of the TPU 2735. For nor- Pins 32 to 34 – RGB Inputs (Fig. 3–6) mal operation high level is required. These pins can be connected to an external RGB source. The specified level of these signals is 0 V to 0.7 Pins 14 to 16 – IM Bus Connections V. For other DC levels, an AC coupling has to be used By means of these pins, the TPU 2735 is linked with the to pins 32 to 34, and a clamping circuit in the VCU has CCU. Pins 15 (Ident Input) and 16 (Clock Input) are con- to adjust the DC level. figured as shown in Fig. 3–8. Pin 14 (Data Input/Output) is shown in Fig. 3–9. The data transfer via the IM bus is explained in section 6. Pin 35 – VSUP, 5V Supply Voltage

Pin 17 to 19, 21 to 26 – DRAM Address Outputs (Fig. Pin 36 – ΦM Main Clock Input (Fig. 3–12) 3–7) Via this pin the TPU 2735 is supplied with the required main clock signal of 20.25, 17.7, 14.4 MHz produced by Pin 27 – DRAM Data Input/Output (Fig. 3–10) the MCU 2600 or MCU 2632 Clock Generator IC.

Pin 28 – Read/Write Output (Fig. 3–7) Pin 38 – D2Data Input (Fig. 3–8) This output supplies the R/W control signal to the exter- For D2MAC teletext acquisition this pin is connected to nal DRAM. the D2Data Output of the DMA 2270.

9 TPU 2735

3.4. Pin Circuits (pin numbers for 40-pin DIL the various pins. The integrated protection structures package) are not shown. The letter “E” means enhancement, the letter “D” depletion. The following figures schematically show the circuitry at

VSUP VSUP DD D

EE BIAS E E Fig. 3–5: Pins 1 to GND Fig. 3–9: Pin 14, GND 4, 39, 40, Inputs Input/Output

V +5 V SUP D +0.7 V E E E E Fig. 3–6: Pins 6 to 8 34, 6,7,8 E 33, E and 32 to 34, RGB Fig. 3–10: Pin 27, 32 0 Inputs and Outputs GND Input/Output

V SUP VSUP E D

E E Fig. 3–7: Pins 9, 17, BIAS 18, 19, 21 to 26, 28, Fig. 3–11: Pin 10, 31, GND 29, 30, Outputs GND Inputs

BIAS VSUP VSUP D D D

D E Fig. 3–8: Pins 11 to 13, 15, 16 and 38, In- E Fig. 3–12: Pin 36, GND puts GND Input

10 TPU 2735

3.5. Electrical Characteristics

All voltages refer to pin 5, all pin numbers refer to DIL Package.

3.5.1. Absolute Maximum Ratings

Symbol Parameter Pin No. Min. Max. Unit

TA Ambient Operating Temper- – 0 65 °C ature

TS Storage Temperature – –40 +125 °C

VSUP Supply Voltage 35 – 6 V

VI Input Voltage, all Inputs – –0.3V VSUP –

VO Output Voltage, all Outputs – –0.3V VSUP –

IO Output Voltage, all Outputs – The push-pull outputs are short-cir- – cuit-proof with respect to ground and supply.

3.5.2. Recommended Operating Conditions at TA = 0 °C to 65 °C, fc = 14.3 to 20.3 MHz

Symbol Parameter Pin Min. Typ. Max. Unit Test Conditions No.

VSUP Supply Voltage 35 4.75 5.0 5.25 V

VIH Input Voltage High, 39, 40, VSUP/2 V Video Inputs 1 to 4 +0.3

VIL Input Voltage Low, V Video Inputs VSUP/2 –0.3

VIH Input Voltage High, 10 0.9 V Fast Blank Input

VIL Input Voltage Low, 10 0.5 V Fast Blank Input

VIH Input Voltage High 11, 12, 2.4 V 14, 15, 16

VIL Input Voltage Low 11, 12, 0.8 V 14, 15, 16

VIH Input Voltage High, 13 2.4 V Reset Input

VIL Input Voltage Low, 13 1.2 V Reset Input

VIH Input Current High, 31 –20 µA Skew Data Input

VIL Input Voltage Low, 31 1.2 V Skew Data Input

11 TPU 2735

Recommended Operating Conditions, continued

Symbol Parameter Pin Min. Typ. Max. Unit Test Conditions No.

VI Input Voltage, Analog RGB In- 32, 33, 0.7 1 VPP puts 34

VPP Input Voltage Swing, Clock In- 36 0.8 2.4 VPP put

VDC Input Voltage DC Level, Clock 36 1.5 3.5 V Input

VIH Input Voltage High, 38 2.4 V D2DATA Input

VIL Input Voltage Low, 38 0.8 V D2DATA Input

fc Clock Frequency, PAL 36 17.7 MHz

fc Clock Frequency, NTSC 36 14.4 MHz

fc Clock Frequency, D2MAC 36 20.25 MHz

CL Load Capacitance, DRAM Inter- 17, 18, 30 pF face 19 21 to 30

TS Input Setup Time, Video Inputs, 39, 40, 9 ns ref. to neg. clock edge PAL/NTSC 1 to 4

TH Input Hold Time, Video Inputs 8 ns ref. to neg. clock edge PAL/NTSC

TS Input Setup Time, H Input 11 0 ns ref. to neg. clock edge PAL/NTSC

TH Input Hold Time, H Input PAL/ 11 20 ns ref. to neg. clock edge NTSC

TS Input Setup Time, H Input 11 –10 ns ref. to pos. clock edge D2MAC

TH Input Hold Time, H input D2MAC 11 25 ns ref. to pos. clock edge

TV Pulse Width, V Input 12 58 H (64 µs)

TS Input Setup Time, D2Data Input 38 5 ns ref. to pos. clock edge

TH Input Hold Time, D2Data Input 38 10 ns ref. to pos. clock edge

12 TPU 2735

clock

data inputs

Data inputs timing chart and symbols (ref to neg. clock edge)

3.5.3. Characteristics of the Digital Section, TA = 0 °C to 65 °C

Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions

ISUP Supply Current 35 200 240 at 0 °C

VOH Output Voltage, High Fast 9 3.5 V IO = –0.1 mA Blank Output

VOL Output Voltage, Low Fast Blank 9 0.6 V IO = 1.6 mA Output

VOL Output Voltage, Low IM Bus 14 0.4 V IO = 3.0 mA Data

VOH Output Voltage, High DRAM In- 17, 18, 3.5 V IO = –0.1 mA terface 19, 21 to 30

VOL Output Voltage, Low DRAM In- 17, 18, 0.6 V IO = 1.6 mA terface 19, 21 to 30

CI Input Capacitance 39, 40, 5 pF 1 to 4, 11, 12, 13, 14, 15, 16, 31, 36

3.5.4. Characteristics, RGB Interface

RGB inputs terminated with 75 Ω, RGB outputs terminated with 1 MΩ k20 pF

Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions

Internal RGB Outputs

VOL RGB Output Voltage low 6, 7, 8 20 50 mV

VOH RGB Output Voltage high 6, 7, 8 0.14 VSUP

VOH RGB Output Voltage high 6, 7, 8 630 700 770 mV VSUP = 5V

13 TPU 2735

Characteristics, continued

Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions

∆VOH Differential RGB Output Volt- 6, 7, 8 20 50 mV VSUP = 5V age, High

∆VOL Differential RGB Output Volt- 6, 7, 8 10 mV VSUP= 5V age, Low

VN Noise at RGB Outputs 6, 7, 8 10 mV Teletext Mode, RMS Bw = 6 MHz

External RGB Interface

CI Input Capacitance RGB Inputs 34, 33, 10 pF 32

RON Resistance from RGB Inputs to 6, 7, 8 200 300 Ω ext. inputs on RGB Outputs to 34, 33, 32

∆RON Differential Resistance 6, 7, 8 10 Ω ext. inputs on to 34, 33, 32

ROFF Resistance from RGB Inputs to 6, 7, 8 1 MΩ ext. inputs off RGB Outputs to 34, 33, 32

Bw Bandwidth ext. RGB 6, 7, 8 6 MHz ext. inputs on to 34, 33, 32

α Cross-Talk RGB Inputs to RGB 6, 7, 8 50 dB measured at RGB Outputs, Intern to 34, ext. inputs off 33, 32 Bw = 6 MHz

α Cross-Talk RGB Inputs to RGB 6, 7, 8 35 dB measured at RGB Outputs, Inputs to 34, ext. inputs on 33, 32 Bw = 6 MHz

VN Noise at RGB Outputs 6, 7, 8 5 mV ext. inputs on RMS Bw = 6 MHz

3.5.5. Characteristics of the External RAM

The TPU 2735 is designed to control one dynamic RAS 64 kbit or 256 kbit RAM. The essential RAM characteris- tCASH tics are: tCASL CAS – page mode capability Fig. 3–13: RAS and CAS timing – access time from CAS 100ns

– 256 cycle 4 ms refresh (A0 to A7)

– max. RAS pulsewidth 10 µs PAL NTSC D2MAC

– data in setup time 0ns tCASH 85 ns 104 ns 85 ns

t 113 ns 104 ns 113 ns – address setup time 0ns CASL

14 TPU 2735

4. Various Operation Modes of the TPU 2735 rounding of normal height characters is switched off automatically thus enabling a balanced display of a Teletext page displayed without interlaced lines. The 4.1. The Menu Mode DPU 25.. Deflection Processor Unit can provide appropriate sync signals on request of the CCU. In the menu mode, on the screen of the TV set is displayed a list of contents of the RAM. This list is achieved When a subtitle or a newsflash page is displayed with by displaying row 0 of all sectors at the same time (Fig. both TV picture and Teletext characters on the screen, 4–1). Each row 0 is supplemented by the sector number the TPU 2735 sets a flag (TVS = 1 in R-DC3) to indicate and the requested page number. These two informa- that a display with interlaced lines is referable. tions are placed at the beginning of each row 0 in the same way as the status indicator. The menu is displayed immediately if MEN (R-DC1) is set to 1. The lower part 4.3. The Effect of Errors in the Transmission of of the menu cannot be displayed in double-height mode. Teletext Data

status indicator 4.3.1. Errors in the Hamming-Code Protected Data 0 > 3 1 5 (page header of selected sector) 1 Single errors are corrected and have no further effect. 2 Rows with multiple errors are not loaded into the DRAM. 3 4 The error flag of this page number is set and the TPU 5 1 3 1 1 row 0 of sector 0 tries to read this page when it occurs again without clear- 6 ing the previously acquired data. 7 2 3 1 2 row 0 of sector 1 8 9 3 3 1 4 row 0 of sector 2 4.3.2. Errors in Data with Parity Check 10 11 4 3 1 5 row 0 of sector 3 12 Data with parity errors is not written to the RAM. A parity 13 5 4 1 0 row 0 of sector 4 error sets the error flag of the received page number. 14 The TPU tries to read this page again without clearing 15 6 1 2 0 row 0 of sector 5 the previously acquired data. 16 17 7 2 1 0 row 0 of sector 6 18 19 8 1 5 0 row 0 of sector 7 4.4. Multipage Conflict Situation 20 21 A conflict situation arises if the TPU 2735 receives a new 22 page while the reception of another requested page has 23 not been finished. This situation comes up if requested pages of different magazine numbers are transmitted Fig. 4–1: Display of the menu on the screen with interleaved rows or if the last page of a block of (example) pages from the same magazine is requested.

In a conflict situation only the first page is stored immedi- 4.2. Teletext Display without Interlaced Lines ately. The others have to wait until they are transmitted again. A page which has a conflict with another page In this operation mode, the flicker of the TV screen is re- loses its priority over the following page when it is stored duced. For this, the TPU 2735 can distinguish between and regains priority when all pages involved in a conflict field 1 and field 2 of a TV frame. If the TPU 2735 is sup- have been stored. The selected page does not loose its plied by sync signals without interlace, the character priority to guarantee the updating of the display.

15 TPU 2735

5. RAM Organization sector contain control and status information for the stored teletext page. The external RAM is a 64 kbit or 256 kbit dynamic RAM. A RAM sector is defined as 8 kbit and is capable to store the information of one teletext page. Row 24 of sector 0 in block 0 is used as a register for control information from the control microprocessor. When A 64 kbit RAM holds 8 sectors, a 256 kbit RAM is organ- the TPU2735 is used in FLOF mode sector 0 of each ized as 4 blocks of 8 sectors. block is used to store row 27 teletext information. In the extended character set (ECS) mode the TPU2735 A RAM sector is organized in 25 rows of 40 bytes (row stores row 26 information in the sector preceding the 0 to row 24) and one row of 24 bytes (row 25). The first current acquisition sector. RAM organization is summa- 8 bytes of row 0 and the first 11 bytes of row 25 of each rized in the following table:

Table 5–1: Memory Organization of Sector N Block M

Row Number

row 0 row 26 des.code 0 of sector N+1 in ECS mode, N even only row 1 row 26 des.code 1 of sector N+1 ” . . . . row 14 row 26 des.code 14 of sector N+1 ” row 15 row 8/30* in sector 0, block 0 only row 16 rolling header FLOF, ECS mode, sector 0, block 0 only row 17 row 27* of ttx page in sector 1 in sector 0, block 0 ... 3 row 18 row 27* of ttx page in sector 2 ” . . . . row 23 row 27* of ttx page in sector 7 ” row 24 register chain 2 in sector 0, block 0 only row 24 rolling header in sector 1, block 0 if FLOF, ECS are not selected

*) only designation code 000X is stored

Column 01234567 8 9101112131415161718192021222324252627282930313233343536373839 Row 0 Control Bits Time 1 2 3 4 5 6 7 8 9 10 11 Teletext Data 12 13 14 15 16 17 18 19 20 21 22 23 24 Register Chain 2 25 Register Chain 1

Fig. 5–1: Organization for 64 Kbit RAM, divided into 8 sectors, sector 0 shown

16 TPU 2735

6. Controlling the TPU 2735 with the CCU 2030, CCU 2050 or CCU 2070

TPU and CCU communicate via the IM bus. The CCU check status can read from and write to all RAM locations of the TPU system and can test the status (ready/busy) of the control interface of the TPU. The CCU can control the TPU by addressing the control registers in the RAM. address

The TPU 2735 distinguishes the following types of commands: check status write next address Command IM Bus Address (auto increment) data read a 16-bit write address 7 A (Hex) read a 16-bit read address 7 B (Hex) 8-bit data transfer 7 C (Hex) (read or write) status test 7 D (Hex) Fig. 6–2: Command sequence for writing data hardware test/configuration 7 E (Hex) from TPU to CCU with optional auto increment

Each type of command has its own IM bus address. The TPU has accomplished a CCU command when the busy flags are 0. The maximum busy time is 2.5 ms. The test of the interface status can be followed immediately by another command if the busy flag was low or by a second test if Every data transfer starts with a TPU status check, i.e. the busy flag was high. a read status command with status equal to zero. Next the read or write address is transferred. After the address command another status check is required. The subsequent data is written to or read from the RAM ac- 6.1. The Address Commands cording to the preceding address command. The RAM address is incremented after each data transfer. The 16-bit address consists of four parts:

– block address (0 to 3) 2 bits – sector address (0 to 7) 3 bits – row address (0 to 25) 5 bits check status – column address (0 to 39) 6 bits

Each sector defines the memory locations for a Teletext address page and consists of 25 rows. The rows 0 to 24 can be used as display memory, row 24 and row 25 can be used as control registers. The row and column addresses cor- respond to the position of the character display on the check status screen. The data format of the address (C0 being transmitted first) is: read next address (auto increment)

data B1 B0 S2 S1 S0 R4 ... R0 C5 ... C0

block sector row column address address address address Fig. 6–1: Command sequence for reading data from TPU to CCU with optional auto increment MSB LSB

17 TPU 2735

6.2. The Data Transfer Command 0 0 0 0 0 0 BUI 2 BUI 1 A data command transfers 8 bits of data from the CCU to the TPU or vice versa. The transfer direction depends on the type of the last address command before the data MSB LSB transfer command. A data transfer command following a read address command makes the TPU answer with The busy flags indicate the status of the interface as fol- 8 bits of data. The LSB is transmitted first. lows:

BUI 1 BUI 2 Interface Status D7 D6 D5 D4 D3 D2 D1 D0 0 0 ready for commands 1 0 not ready for commands MSB LSB 1 1 ready only for address commands The RAM address of subsequent data transfer commands is automatically incremented by 1. However, the sector address is not incremented on row address over- 6.4. The IM Bus Hardware Test/Configuration flow. Register

Read Address Command This register allows to control the polarity and the state of the fast blank input signal. The register is write only Write Address Command and is cleared with hardware reset. All unused bits must Data Transfer be set to zero. Command

D7 D6 D5 D4 D3 D2 D1 D0 N 1 N 1+1 N 1+2 N 1+3 N 2 N 2 +1 RAM Address

0000FBP FBO 0 0 Busy 1

Busy 2

Fig. 6–3: Example of a Read/Write command FBP: Fast Blank Polarity: sequence 0 active low (compatible with TPU 2732) 1 active high

6.3. The Status Test Command FBO: Fast Blank Overwrite: 0 no action The TPU answers to this command with an 8-bit status 1 set Fast Blank to 1 (internally) – in this state FBP allows word: to switch the FB signal under program control.

18 TPU 2735

7. The Control Registers of Register Chain 2 R-PRx Page Request Registers

The registers which are used by the CCU to control the address 0/24/2x, 2-byte register TPU have the addresses 0/24/0 to 0/24/30 and are designated as register chain 2. The following pages define the function of the individual registers. An asterisk* D7 D6 D5 D4 D3 D2 D1 D0 marks those bits which can be modified by the TPU. In ** * a write access, each undefined control bit must be set to RESNUFx CF1x NRFx ERFx MSB LSB zero to ensure future compatibility.

Register Chain 2 requested magazine number (binary, 0 0 0 ¢8) address bytes name D7 D6 D5 D4 D3 D2 D1 D0 0/24/0 2 R–PR0 2 2 R–PR1 MSB LSB MSB LSB 4 2 R–PR2 6 2 R–PR3 page request 8 2 R–PR4 tens BCD units BCD 10 2 R–PR5 12 2 R–PR6 requested page number 14 2 R–PR7

x is the sector number where the page is to be stored. 0/24/16 2 R–PS page selection RES: Bit is reserved, set to zero 18 2 R–SC subcode NUFx: no updating flag 20 1 R–DS display selection NUFx = 1 prevents the data acquisition unit of the TPU 21 1 R–DAC data acquistion from writing to the RAM sector x. NUFx can be used in control the HALT mode to protect a received page against modi- 22 2 R–SI status indicator fications. ERFx: error flag 0/24/24 1 R–DC1 The TPU sets ERFx = 1 if a bit error was detected during 25 1 R–DC2 the reception of a Teletext page. The TPU will load a 26 1 R–DC3 display control page with ERFx = 1 once again as soon as it is transmit- 27 1 R–DC4 ted again. ERFx has to be reset when the page request 28 1 R–DC5 register is loaded with a new page number. 29 1 R–DC6 NRFx: new request flag 0/24/30 1 R–MC memory control NRFx has to be set to 1 if the CCU loads a new request into R-PRx. The TPU resets NRFx when the requested page has been received. NRFx influences the page header (rolling header and color) when sector x or the 7.1. The Page Request Registers, R-PRx menu is displayed (see section 7.5. “Data Acquisition Register R-DAC 1”). Each sector of the acquisition block has its own page request register. Their structure can be seen below. They CF1x: conflict flag 1 have to be loaded with the page numbers of the pages CF1x: = 1 indicates a conflict situation where the re- which shall be stored in the according sector when the quested page of sector x is involved. CF1x = 1 leads to TPU receives this page. If more than one register con- a longer access time (see section 4.4. “Multipage Con- tains the same page number the register with the lowest flict Situation”). CF1x has to be reset when the page re- sector number has the highest priority. quest register is loaded with a new page number.

19 TPU 2735

7.2. The Page Selection Register, R-PS 7.3. The Subcode Register, R-SC

The CCU can write a number of a page into R-PS when The subcode register can be used to make the TPU this page has been requested before and shall now be 2735 respond only to transmitted pages with the sub- displayed. R-PS has only effect if SIC = 1. (see section code specified in R-SC. The subcode is normally inter- 9., “Two Ways to Select a Page for Display”). preted as a time code. R-PS Page Selection Register R-SC Subcode Register address 0/24/16, 2-byte register address 0/24/18, 2-byte register

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 * TXIDOPN DPC FLOF OE SSC0SCT2 SCT1 SCT0 SCU3 SCU2 SCU1 SCU0

magazine number (binary, 0 0 0 ¢8) SCT: subcode tens (minutes tens)

D7 D6 D5 D4 D3 D2 D1 D0 SCU: subcode units (minutes units)

D7 D6 D5 D4 D3 D2 D1 D0

tens BCD units BCD SSC2SSC1 SCM1 SCM0 SCH3 SCH2 SCH1 SCH0

page number selected for display SC: subcode control

TXID: Teletext transmission indicator SCM: subcode thousands (hours tens) TXID = 1 if a Teletext line was detected in the vertical flyback interval. SCH: subcode hundreds (hours units) OPN: open OPN = 1 makes the TPU receive a requested page The subcode-control flags SCC 0 to SCC 2 determine whenever it is transmitted. OPN = 0 makes the TPU re- for which sector the subcode is valid. ceive a requested page only if NRF = 1, or errors have been detected (ERF = 1), or C4 = 1 or C8 = 1 (clear page or update page). Subcode Control Flags

DPC: disable parity checking DPC = 1 disables parity checking for the data bytes of all SSC2 SSC1 SSC0 Function received TTX rows. 0 0 0 subcode ignored 0 0 1 subcode valid only for sector 1 FLOF: enable FLOF mode 0 1 0 subcode valid only for sector 2 FLOF = 1 enables reception of rows 24, 27 and 8/30. 0 1 1 subcode valid only for sector 3 1 0 0 subcode valid only for sector 4 OE: odd/even data sampling 1 0 1 subcode valid only for sector 5 OE = 0 samples the odd data bits off the D2DATA signal, 1 1 0 subcode valid only for sector 6 OE=1 samples the even data bits. This bit is used to se- 1 1 1 subcode valid for all sectors lect the TTX Data channel for DMAC VBI TTX Data.

20 TPU 2735

7.4. The Display Selection Register, R-DS 7.5. The Data Acquisition Control Register, R-DAC

R-DS controls the selection of a RAM sector for display. This register controls the slicer, the ghost compensation, The sector number of the displayed sector is either de- the acquisition of the page header and the skew data. termined by the TPU using R-PS or by the CCU. R-DAC Data Acquisition Control Register R-DS Display Selection Register address 0/24/21, 1-byte register address 0/24/20, 1-byte register D7 D6 D5 D4 D3 D2 D1 D0 * TBDDSEN RHA NRT NRH NDA NGC RGC

D7 D6 D5 D4 D3 D2 D1 D0 TBD: vertical blanking delay ******Set to 1 if the delay between horizontal and vertical ERSSIC NRS RPS RPSV MSB LSB blanking pulse is more than 32 ms in field 1 of a TV frame. TBD is used to adapt the TPU 2735 to different sources of the blanking pulses required for synchroniza- Sector number of tion of the TPU (see Fig. 7–1). TBD must be set to 0 in displayed sector D2MAC mode.

DSEN: deflection skew data enable DSEN = 0: the horizontal display start is controlled by pin ERS: error flag of the selected page 11. DSEN = 1: the horizontal display start is controlled ERS = 1 means: the selected page has been received by pin 31 (skew data). with errors. ERS is for internal use of the TPU 2735.

The TPU 2735 is able to adjust the horizontal phase of SIC: start internal comparison the Teletext RGB signal under control of deflection skew The CCU has to set SIC = 1 when a new page number data (DSD) at pin 31. The phase can be adjusted by is loaded into R-PS. SIC is reset by the TPU when RPS steps of 1/16 of the main clock period, i. e. 3.5 ns for PAL is valid. and 4.4 ns for NTSC. DSD provides a Teletext picture without visible jitter even when there is no color burst in the video signal and the DPU is not in the locked mode. For more details refer to the description of the DPU 25.. NRS: new request flag of the selected page Deflection Processor. NRS = 1 means: the selected page has not yet been received. NRS is only for internal use of the TPU. RHA: rolling header always Refer to Table Rolling RPS: requested page is selected NRT: no rolling time The TPU sets RPS to 1 if a page number of one of the Header eight request registers is identical to the selected page Options NRH: no rolling header number of R-PS (see section 9., “Two Ways to Select a Page for Display”). When RPS is set to one and Display (R-DC3) and Acquisition Block (R-MC) are different, the NDA: no data acquisition; current magazine (in parallel magazine mode) is taken Default value is NDA = 0. If NDA = 1, the Teletext data from R-PS. acquisition is switched off.

NGC: no ghost compensation RPSV: RPS flag valid NGC = 1 switches off the ghost compensation Only if RPSV = 1 the value of RPS is valid. When R-PS has been loaded with a new page number the TPU ac- complishes a comparison within 20 ms. The result is RGC: reset ghost compensation; written into R-DS. When a comparison is accomplished Zero written to this bit resets the ghost compensation fil- RPSV is set to 1. The CCU can reset RPSV after loading ter; returns automatically to 1 when the reset command R-PS and then check if RPSV is set to 1 again. is executed.

21 TPU 2735

Rolling Header Options R-SI Status Indicator Register

address 0/24/22, 2-byte register RHA NRT NRH Option

0 0 0 rolling header while searching the selected page, rolling time D7 D6 D5 D4 D3 D2 D1 D0 always 0 0 1 only time is rolling MSB LSB MSB LSB 0 1 0 only central header section is rolling while searching (recommended for NTSC mode) tens BCD units BCD 0 1 1 header does not change indicated page number 1 0 0 rolling header always 1 X 1 ignore parallel magazine D7 D6 D5 D4 D3 D2 D1 D0 control bit (C11 in 8.4.) for rolling header acquisition PMI NVMI

page symbol indicated magazine Composite number Sync (binary, 0 0 0 ¢8) Signal

Horizontal Blanking PMI: programming mode indicator; Pulse tAZ PMI = 1 changes the color of the indicated page number t < 32 µs to blue. PMI can be used to indicate that a new page d number is not complete or has not yet been accepted. TBD = 0 Vertical Blanking t > µ d 32 s Pulse tAB NVMI: non-volatile memory indicator; in Line TBD =1 No. 1 NVMI = 1 changes the color of the indicator to yellow

Fig. 7–1: Timing diagram for the horizontal and vertical blanking pulses tAZ and tAB for two cases Page Symbol List

7.6. The Status Indicator Register, R-SI D6 D5 D4 Page Symbols

The contents of R-SI determine the eight characters of 0 0 0 “space” the status indicator in left corner of row 0. The status indi- 0 0 1 R cator displays three numerals which represent a page 0 1 0 S number. PMI and NVMI determine the mode of their dis- 0 1 1 T play: 1 0 0 = 1 0 1 > Page Symbol List 1 1 0 ? 1 1 1 P

PMI NVMI Display Mode >100 Page Header 0 0 white, steady 1 0 light-blue, steady 0 1 yellow, steady Fig. 7–2: Display of the status indicator in the left 1 1 red, flashing corner of row 0

22 TPU 2735

7.7. The Display Control Registers, R-DC1 to BXT: display boxes (with time-out option) in a R-DC6 TV picture

The flags of R-DC1 determine the way the control information (page header, status indicator, time, menu) is PAH: display page header displayed. The flags of R-DC2 and R-DC4 determine the If PAH is set to 1 by the CCU, a 5 second timer is started. way the Teletext page is displayed. The flags of R-DC5 During these 5 sec the row 0 of the selected sector is dis- determine which character set is used. played. Thereafter, PAH is reset to 0. Time-out can be switched off by TOE = 0. If PAH, TOF and TTM are 1, the R-DC1 Display Control Register 1 row 0 of the selected sector is boxed in the normal TV picture. address 0/24/24, 1-byte register IND: display indicator (with time-out option) D7 D6 D5 D4 D3 D2 D1 D0 similar to PAH, but the first eight characters of row 0 of ***** the selected sector are displayed. TOEMEN TOF BXT PAH IND TIM HLT TIM: display time (with time-out option) similar to PAH, but the last eight characters of row 0 of TOE: timeout enable the selected sector are displayed in white. TOE = 1 enables the automatic reset of BXT, PAH, IND and TIM after 5 s for PAL or 4 s for NTSC. HLT: indicate halt mode If HLT = 1 the last eight characters of the displayed page MEN: display menu header are replaced by a symbol which indicates that MEN = 0 means normal display, and MEN = 1 means the page is not updated. TIM has priority over HLT. that the menu is displayed.

TOF: text off PAH and BXT are influenced by the data acquisition con- TV picture is displayed (BL = 0) trol according to the following table:

Display Behaviour of Updated Pages

Requested Page Sector N is Subtitle Page Clear Page Update Page NRFx Set PAH of Sector N is received selected for display and BXT 0 x x x x x 0 1 0 x x x x 0 1 1 x x x 1 1 1 1 0 1 x x 1 1 1 0 x 1 x 1 1 1 1 x x 0 0

x = don’t care

23 TPU 2735

R-DC2 Display Control Register 2 not reset by the TPU. The CCU may monitor UPI and reset UPI after an update has been detected. address 0/24/25, 1-byte register REV: reveal D7 D6 D5 D4 D3 D2 D1 D0 If REV = 1, the conceal control character 1/8 has no ef- * fect. TTMDW DR MIX UPI REV DLB DHT DLB: display large bottom DLB has no effect if DHT = 0, see DHT. TTM: Teletext mode If TTM = 0, no Teletext data is displayed. The R, G, B in- DHT: double height puts are connected to the R, G, B outputs. The state of DHT = 0 and DW = 0 means normal display. DHT = 1 and the Fast Blanking output depends on the Fast Blanking DLB = 0 means large top. DHT = 1 and DLB = 1 means input and the RGBE control bit (ref. section 7.8.). large bottom. In connection with control character 0/13 If TTM = 1, Teletext data is displayed according to the some characters may not be fourfold high – 0/13 has no status of the control registers. effect.

DW,DR: double width R-DC3 Display Control Register 3 DW = 0 and DHT = 0 means normal display. DW = 1 and DR = 0 displays the left half of the Teletext page in double address 0/24/26, 1-byte register width characters. If DR = 1 and DW = 1, the right half of the screen is shown in double width; any attribute char- D7 D6 D5 D4 D3 D2 D1 D0 acters that are in the left half of the page will have no ef- * TVSDB1 DB0 X X X X X fect. DW = 1 and DHT = 1 means double size display. In this case DR and DLB select 1 of 4 possible display quadrants. TVS: TV synchronization required (mixed mode) The TPU sets TVS = 1 if the displayed Teletext page con- MIX: mixed display sists of mixed data TV/Teletext, e. g. If MIX = 1, characters may be displayed with TV back- MIX = 1, C6 = 1 (subtitle), C5 = 1 (newsflash). ground. The margin background is TV picture (see Table below). DB: Display Block Address (0 to 3) of the current block (8 pages) to display. UPI: update indicator Default value is UPI = 0. UPI is set by the TPU whenever X: for internal use only the page which is selected for display is updated. UPI is Should not be modified via IM bus.

MIXC5 or C6 BXT TOF PAH IND TIM background normal box indicator header time

0 0 x 0 x x x TT TT TT TT TT 0 1 x 0 0 0 – TT – – – 0 0 0 1 0 0 0 – – – – – 0 0 1 1 0 0 0 – TT – – – 1 0 0 x 0 0 0 TV TV TV TV TV 1 1 x 0 0 0 0 TV TT TV TV TV 1 0 1 0 0 0 0 TV TV TV TV TV 1 1 0 1 0 0 0 TV TV TV TV TV 1 1 0 1 1 0 0 TV TT TT TT TT 1 1 0 1 0 1 0 TV TT TT TV TV 1 1 0 1 0 0 1 TV TT TV TV TT 1 1 1 1 0 0 0 TV TT TV TV TV 1 1 1 1 1 0 0 TV TT TT TT TT 1 1 1 1 0 1 0 TV TT TT TV TV 1 1 1 1 0 0 1 TV TT TV TV TT TT = Teletext – = not displayed

24 TPU 2735

R-DC4 Display Control Register 4 UKS: swap UK/US English character set Default value is UKS = 0, (ref. to Table below). address 0/24/27, 1-byte register UKS = 0: The UK character set is displayed in PAL mode. D7 D6 D5 D4 D3 D2 D1 D0 The US character set is displayed in NTSC mode. UKS =1: D2 The US character set is displayed in PAL mode. INO IBL NTSCMAC NTS NHS NFL NCR The UK character set is displayed in NTSC mode.

ECS: Extended character set mode INO: inverted outputs (R, G, B and Fast Blank- Reception of rows x/26 and additional (Spanish) charac- ing) ter set are enabled. The memory organization is changed in order to store the row x/26 for each sector IBL: inverse blanking (please ref. to sect. 5 pg. 16). Two additional control If IBL = 1, the Fast Blanking output is inverted. characters ‘0x0: alpha black’ and ‘0x10: mosaic black’ are processed. Additional characters for the Spanish NTSC: NTSC mode Teletext system are provided, these characters overlay the control characters with bit 7 (MSB) set. D2MAC: D2MAC mode UPEN: update enable NTS: no text suppression Default value is UPEN = 0. NTS = 1 disables control bit C10. UPEN = 1prevents BTX and PAH from being set when the displayed page is updated. Only the update indicator NHS: no header suppression UPI will be set and the software may decide about the NHS = 1 disables control bit C7. way an update is shown on the display. ELS: external language selection NFL: no flash ELS = 1: The selection of the different character sets is NFL = 1 disables control character 0/8. under software control, using the display control register R-DC5 (LS2, LS1 and LS0). NCR: no character rounding ELS = 0: The selection of the different character sets is NCR = 0 means character rounding on, and NCR = 1 is under transmitter control, using the control bits C12, C13 character rounding off. If the TPU 2735 is supplied by a and C14 of the page header. sync signal with non-interlaced lines, character rounding is turned off automatically for normal height characters. LSx: Language select code Double height characters are displayed with character rounding unless NCR = 1. C12 C13 C14 NTSC UKS Character Set selected LS2 LS1 LS0 Mode R-DC5 Display Control Register 5 0 0 0 0 0 English, UK Version address 0/24/28, 1-byte register 0 0 0 1 0 English, US Version 0 0 0 0 1 English, US Version 0 0 0 1 1 English, UK Version D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 x x German 0 1 0 x x Scandinavian IISPUKS ECS UPEN ELS LS 2 LS 1 LS 0 0 1 1 x x Italian 1 0 0 x x French/Belgian 1 0 1 x x Spanish 1 1 0 x x English, US Version IISP: indicator insertion suppression 1 1 1 x x reserved IISP = 1 suppresses the display of the status indicator and displays the memory locations x/0/0 to x/0/7 in- stead. x = don’t care

25 TPU 2735

Pin 11 R-DC6 Display Control Register 6 Hor. Blanking address 0/24/29, 1-byte register

D7 D6 D5 D4 D3 D2 D1 D0 É

É É Pin 31 t Defl. Skew DSDLS HDA HDA HDA HDA HDA HDA D1 Data

tD0 tHDA Page Width ÉÉÉÉÉ DS: double-scan mode DS = 1 doubles the display frequencies. When DS = 1 ÉÉÉÉÉ RGB Out and DSEN = 0, the RGB horizontal period is 567.5 main Fig. 7–3: Horizontal display start in normal scan clock periods for PAL and 515 main clock periods for mode NTSC. tD1 = minimum delay of the horizontal RGB start from DSD at pin 31 (DSEN = 1) DLS: Display lines tD0 = minimum delay of the horizontal RGB start DLS = 0 selects 24 display lines. DLS = 1 selects 25 dis- from horizontal blanking at pin 11 (DSEN = 0) play lines. DLS = 1 is only valid in PAL, D2MAC modes. tD1 = 12.2 µs for PAL/D2MAC and 10.8 µs for NTSC Row flag RRO is used to control line 25, (see section tD0 = 15.6 µs for PAL/D2MAC and 14.6 µs for NTSC 8.5.). DLS also effects the number of lines cleared with the CDS (Clear Display Sector) command (see section 7.8.). Pin 11 Hor. Blanking HDA: horizontal display adjustment A 6-bit binary number can be loaded into HDA to shift the

Teletext picture from the left towards the right edge of the

É ÉÉ

screen. The additional RGB delay generated by HDA is É

É ÉÉ É Pin 31 in steps of 1/4 character. tD1 tD1 Defl. Skew Page Width Data

tD0 tHDA tHDA

ÉÉÉ ÉÉÉÉ

Pins 6 to 8 ÉÉÉÉ ÉÉÉ RGB Out Fig. 7–4: Horizontal display start in double-scan mode tD1 = minimum delay of the horizontal RGB start from DSD at pin 31 (DSEN = 1) tD0 = minimum delay of the horizontal RGB start from horizontal blanking at pin 11 (DSEN = 0) tD1 = 10.4 µs for PAL and 10.8 µs for NTSC tD0 = 6.9 µs for PAL and 6.4 µs for NTSC

Display Timing

Main Clock Double Double Width Pixel Width Page Width Period T Scan (µs) 56.4/49.4 ns PAL/D2MAC 0 0 169.2 ns = 3 ⋅ T 40.6 56.4/49.4 ns PAL/D2MAC 1 0 84.6 ns = 1.5 ⋅ T 20.3 56.4/49.4 ns PAL/D2MAC 0 1 338.3 ns = 6 ⋅ T – 56.4/49.4 ns PAL/D2MAC 1 1 169.2 ns = 3 ⋅ T –

69.8 ns NTSC 0 0 139.7 ns = 2 ⋅ T 33.5 69.8 ns NTSC 1 0 69.8 ns = 1 ⋅ T 16.7 69.8 ns NTSC 0 1 279.4 ns = 4 ⋅ T – 69.8 ns NTSC 1 1 139.7 ns = 2 ⋅ T –

In NTSC mode the Teletext page is about 18% smaller than in PAL mode.

26 TPU 2735

7.8. The Memory Control Register, R-MC CDS: clear display sector; CDS = 1 clears the data part of the selected display sec- R-MC provides an easy way to clear parts of the se- tor. lected RAM sector. Depending on the DLS control bit in R_DC5 of RC2, 24 R-MC Memory Control Register or 25 lines of the sector will be written. Also the “Display Header Options” (ref. to R_DAC in section 7.5) influence address 0/24/30, 1-byte register the write operation: if “Rolling Header” or “Rolling Time” D7 D6 D5 D4 D3 D2 D1 D0 is selected, the respective areas in the rolling header and/or rolling time fields are cleared and the contents of **** the current display page remains unchanged. If CDS is RGBERGBI AB1 ABO SST CDS CR1 CR2 set to 1 the display period of the subsequent field is turned into an erase period: read is turned to write, and data is stuck to blank (0x20). The next field resets CDS RGBE: switch external RGB signal to the to 0. RGB outputs (see section 3.3., pin 10). CR1: clear register chain 1 of the selected display sector RGBI: indicator for external blanking in line 6, i.e. constant external blanking CR2: clear register chain 2 ABx: Address of current acquisition block CR1(2) = 1 clears all bits of all registers of register chain SST: is for testing purposes only 1(2). This is done in the field following the clear com- SST = stop on same page header. SST = 1 makes the mand in line 25, 26. CR1(2) is reset by the TPU when the TPU close a page whenever a new page header of the clear command is executed. Power-up reset makes same magazine is received. Default value is SST = 0. CR2 = 1.

27 TPU 2735

8. The Control Registers of Register Chain 1 C4 clear page: C4 0→1 clears row flags and makes BXT=PAH=1 Each RAM sector has its own registers for internal control purposes. These registers are designated as register chain 1 (of sector x) and have the addresses x/25/0 8.3. The Control Bit Register 2, R-CB2 to x/25/10. They are used for control information of the Teletext transmitter and information about the status of the data acquisition. In a normal Teletext mode the CCU address x/25/3, 1-byte register does not read or modify these registers. The following pages define the function of the individual registers. In D7 D6 D5 D4 D3 D2 D1 D0 a write access, each undefined control bit must be set to zero to ensure future compatibility. C6 C5 MSB LSB MSB LSB

Register Chain 1 of Sector x tens BCD units BCD address bytes name hours of time code x/25/0 2 R–PI page identification C5: newsflash x/25/2 1 R–CB1 control bits 3 1 R–CB2 C : subtitle 4 1 R–CB3 6 x/25/5 6 R–RF row flags only boxed information is displayed and superimposed on a TV picture. 8.1. The Page Identification Register, R-PI address x/25/0, 2-byte register 8.4. The Control Bit Register 3, R-CB3

D7 D6 D5 D4 D3 D2 D1 D0 address x/25/4, 1-byte register

MSB LSBMSB LSB D7 D6 D5 D4 D3 D2 D1 D0

C C C C C C C C row number of the page magazine number 14 13 12 11 10 9 8 7 header (=0)

of the received page C14: language selection (see R-DC5) D7 D6 D5 D4 D3 D2 D1 D0 C13: language selection (see R-DC5) MSB LSB MSB LSB C12: language selection (see R-DC5)

tens BCD units BCD C11: serial magazine mode page number of the received page

C10: inhibit Teletext: inhibits the display of page 8.2. The Control Bit Register 1, R-CB1 C9: out of sequence: this header is not used for the address x/25/2, 1-byte register rolling-header display

D7 D6 D5 D4 D3 D2 D1 D0 C8: update: C8 0→1 makes BXT=PAH=1 C7: suppress header: this header is not displayed C4 MSB LSB The function of C7 is influenced by the “No Header Sup- pression” (NHS) control bit in register R_DC4 of register chain 2. Also the “Display Page Header” (PAH) control tens BCD units BCD bit in register R_DC1 of RC2 overwrites C7. Note that PAH is set every time the page is updated, and must be minutes of time code reset to enable the function of C7.

28 TPU 2735

8.5. The Row Flag Register, R-RFx 8.6. The Timing of the Register Chains address x/25/5, 6-byte register The contents of the register chains 1 and 2 is updated in the TPU only once per field. This is important for a command sequence with commands which rely on the D7 D6 D5 D4 D3 D2 D1 D0 execution of preceding commands, e. g. “a clear display” command followed by new display data. In this example R7R6 R5 R4 R3 R2 R1 R0 a pause of 2 fields is necessary before the new data is written into the RAM: one field for the TPU to recognize the clear command and another field to execute this command.

R15R14 R13 R12 R11 R10 R9 R8

9. Two Ways to Select a Page for Display

R23R22 R21 R20 R19 R18 R17 R16 First Way Load the selected page number into R-PS and set SIC = 1; if the page number has already been requested, R-DS is loaded automatically with the according sector RR7RR6 RR5 RR4 RR3 RR2 RR1 RR0 number and RPS is set to 1; if RPS remains 0, the CCU has to load one of the eight R-PR 0 to 7 with this page number.

RR15RR14 RR13 RR12 RR11 RR10 RR9 RR8 Second Way The CCU compares the selected page number with the contents of R-PR 0 to 7; if the page number is not found in R-PR 0 to 7, one register of R-PR 0 to 7 has to be loaded with the selected page number. The CCU loads RR23RR22 RR21 RR20 RR19 RR18 RR17 RR16 the number of the selected sectors into R-DS.

A row flag is set to 1 by the TPU if the corresponding row The R-PS register and SIC control bit are kept for com- has been received. When a new page is received, all row patibility with TPU 2732. For new software the second flags of the corresponding sector are cleared. way for page selection is recommended. The display unit displays only those rows whose row flags are 1.

The registers x/25/8 to x/25/10 contain the right-hand- 10. Reset of the TPU 2735 Teletext Processor side row flags which are used in NTSC mode. They control the display of the last 8 character positions of each The power-up reset makes TTM = 0 (no Teletext mode) row which are transmitted in separate lines. and CR 2 = 1 (clear register chain 2). A software reset is achieved by setting CR 2 = 1. In PAL/D2MAC mode some of the right-hand side row flags are used when the FLOF or ECS bits are active: rowflag RR0: controls display of row x/24. This flag is under software control rowflag RR4: indicates reception of a row x/27 and is set/ reset by TPU rowflag RR8: indicates reception of one or more rows x/26, set/reset by TPU

29 TPU 2735

11. Application Notes magazine close row. Transmitting this row would solve all of these problems. Problem: Clamping of External RGB Signals Problem: Spanish Teletext The external RGB inputs are fed through the TPU to the VCU. Clamping of these signals is done by the VCU dur- As the decoding of the information transmitted in rows ing the color key pulse. The RGB switches of the TPU 26 is done by the CCU obviously the control program are controlled by the external “Fast Blank” input to the has to check for the reception of any row26. The actual TPU and by internal control bits (TTM, RGBE, please re- row26 processing is only required for the page currently fer to sections 3.3., 6.4.). In some cases the external fast displayed. This should be done in the ‘idle loop’ of the blank signal is switched off during the horizontal blank- control program. There is no other way than polling to ing interval (e.g. PIP insertion and OSD active). In these see if a row26 was received. cases the external RGB inputs are not switched to the The ‘Spanish Teletext Specification’ requires the extra VCU during the blanking interval and the clamping fails. characters to be transmitted with even parity. Therefore To force clamping of the RGB inputs in all modes the col- a true ‘Spanish Teletext Page’ cannot be received with- or key should be ‘ored’ to the external fast blank signal. out errors and will be acquired again and again. (It is not recommended to use the NPC mode.) A way to detect Problem: Conflict flag the reception of a ‘new’ (i.e. different) page is to check the subcode information stored in register chain one. The conflict flag in the page request register is set if the Usually a subcode of all zeros or all ones indicates a TPU273x has opened a page for acquisition and re- non-rolling page. ceives a header row for another page that is requested in some other request register. This usually happens Problem: Initialization when the last page of a magazine is requested. In the case of a conflict the internal logic of the TPU assigns the Initialization of the TPU should always start with a clear highest priority to the page selected for display. Setting of register chain 2 via the CR2 bit in the R_MC register. the ‘no updating’ flag for this page will resolve the con- If the mode is switched to NTSC/D2MAC, setting the ap- flict. (In order to get an ‘open’ page into NUF mode one propriate control bit in register R_DC4 should be the should set NUP and NRF.) Also the behavior of the ac- next action. Since internal clocks of the TPU are quisition circuit is influenced by the open (OPN) bit in the switched by these bits, the next thing should be a clear page selection register. This bit forces the acquisition of all registers in register chain 2 (except the mode regis- circuit to keep pages open and thereby makes conflict ter R_DC4). In case of NTSC mode, it is recommended situations worse. This bit should be zero for normal Tele- to set the NTSC bit, wait for two fields, check that the text acquisition. NTSC bit is still set, and then start the clearing of register chain 2. After this procedure the normal initialization of Continuous long updating times for the ‘time’ field are registers should follow. also influenced by the conflict. Samples for TPU2735-E are available and are marked The World System Teletext Specification reserves a TPU2735-TC18. The logic of these samples is identical Row0 of page 0x?FF (hexadecimal) for the function of to TPU2735-TC15.

30 TPU 2735

Data Sheet Update: ECS 01

In ECS mode the TPU acquires Teletext rows x/26. The 0öÀ memory organization is changed in order to store the row x/26 for each sector (ref. to section 5). Two addition- 1 al control characters “0x0: alpha black” and “0x10: mo- ï. saic black” are processed. Additional characters for the Spanish Teletext system are provided (ref. Fig. 11–1). 2âê These characters overlay the control characters with bit 7 (MSB) set. 3ô ã

4õÜ

5Íä

6ëî

7ûÁ

8ÑÕ

9ÃÇ

10 ↑ È

11 É →

a o 12

13 Ó#

14 ÒÏ

15 Úò

Fig. 11–1: Extended character set for Spanish Teletext system

31 TPU 2735

TPU2735-E Character Set for Eastern Europe Appli- Character Set Assignments Register R-DC5 cation LS UKS=0 UKS=1 TPU2735 will be available with a character set for East- ern European countries. This version of TPU2735 will be 0 English Polish designated TPU2735-E. The only logic changes are for 1 German German control of character sets via register R-DC5 in register 2 Swedish Hungarian chain 2. An NTSC character set will not be supported by 3 Italian Italian TPU2735-E, the UKS bit in R-DC5 allows to select two 4 French French different character set assignments. 5 Polish Polish 6 Turkish Turkish 7 Rumanian Rumanian

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Standard G0 2 Character Set 3

2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13 7/14 English

German

Swedish/ Hungarian Italian

French

Polish

Turkish

Rumanian

ECS 0 Character Set 1

Fig. 11–2: TPU 2735-E character set for Eastern Europe Application

32 TPU 2735

12. Description of the IM Bus

The INTERMETALL Bus (IM Bus for short) was designed to control the DIGIT 2000 ICs by the CCU Central Control Unit. Via this bus the CCU can write data to the ICs or read data from them. This means the CCU acts as a master whereas all controlled ICs are slaves.

The IM Bus consists of three lines for the signals Ident (ID), Clock (CL) and Data (D). The clock frequency range is 50Hz to 170 kHz. Ident and clock are unidirec- tional from the CCU to the slave ICs, Data is bidirec- tional. Bidirectionality is achieved by using open-drain outputs with on-resistances of 150 Ω maximum. The 2.5 kΩ pull-up resistor common to all outputs is incorporated in the CCU.

The timing of a complete IM Bus transaction is shown in Fig. 12–1 and Table 12–1. In the non-operative state the signals of all three bus lines are High. To start a transaction the CCU sets the ID signal to Low level, indicating an address transmission, and sets the CL signal to Low level as well to switch the first bit on the Data line. There- after eight address bits are transmitted beginning with the LSB. Data takeover in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal goes High, initiating the address comparison in the slave circuits. In the addressed slave the IM bus interface switches over to Data read or write, because these functions are correlated to the address.

Also controlled by the address the CCU now transmits eight or sixteen clock pulses, and accordingly one or two bytes of data are written into the addressed IC or read out from it, beginning with the LSB.

The completion of the bus transaction is signalled by a short low-state pulse of the ID signal. This initiates the storing of the transferred data.

It is permissible to interrupt a bus transaction for up to 10 ms.

33 TPU 2735

Table 12–1: Timing of the IM bus signals

Time tIM1 tIM2 tIM3 tIM4 tIM5 tIM6 tIM7 tIM8 tIM9 tIM10 Min. µs 0 3.0 3.0 0 1.5 6.0 0 0 0 3.0

H Ident L

H 16 Clock 12345 678910111213 or 24 L H Data LSB Address MSB LSB Data MSB L

AB C

Section A Section B Section C

tIM10 H Ident L

tIM1 t tIM3 tIM4 tIM5 IM6

tIM2 H Clock L

tIM7 tIM8 tIM9

H Data Address LSB Address MSB Data MSB L

Fig. 12–1: IM bus waveforms

34 TPU 2735

35 TPU 2735

ITT Semiconductors Group Reprinting is generally permitted, indicating the source. How- World Headquarters ever, our consent must be obtained in all cases. Information INTERMETALL furnished by ITT is believed to be accurate and reliable. How- Hans-Bunte-Strasse 19 ever, no responsibility is assumed by ITT for its use; nor for any D-79108 Freiburg (Germany) infringements of patents or other rights of third parties which P.O. Box 840 may result from its use. No license is granted by implication or D-79008 Freiburg (Germany) otherwise under any patent or patent rights of ITT. The informa- Tel. +49-761-517-0 tion and suggestions are given without obligation and cannot Fax +49-761-517-2174 give rise to any liability; they do not indicate the availability of the components mentioned. Delivery of development samples Printed in Germany does not imply any obligation of ITT to supply larger amounts of by Simon Druck GmbH & Co., Freiburg (01/93) such units to a fixed term. To this effect, only written confirma- Order No. 6251-312-4E tion of orders will be binding.

36 End of Data Sheet

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