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Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)

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Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN) Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 1] 3rd Edition Ch. 4 Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 4] 3rd Edition Ch. 5 Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. 3rd Edition Ch. 5 (not in 4th) Week 5 • Microprogrammed Control Unit Design. 3rd Edition Ch. 5 (not in 4th Edition) – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 4] 3rd Edition Ch. 6 • The Memory Hierarchy: Cache Design & Performance. [Chapter 5] Week 8 3rd Edition Ch. 7 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 5] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 7] 3rd Edition Ch. 8 Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2011 11-29-2011 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy of Computer Architecture • Hardware Description: Register Transfer Notation (RTN) • Computer Architecture Vs. Computer Organization • Instruction Set Architecture (ISA): – Definition and purpose – ISA Specification Requirements – Main General Types of Instructions ISA CPU Design – ISA Types and characteristics – Typical ISA Addressing Modes – Instruction Set Encoding – Instruction Set Architecture Tradeoffs – Complex Instruction Set Computer (CISC) – Reduced Instruction Set Computer (RISC) – Evolution of Instruction Set Architectures Chapters 1, 2 (both editions) EECC550 - Shaaban #2 Lec # 1 Winter 2011 11-29-2011 Computing Element Choices • General Purpose Processors (GPPs): Intended for general purpose computing (desktops, servers, clusters..) • Application-Specific Processors (ASPs): Processors with ISAs and architectural features tailored towards specific application domains – E.g Digital Signal Processors (DSPs), Network Processors (NPs), Media Processors, Graphics Processing Units (GPUs), Vector Processors??? ... • Co-Processors: A hardware (hardwired) implementation of specific algorithms with limited programming interface (augment GPPs or ASPs) • Configurable Hardware: – Field Programmable Gate Arrays (FPGAs) – Configurable array of simple processing elements • Application Specific Integrated Circuits (ASICs): A custom VLSI hardware solution for a specific computational task • The choice of one or more depends on a number of factors including: - Type and complexity of computational algorithm (general purpose vs. Specialized) - Desired level of flexibility/ - Performance requirements programmability - Development cost/time - System cost - Power requirements - Real-time constrains The main goal of this course is the study of fundamental design EECC550 - Shaaban techniques for General Purpose Processors EECC550 - Shaaban #3 Lec # 1 Winter 2011 11-29-2011 Computing Element Choices The main goal of this course is the study General Purpose of fundamental design techniques Processors for General Purpose Processors (GPPs): Processor : Programmable computing element that Flexibility runs programs written using a pre-defined set of Application-Specific instructions Processors (ASPs) ISA Requirements → Processor Design Configurable Hardware Programmability / Selection Factors: - Type and complexity of computational algorithms Co-Processors (general purpose vs. Specialized) Application Specific - Desired level of flexibility - Performance Integrated Circuits - Development cost - System cost (ASICs) - Power requirements - Real-time constrains Specialization , Development cost/time Performance/Chip Area/Watt Performance (Computational Efficiency) EECC550 - Shaaban Software Hardware #4 Lec # 1 Winter 2011 11-29-2011 Computing Element Choices: ComputingComputing ElementElement ProgrammabilityProgrammability (Hardware) (Processor) Software Fixed Function: Programmable: • Computes one function (e.g. • Computes “any” FP-multiply, divider, DCT) computable function (e.g. • Function defined at Processors) fabrication time • Function defined after • e.g hardware (ASICs) fabrication Parameterizable Hardware: Performs limited “set” of functions e.g. Co-Processors Processor = Programmable computing element that runs programs written using pre-defined instructions EECC550 - Shaaban #5 Lec # 1 Winter 2011 11-29-2011 Computing Element Choices: SpatialSpatial vs.vs. TemporalTemporal ComputingComputing Spatial Temporal (using hardware) (using software/program running on a processor) Defined by fixed functionality and connectivity of hardware elements Time Hardware Block Diagram Processor Instructions (Program) Processor = Programmable computing element that runs programs written using a pre-defined set of instructions EECC550 - Shaaban #6 Lec # 1 Winter 2011 11-29-2011 MainMain ProcessorProcessor Types/ApplicationsTypes/Applications The main goal of this course is the study of fundamental design techniques for General Purpose Processors • General Purpose Computing & General Purpose Processors (GPPs) – High performance: In general, faster is always better. – RISC or CISC: Intel P4, IBM Power4, SPARC, PowerPC, MIPS ... 64 bit – Used for general purpose software – End-user programmable – Real-time performance may not be fully predictable (due to dynamic arch. features) – Heavy weight, multi-tasking OS - Windows, UNIX – Normally, low cost and power not a requirement (changing) – Servers, Workstations, Desktops (PC’s), Notebooks, Clusters … Increasing Cost/Complexity • Embedded Processing: Embedded processors and processor cores – Cost, power code-size and real-time requirements and constraints – Once real-time constraints are met, a faster processor may not be better – e.g: Intel XScale, ARM, 486SX, Hitachi SH7000, NEC V800... 16-32 bit – Often require Digital signal processing (DSP) support or other application-specific support (e.g network, media processing) – Single or few specialized programs – known at system design time volume Increasing – Not end-user programmable – Real-time performance must be fully predictable (avoid dynamic arch. features) – Lightweight, often realtime OS or no OS – Examples: Cellular phones, consumer electronics .. … • Microcontrollers – Extremely code size/cost/power sensitive 8 bit – Single program – Small word size - 8 bit common Processor = Programmable computing element – Usually no OS that runs programs written using pre-defined instructions – Highest volume processors by far – Examples: Control systems, Automobiles, industrial control, thermostats, ... Examples of Application-Specific Processors (ASPs) EECC550 - Shaaban #7 Lec # 1 Winter 2011 11-29-2011 TheThe ProcessorProcessor DesignDesign SpaceSpace Application specific architectures for performance Embedded Microprocessors Real-time constraints processors GPPs Specialized applications Low power/cost constraints Performance is everything & Software rules Performance The main goal of this course is the Microcontrollers study of fundamental design techniques for General Purpose Processors Cost is everything Chip Area, Power Processor Cost complexity Processor = Programmable computing element EECC550 - Shaaban that runs programs written using a pre-defined set of instructions #8 Lec # 1 Winter 2011 11-29-2011 General Purpose Processor/Computer System Generations Classified according to implementation technology: • The First Generation, 1946-59: Vacuum Tubes, Relays, Mercury Delay Lines: – ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, 18000 vacuum tubes, 1500 relays, 5000 additions/sec (1944). – First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator), 1949. • The Second Generation, 1959-64: Discrete Transistors. – e.g. IBM Main frames • The Third Generation, 1964-75: Small and Medium-Scale Integrated (MSI) Circuits. – e.g Main frames (IBM 360) , mini computers (DEC PDP-8, PDP-11). • The Fourth Generation, 1975-Present: The Microcomputer. VLSI-based Microprocessors (single-chip processor) – First microprocessor: Intel’s 4-bit 4004 (2300 transistors), 1970. – Personal Computer (PCs), laptops, PDAs, servers, clusters … – Reduced Instruction Set Computer (RISC) 1984 Common factor among all generations: All target the The Von Neumann Computer Model or paradigm EECC550 - Shaaban #9 Lec # 1 Winter 2011 11-29-2011 TheThe VonVon NeumannNeumann ComputerComputer ModelModel • Partitioning of the programmable computing engine into components: – Central Processing Unit (CPU): Control Unit (instruction decode , sequencing of operations), Datapath (registers, arithmetic and logic unit, connections, buses …). – Memory: Instruction (program) and operand (data) storage. AKA Program Counter – Input/Output (I/O) sub-system: I/O bus, interfaces, devices. (PC) Based Architecture – The stored program concept: Instructions from an instruction
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