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(12) United States Patent (10) Patent No.: US 9,564.432 B2 Or-Bach Et Al USOO9564432B2 (12) United States Patent (10) Patent No.: US 9,564.432 B2 Or-Bach et al. (45) Date of Patent: Feb. 7, 2017 (54) 3D SEMICONDUCTOR DEVICE AND (58) Field of Classification Search STRUCTURE None See application file for complete search history. (71) Applicant: Monolithic 3D Inc., San Jose, CA (US) (56) References Cited (72) Inventors: Zvi Or-Bach, San Jose, CA (US); U.S. PATENT DOCUMENTS Deepak C. Sekar, San Jose, CA (US); Brian Cronquist, San Jose, CA (US); 3,007,090 A 10, 1961 Rutz Israel Beinglass, Sunnyvale, CA (US); 3,819,959 A 6/1974 Chang et al. Jan Lodewijk de Jong, Cupertino, CA (Continued) (US) FOREIGN PATENT DOCUMENTS (73) Assignee: MONOLITHIC 3D INC., San Jose, EP 126.7594 A2 12/2002 CA (US) EP 1909311 A2 4/2008 (*) Notice: Subject to any disclaimer, the term of this WO 2008/063483 5, 2008 patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. OTHER PUBLICATIONS Wu, B., et al., “Extreme ultraviolet lithography and three dimen (21) Appl. No.: 14/509,288 sional circuits.” Applied Phyisics Reviews, 1, 0.11104 (2014). (22) Filed: Oct. 8, 2014 (Continued) Primary Examiner — Alexander Ghyka (65) Prior Publication Data (74) Attorney, Agent, or Firm — Tran & Associates US 2015/OO61036A1 Mar. 5, 2015 (57) ABSTRACT A semiconductor device, including: a first layer including Related U.S. Application Data monocrystalline material and first transistors, the first tran sistors overlaid by a first isolation layer; a second layer (63) Continuation of application No. 13/355,369, filed on including second transistors and overlaying the first isolation Jan. 20, 2012, now Pat. No. 8,912,052, which is a layer, the second transistors including a monocrystalline (Continued) material; where the second layer includes at least one through layer via to provide connection between at least one (51) Int. Cl. of the second transistors and at least one of the first tran HOIL 27/088 (2006.01) sistors, where the at least one through layer via has a GITC 17/4 (2006.01) diameter of less than 200 nmi; a first set of external connec (Continued) tions underlying the first layer to connect the device to (52) U.S. Cl. external devices; and a second set of external connections CPC ............. HOIL 27/088 (2013.01); GIIC 17/14 overlying the second layer to connect the device to external (2013.01); HOIL 2 1/76254 (2013.01); devices. (Continued) 20 Claims, 276 Drawing Sheets 4540 4550 4542 4544 4554 4546 530 4532 Soxide Soxide Ox N-- N. Sisstrate US 9,564.432 B2 Page 2 Related U.S. Application Data (2013.01); HOIL 2225/06589 (2013.01); HOIL continuation of application No. 13/314.435, filed on 2924/00011 (2013.01); HOIL 2924/00014 Dec. 8, 2011, now Pat. No. 8,709,880, which is a (2013.01); HOIL 2924/01019 (2013.01); HOIL continuation of application No. 13/246,391, filed on 2924/01066 (2013.01); HOIL 2924/01322 Sep. 27, 2011, now Pat. No. 8,153,499, which is a (2013.01); HOIL 2924/10253 (2013.01); HOIL continuation of application No. 13/083,802, filed on 2924/12032 (2013.01); HOIL 2924/12036 Apr. 11, 2011, now Pat. No. 8,058,137, which is a (2013.01); HOIL 2924/12042 (2013.01); HOIL continuation of application No. 12/847,911, filed on 2924/1301 (2013.01); HOIL 2924/1305 Jul. 30, 2010, now Pat. No. 7,960,242, which is a (2013.01); HOIL 2924/13062 (2013.01); HOIL continuation-in-part of application No. 12/792,673, 2924/13091 (2013.01); HOIL 2924/14 filed on Jun. 2, 2010, now Pat. No. 7,964,916, which (2013.01); HOIL 2924/15788 (2013.01); HOIL is a continuation-in-part of application No. 12/706, 2924/181 (2013.01); HOIL 2924/3011 520, filed on Feb. 16, 2010, now abandoned. (2013.01); HOIL 2924/3025 (2013.01) (51) Int. C. (56) References Cited HOIL 2L/762 (2006.01) U.S. PATENT DOCUMENTS HOIL 2/822 (2006.01) HOIL 2L/84 (2006.01) 4,197.555 A 4, 1980 Uehara et al. HOIL 23/525 (2006.01) 4400,715 A 8, 1983 Barbee et al. HOIL 2.3/544 (2006.01) 4.487,635 A 12/1984 Kugimiya et al. 4,522,657 A 6/1985 Rohatgiet al. HOIL 25/065 (2006.01) 4,612,083. A 9, 1986 Yasumoto et al. HOIL 25/18 (2006.01) 4,643,950 A 2/1987 Ogura et al. HOIL 27/02 (2006.01) 4,704,785 A 11/1987 Curran HOIL 27/06 (2006.01) 4,711,858 A 12/1987 Harder et al. 4,721,885 A 1/1988 Brodie HOIL 27/092 (2006.01) 4,732,312 A 3/1988 Kennedy et al. HOIL 27/05 (2006.01) 4,733,288 A 3, 1988 Sato HOIL 27/08 (2006.01) 4,829,018 A 5/1989 Wahlstrom HOIL 27/II (2006.01) 4,854,986 A 8/1989 Raby HOIL 27/12 (2006.01) 4.866,304. A 9, 1989 Yu 4,939,568 A 7, 1990 Kato et al. HOIL 27/118 (2006.01) 4.956,307 A 9, 1990 Pollack et al. HO3K 7/687 (2006.01) 5,012,153 A 4, 1991 Atkinson et al. HO3K 9/0948 (2006.01) 5,032,007 A 7, 1991 Silverstein et al. H03K 19/177 (2006.01) 5,047,979 A 9/1991 Leung HOIL 2/8226 (2006.01) 5,087,585 A 2/1992 Hayashi 5,093,704 A 3, 1992 Sato et al. HOIL 23/248 (2006.01) 5,106,775 A 4/1992 Kaga et al. HOIL 23/528 (2006.01) 5,152,857 A 10, 1992 Ito et al. HOIL 2.3/532 (2006.01) 5,162,879 A 11, 1992 Gill HOIL 23/OO (2006.01) 5,217,916 A 6/1993 Anderson et al. 5,250.460 A 10/1993 Yamagata et al. (52) U.S. C. 5,258,643 A 11/1993 Cohen CPC ...... HOIL 21/8221 (2013.01): HOIL 21/8226 5,265,047 A 11/1993 Leung et al. (2013.01); HOIL 21/84 (2013.01); HOIL 5,266,511 A 11/1993 Takao 23/481 (2013.01); HOIL 23/528 (2013.01); 5,277,748 A 1/1994 Sakaguchi et al. 5,286,670 A 2/1994 Kang et al. HOIL 23/5252 (2013.01); HOIL 23/53214 5,294.556 A 3/1994 Kawamura (2013.01); HOIL 23/53228 (2013.01); HOIL 5,308,782 A 5/1994 Mazure et al. 23/544 (2013.01); HOIL 24/14 (2013.01); 5,312,771 A 5/1994 Yonehara HOIL 25/0657 (2013.01); HOIL 25/18 5,317,236 A 5/1994 Zavracky et al. (2013.01); HOIL 27/0207 (2013.01); HOIL 5,324,980 A 6/1994 Kusunoki 5,355,022 A 10/1994 Sugahara et al. 27/0688 (2013.01); HOIL 27/0694 (2013.01); 5,371,037 A 12/1994 Yonehara HOIL 27/092 (2013.01); HOIL 27/105 5,374,564 A 12/1994 Bruel (2013.01); HOIL 27/10873 (2013.01); HOIL 5,374,581 A 12/1994 Ichikawa et al. 27/10876 (2013.01); HOIL 27/10897 5,424,560 A 6/1995 Norman et al. 5,475,280 A 12/1995 Jones et al. (2013.01); HOIL 27/II (2013.01); HOIL 5,478,762 A 12, 1995 Chao 27/112 (2013.01); H0IL 27/11206 (2013.01); 5,485,031 A 1/1996 Zhang et al. HOIL 27/11803 (2013.01); H03K 17/687 5,498,978 A 3, 1996 Takahashi et al. (2013.01); H03K 19/0948 (2013.01); H03K 5,527.423 A 6/1996 Neville et al. 19/177 (2013.01); HOIL 24/45 (2013.01); 5.535,342 A 7/1996 Taylor 5,554,870 A 9, 1996 Fitch et al. HOIL 24/48 (2013.01); HOIL 27/1108 5,563,084 A 10, 1996 Ramm et al. (2013.01); HOIL 2223/5442 (2013.01); HOIL 5,583,349 A 12/1996 Norman et al. 2223/54426 (2013.01); HOIL 2223/54453 5,583,350 A 12/1996 Norman et al. (2013.01); HOIL 2224/32145 (2013.01); HOIL 5,594,563 A 1/1997 Larson 22.24/45124 (2013.01); HOIL 2224/45 147 5,604,137 A 2f1997 Yamazaki et al. 5,617,991 A 4/1997 Pramanicket al. (2013.01); HOIL 2224/48091 (2013.01); HOIL 5,627,106 A 5, 1997 Hsu 2224/73265 (2013.01); HOIL 2225/06513 5,656,548 A 8/1997 Zavracky et al. (2013.01); HOIL 2225/06517 (2013.01); HOIL 5,656,553 A 8, 1997 Leas et al. 2225/06527 (2013.01); HOIL 2225/06541 5,670,411 A 9, 1997 Yonehara et al. US 9,564.432 B2 Page 3 (56) References Cited 6,475,869 B1 11/2002 Yu 6,476,493 B2 11/2002 Or-Bach et al. U.S. PATENT DOCUMENTS 6.479,821 B1 11/2002 Hawryluk et al. 6,515,511 B2 2, 2003 Sugibayashi et al. 5,681,756 10, 1997 Norman et al. 6,526,559 B2 2, 2003 Schiefele et al. 5,695,557 12, 1997 Yamagata et al. 6,528,391 B1 3, 2003 Henley et al. 5,701,027 12, 1997 Gordon et al. 6,534,352 B1 3, 2003 Kim 5,707,745 1, 1998 Forrest et al. 6,534.382 B1 3, 2003 Sakaguchi et al. 5,714,395 2, 1998 Bruel 6,544,837 B1 4/2003 Divakauni et al.
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