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Soft error
Radiation-Induced Soft Errors in Advanced Semiconductor Technologies Robert C
MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits
Scaling and Technology Issues for Soft Error Rates Allan
Radiation Hardening Efficiency of Gate Sizing and Transistor Stacking Based on Standard Cells
Design of Robust CMOS Circuits for Soft Error Tolerance
Evaluation of Soft Errors Rate in a Commercial Memory Eeprom
Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC) C
ECE 571 – Advanced Microprocessor-Based Design Lecture 17
Managing Correctable Memory Errors on Cisco UCS Servers
Soft Errors of Semiconductors Caused by Secondary Cosmic-Ray Neutrons
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
Circuit Design Methodologies for Soft Error Resilience in Nano-Scaled CMOS Technologies N
Memory and Logic Soft Error Improvement Using Phase Transition
FPGA‐SRAM Soft Error Radiation Hardening
Soft Error Rate Reduction Using Redundancy Addition and Removal
Circuit and Layout Techniques for Soft-Error-Resilient Digital Cmos Circuits
Radiation Induced Soft Errors in Integrated Circuits
Soft Error Rate Simulation and Initial Design Considerations of Neutron
Top View
Memory Errors in Modern Systems the Good, the Bad, and the Ugly
Error Correction Code in Soc FPGA-Based Memory Systems
Local Susceptibility Against Soft Errors in Dynamic Random Access Memories (Drams) Analyzed by Nuclear Microprobes
Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data
A Memory Soft Error Measurement on Production Systems∗
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor Christopher Weaver1, Joel Emer1, Shubhendu S
Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field
Enhancing Robust SEU Mitigation with 28-Nm Fpgas
Soft Error Tolerance in Memory Applications
Fault Tolerance and Security
The Importance of ECC Memory in Your Substation Computer
Soft Error Rate Reduction Using Redundancy Addition and Removal
Soft Errors in Broadcom Switch Devices
Multi-Bit Error Tolerant Caches Using Two-Dimensional Error Coding
Temporal Filtering with Soft Error Detection and Correction Technique for Radiation Hardening Based on a C-Element and BICS Daniel Gomez Toro
Soft Error Trends and Mitigation Techniques in Memory Devices
Error Correction for Soft Errors Dhanushya T* and Latha T Department of Electronics and Communication Engineering, St
Soft Errors a Curse from the Heavens
BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics
DRAM Errors in the Wild: a Large-Scale Field Study
Reliability-Book-2013-Ch 33
The Soft Error Problem: an Architectural Perspective Shubhendu S
Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications
Towards Soft Errors∗
Design and Analysis Methodologies to Reduce Soft Errors in Nanometer Vlsi Circuits
Blockhammer: Preventing Rowhammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows A
On the Radiation-Induced Soft Error Performance of Hardened Sequential Elements in Advanced Bulk CMOS Technologies N
Soft Errors: Modeling and Interactions With
Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection
Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Except Where Reference Is Made to the Work of Others, the Work De
SOFT-ERROR SUSCEPTIBILITY of Finfet Srams VOLUME 18 NO
Soft-Error Resilience Framework for Reliable and Energy-Efficient CMOS Logic and Spintronic Memory Architectures
Introduction to Single-Event Upsets
Blockhammer: Preventing Rowhammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows A
Reducing Data Cache Susceptibility to Soft Errors
Soft Error Analysis and Mitigation at High Abstraction Levels
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Built-In Soft Error Resilience for Robust System Design