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Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications

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Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications Journal of Electronic Testing (2020) 36:255–269 https://doi.org/10.1007/s10836-020-05864-7 Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications Ambika Prasad Shah1,2 · Santosh Kumar Vishvakarma2 · Michael Hubner¨ 3 Received: 24 June 2019 / Accepted: 13 February 2020 / Published online: 6 March 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020 Abstract Soft error in SRAM cell is one of the major reliability concern under aerospace radiation environment. A soft error occurs in SRAM cell due to charged particle strikes on sensitive nodes. In this paper, a radiation hardened asymmetric 10T (AS10T) SRAM cell is presented to enhance the soft error hardening. The proposed cell uses read decoupled path to improve read static noise margin (RSNM) and voltage booster connected between storage nodes to improve node capacitance and hence enhanced radiation hardening. The proposed AS10T cell has a 75.83% higher critical charge as compared to 6T SRAM cell. For validation of soft error hardening of the proposed cell, soft error rate ratio with supply voltage and temperature change is calculated and it is found that the AS10T has 6.41× and 3.2× less soft error rate ratio compared to 6T SRAM cell, respectively. To better assess soft-error resilience and performance of the cell, we introduce reliability stability to energy area product (RSEAP) ratio as a performance metric. Our analysis indicates that AS10T cell has 2.83×,1.6×, and 1.36× higher RSEAP as compared to 6T, RD8T, and AS8T SRAM cells, respectively. Keywords SRAM cell · Soft error · Critical charge · Static noise margin · Soft error rate ratio 1 Introduction and increased transistor density [18]. This makes the SRAM cells is affected by the external particle radiations SRAM occupies a considerable portion of the total chip which causes the soft-error [9, 11]. The single event upset area in the modern VLSI designs [6]. SRAMs have been (SEU) induced by radiation particles in the terrestrial and extensively accepted in aerospace systems for data storage aerospace applications is the major failure mechanism that and processing. With the technology scaling, SRAM cells causes the failure of the electronics systems by temporarily are more susceptible to the reliability challenges because flipping the stored data [5, 8]. When the sensitive node of an of reduced supply voltage, decreased critical charge (Qcrit), circuit hits by the high energy particle, the induced charge is collected and accumulated through the drift process. Responsible Editor: K. K. Saluja Once the generated voltage pulse from accumulated charge is above the switching threshold, the stored data of the Ambika Prasad Shah sensitive node flips [7, 22]. ambika [email protected] Previous results show that the conventional 6T SRAM Santosh Kumar Vishvakarma cell as shown in Fig. 1a does not provide adequate reliability [email protected] in aerospace environment. Recently, several research work has been published on SRAM cells. In [3] Chang et al. Michael H¨ubner [email protected] proposed read decoupled 8T SRAM cell (RD8T) which requires separate write and read wordlines and bitlines asshowninFig.1b. This cell improves the read SNM 1 Institute for Microelectronics, Technische Universitat¨ Wien, Vienna 1040, Austria equivalent to hold SNM without affecting other parameters. The storage node capacitance of this SRAM cell is same 2 Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute as 6T SRAM cell; hence even though this cell improves of Technology Indore, Indore M.P., 453552, India the read SNM, still affected by external radiation same as 3 Institute for Informatics, Brandenburg University of Technol- the 6T SRAM cell means no improvement in the soft error ogy, Cottbus-Senftenberg, Cottbus 03046, Germany hardening. In [2], an asymmetric 8T SRAM cell (AS8T) 256 J Electron Test (2020) 36:255–269 WWL VDD VDD WWL M LP M RP Q Q M LA B M RA M LN M RN BL Gnd Gnd BLB (a) WWL VDD VDD WWL M M M R1 LP RP RWL Q x Q M LA B M RA M R2 M LN M RN BL Gnd Gnd BLB RBL (b) WWL VDD VDD WWL M LP M RP Q Q M LA B M RA M LN M RN BL Gnd M V1 Gnd BLB MV2 Voltage Booster (c) Fig. 1 Schematic of standard SRAM Cells (a)6T(b) RD8T [3](c)AS8T[2] to improve soft error hardening is discussed. As shown in pseudo differential single event upset immune 12T (PD12T) Fig. 1c, an minimum sized voltage booster is connected SRAM cell is presented in [1]. This cell has improved between storage nodes to increase the node capacitance and soft error hardening but requires a large area as well as hence improved soft error hardening. However, the read additional control signal requirements. Above discussions SNM of this SRAM cell is still same as 6T SRAM cell. An on SRAM cells strongly motivates for the substitute SRAM J Electron Test (2020) 36:255–269 257 cell which can provide the better soft error resilience as leakage current estimation of SRAM cells are given in the well as improved RSNM while considering area, delay and Section 4. Simulation results and discussion are explain in power of the SRAM cell. Section 5 followed by the conclusion in Section 6. In this paper an asymmetric radiation hardened 10T (AS10T) SRAM cell is proposed. To improve the read stability of the cell, read decoupled circuit is utilized from 2 Proposed Radiation Hardened Asymmetric the RD8T cell whereas voltage booster is adopted from 10T SRAM Cell AS8T to improve the soft error hardening of the cell. The main goal of this paper is to access the soft error Figure 2 shows the proposed radiation hardened asymmetric hardening enhancement analysis of the proposed AS10T 10T (AS10T) SRAM cell. AS10T SRAM cell is designed to SRAM cell. To increase the sensitive node critical charge, improve the soft error performance with minimum possible voltage booster is connected between storing nodes. To area overhead [17]. AS10T SRAM cell is designed by this end we first compare it with existing SRAM cells, adding a minimum sized CMOS inverter (MV1 and MV2, i.e., 6T, RD8T and AS8T, in terms of critical charge at named as voltage booster) between the storage nodes of the sensitive nodes. Further, we calculated critical charge RD8T SRAM cell. The proposed design is inspired by variations when exposed to different temperature and supply RD8T SRAM cell to increase the read SNM because to voltages. Subsequently, the viability of radiation hardening separate read decoupled circuit (MR1 and MR2) for read enhancement of different SRAM cells are measured using operation and AS8T SRAM cell to enhance the soft error soft error rate ratio with supply voltage and temperature hardening. The proposed cell utilizes the advantage of both change namely SERRV and SERRT , respectively, and RD8T and AS8T cells. The role of voltage booster is to our evaluations indicate that the AS10T cell has smallest withstand the effect of particle strike on SRAM cell. The SERRV and SERRT when compared with 6T, RD8T and voltage booster increases the storage node capacitance and AS8T SRAM cells. While soft error susceptibility is the recover the data by pulling back the correct logic state. As key metric for our analysis, to get a better prospective on a matter of fact, AS10T SRAM cell enhances the soft error AS10T SRAM cell, we evaluated Reliability, Stability to immunity because of increased minimum amount of charge Energy Area Product (RSEAP) ratio considering all the to flip the stored data. The level of reliability in the proposed major parameters of the SRAM cell. Our findings indicate cell depends on the direction of voltage booster connection. that, the RSEAP of the proposed SRAM cell is 2.83× higher The control signals for different operations of the proposed than the conventional 6T SRAM cell. We also analyzed AS10T SRAM cell are given in Table 1. the Monte Carlo simulations on critical voltages of storing nodes of various SRAM cells and result demonstrate that the AS10T has less effect of process variations. 3 Radiation Hardening Analysis The organization of rest of the paper is as follows. Methodology Section 2 describes the proposed radiation hardened asym- metric 10T SRAM cell. In Section 3, the theoretical aspects The radiation hardening investigation of the above various of the radiation hardening methodology is discussed. The SRAM cells are carried out using the HSPICE tool. Fig. 2 Proposed radiation WWL VDD V WWL hardened asymmetric 10T DD (AS10T) SRAM cell M M M R1 LP RP RWL Q x Q M LA B M RA M R2 M LN M RN BL Gnd M V1 Gnd BLB RBL MV2 Voltage Booster 258 J Electron Test (2020) 36:255–269 Table 1 Control signals of proposed AS10T SRAM cell for different Also, τf and τr are material dependent time constants. As operations. Write ‘0’ and Write ‘1’ correspond to the storage node Q suggested in [2], for simulation we have used a typical value Operations Control signals of 1 ps and 50 ps for the τr and τf , respectively. In our experiments, the Qcrit is determined by injecting BL BLB WWL RWL RBL current at the sensitive node of the SRAM cells as shown in Fig. 4. This pulse simulate the current induced by the Write 0 0 1 1 0 0 particle strike at the sensitive node. To calculate Qcrit,we Write 1 1 0 1 0 0 determine the minimum magnitude and duration of injected ×× Hold 000current pulse that is sufficient to flip the state of storage Read 1 × 111 node.
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