Journal of Electronic Testing (2020) 36:255–269 https://doi.org/10.1007/s10836-020-05864-7
Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications
Ambika Prasad Shah1,2 · Santosh Kumar Vishvakarma2 · Michael Hubner¨ 3
Received: 24 June 2019 / Accepted: 13 February 2020 / Published online: 6 March 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Soft error in SRAM cell is one of the major reliability concern under aerospace radiation environment. A soft error occurs in SRAM cell due to charged particle strikes on sensitive nodes. In this paper, a radiation hardened asymmetric 10T (AS10T) SRAM cell is presented to enhance the soft error hardening. The proposed cell uses read decoupled path to improve read static noise margin (RSNM) and voltage booster connected between storage nodes to improve node capacitance and hence enhanced radiation hardening. The proposed AS10T cell has a 75.83% higher critical charge as compared to 6T SRAM cell. For validation of soft error hardening of the proposed cell, soft error rate ratio with supply voltage and temperature change is calculated and it is found that the AS10T has 6.41× and 3.2× less soft error rate ratio compared to 6T SRAM cell, respectively. To better assess soft-error resilience and performance of the cell, we introduce reliability stability to energy area product (RSEAP) ratio as a performance metric. Our analysis indicates that AS10T cell has 2.83×,1.6×, and 1.36× higher RSEAP as compared to 6T, RD8T, and AS8T SRAM cells, respectively.
Keywords SRAM cell · Soft error · Critical charge · Static noise margin · Soft error rate ratio
1 Introduction and increased transistor density [18]. This makes the SRAM cells is affected by the external particle radiations SRAM occupies a considerable portion of the total chip which causes the soft-error [9, 11]. The single event upset area in the modern VLSI designs [6]. SRAMs have been (SEU) induced by radiation particles in the terrestrial and extensively accepted in aerospace systems for data storage aerospace applications is the major failure mechanism that and processing. With the technology scaling, SRAM cells causes the failure of the electronics systems by temporarily are more susceptible to the reliability challenges because flipping the stored data [5, 8]. When the sensitive node of an of reduced supply voltage, decreased critical charge (Qcrit), circuit hits by the high energy particle, the induced charge is collected and accumulated through the drift process. Responsible Editor: K. K. Saluja Once the generated voltage pulse from accumulated charge is above the switching threshold, the stored data of the Ambika Prasad Shah sensitive node flips [7, 22]. ambika [email protected] Previous results show that the conventional 6T SRAM Santosh Kumar Vishvakarma cell as shown in Fig. 1a does not provide adequate reliability [email protected] in aerospace environment. Recently, several research work has been published on SRAM cells. In [3] Chang et al. Michael H¨ubner [email protected] proposed read decoupled 8T SRAM cell (RD8T) which requires separate write and read wordlines and bitlines asshowninFig.1b. This cell improves the read SNM 1 Institute for Microelectronics, Technische Universitat¨ Wien, Vienna 1040, Austria equivalent to hold SNM without affecting other parameters. The storage node capacitance of this SRAM cell is same 2 Nanoscale Devices, VLSI Circuit & System Design Lab, Discipline of Electrical Engineering, Indian Institute as 6T SRAM cell; hence even though this cell improves of Technology Indore, Indore M.P., 453552, India the read SNM, still affected by external radiation same as 3 Institute for Informatics, Brandenburg University of Technol- the 6T SRAM cell means no improvement in the soft error ogy, Cottbus-Senftenberg, Cottbus 03046, Germany hardening. In [2], an asymmetric 8T SRAM cell (AS8T) 256 J Electron Test (2020) 36:255–269
WWL VDD VDD WWL
M LP M RP
Q Q M LA B M RA
M LN M RN
BL Gnd Gnd BLB (a)
WWL VDD VDD WWL
M M M R1 LP RP RWL
Q x Q M LA B M RA M R2
M LN M RN
BL Gnd Gnd BLB RBL (b)
WWL VDD VDD WWL
M LP M RP
Q Q M LA B M RA
M LN M RN
BL Gnd M V1 Gnd BLB
MV2 Voltage Booster
(c)
Fig. 1 Schematic of standard SRAM Cells (a)6T(b) RD8T [3](c)AS8T[2] to improve soft error hardening is discussed. As shown in pseudo differential single event upset immune 12T (PD12T) Fig. 1c, an minimum sized voltage booster is connected SRAM cell is presented in [1]. This cell has improved between storage nodes to increase the node capacitance and soft error hardening but requires a large area as well as hence improved soft error hardening. However, the read additional control signal requirements. Above discussions SNM of this SRAM cell is still same as 6T SRAM cell. An on SRAM cells strongly motivates for the substitute SRAM J Electron Test (2020) 36:255–269 257 cell which can provide the better soft error resilience as leakage current estimation of SRAM cells are given in the well as improved RSNM while considering area, delay and Section 4. Simulation results and discussion are explain in power of the SRAM cell. Section 5 followed by the conclusion in Section 6. In this paper an asymmetric radiation hardened 10T (AS10T) SRAM cell is proposed. To improve the read stability of the cell, read decoupled circuit is utilized from 2 Proposed Radiation Hardened Asymmetric the RD8T cell whereas voltage booster is adopted from 10T SRAM Cell AS8T to improve the soft error hardening of the cell. The main goal of this paper is to access the soft error Figure 2 shows the proposed radiation hardened asymmetric hardening enhancement analysis of the proposed AS10T 10T (AS10T) SRAM cell. AS10T SRAM cell is designed to SRAM cell. To increase the sensitive node critical charge, improve the soft error performance with minimum possible voltage booster is connected between storing nodes. To area overhead [17]. AS10T SRAM cell is designed by this end we first compare it with existing SRAM cells, adding a minimum sized CMOS inverter (MV1 and MV2, i.e., 6T, RD8T and AS8T, in terms of critical charge at named as voltage booster) between the storage nodes of the sensitive nodes. Further, we calculated critical charge RD8T SRAM cell. The proposed design is inspired by variations when exposed to different temperature and supply RD8T SRAM cell to increase the read SNM because to voltages. Subsequently, the viability of radiation hardening separate read decoupled circuit (MR1 and MR2) for read enhancement of different SRAM cells are measured using operation and AS8T SRAM cell to enhance the soft error soft error rate ratio with supply voltage and temperature hardening. The proposed cell utilizes the advantage of both change namely SERRV and SERRT , respectively, and RD8T and AS8T cells. The role of voltage booster is to our evaluations indicate that the AS10T cell has smallest withstand the effect of particle strike on SRAM cell. The SERRV and SERRT when compared with 6T, RD8T and voltage booster increases the storage node capacitance and AS8T SRAM cells. While soft error susceptibility is the recover the data by pulling back the correct logic state. As key metric for our analysis, to get a better prospective on a matter of fact, AS10T SRAM cell enhances the soft error AS10T SRAM cell, we evaluated Reliability, Stability to immunity because of increased minimum amount of charge Energy Area Product (RSEAP) ratio considering all the to flip the stored data. The level of reliability in the proposed major parameters of the SRAM cell. Our findings indicate cell depends on the direction of voltage booster connection. that, the RSEAP of the proposed SRAM cell is 2.83× higher The control signals for different operations of the proposed than the conventional 6T SRAM cell. We also analyzed AS10T SRAM cell are given in Table 1. the Monte Carlo simulations on critical voltages of storing nodes of various SRAM cells and result demonstrate that the AS10T has less effect of process variations. 3 Radiation Hardening Analysis The organization of rest of the paper is as follows. Methodology Section 2 describes the proposed radiation hardened asym- metric 10T SRAM cell. In Section 3, the theoretical aspects The radiation hardening investigation of the above various of the radiation hardening methodology is discussed. The SRAM cells are carried out using the HSPICE tool.
Fig. 2 Proposed radiation WWL VDD V WWL hardened asymmetric 10T DD (AS10T) SRAM cell M M M R1 LP RP RWL
Q x Q M LA B M RA M R2
M LN M RN
BL Gnd M V1 Gnd BLB RBL
MV2 Voltage Booster 258 J Electron Test (2020) 36:255–269
Table 1 Control signals of proposed AS10T SRAM cell for different Also, τf and τr are material dependent time constants. As operations. Write ‘0’ and Write ‘1’ correspond to the storage node Q suggested in [2], for simulation we have used a typical value Operations Control signals of 1 ps and 50 ps for the τr and τf , respectively. In our experiments, the Qcrit is determined by injecting BL BLB WWL RWL RBL current at the sensitive node of the SRAM cells as shown in Fig. 4. This pulse simulate the current induced by the Write 0 0 1 1 0 0 particle strike at the sensitive node. To calculate Qcrit,we Write 1 1 0 1 0 0 determine the minimum magnitude and duration of injected ×× Hold 000current pulse that is sufficient to flip the state of storage Read 1 × 111 node. Hence Qcrit is determined by integrating the current pulse for the time interval 0 to Tcrit. Therefore, the injected = Figure 3 summarizes the various steps involved in the charge until Tcrit is sufficient to make VQ VQB. Hence the critical charge analysis with various supply voltages and critical charge can be given as: operating temperatures for different SRAM cells. Tcrit = To inject SEU into the simulated circuits, the current Qcrit Iinj(t)dt (3) 0 induced by α-particles hitting CMOS circuits is modeled by where I (t) is the injected current pulse at sensitive node double exponential current source specified by Eq. 1 [10]. inj for the SEU analysis. Q inj −t/τf −t/τr Iinj(t) = × (e − e ) (1) τf − τr 3.1 Soft Error Rate Or, − − Soft error in any digital circuit occurs when a high energy I (t) = I × (e t/τf − e t/τr ) (2) inj peak particle from chip packaging materials or cosmic radiation where, Qinj is the total amount of charge deposited at the induces enough charge that, if it is collected by a sensitive sensitive node and Ipeak is the peak value of current source. node, can change its logic value of the hit circuit node. Here, soft error rate of circuits are analyzed by considering memory cells. Circuits designed using deep submicron technology are highly susceptible to soft errors due to small critical charge attributed to the lower supply voltages and smaller node capacitances. The soft error resilience of any circuit can be evaluated from its Qcrit. The soft error rate (SER) has exponential dependency on Qcrit and observed that the higher value of Qcrit translates into lower SER [4]. SER can be express as given by Eq. 4:
− Qcrit Q SER ∝ NfluxAe S (4)
where, Nflux is the neutron flux intensity, A is the cross section area of the sensitive node, and QS is the charge collection efficiency of the device in fC. From the above equation, it is observed that, a small increase in Qcrit will significantly reduces the SER.
3.1.1 Intra Cell SERR
For the validation of soft error hardening enhancement on different SRAM cells with the supply voltage and temperature variations, we have computed the intra cell soft error rate ratio (SERR). The intra cell SERR provides information about the soft error hardening of a particular SRAM cell with supply voltage and temperature variations. The approximate soft error rate ratio for subthreshold Fig. 3 Simulation flow of soft-error analysis with different operating and superthreshold operations (SERRV ) is introduced to temperatures and supply voltages analyze the effect of supply variations, and it can be J Electron Test (2020) 36:255–269 259
Fig. 4 Graphical representation defining critical charge. V and Q I VQB are the storage node peak voltages of SRAM cell. Simulation setup for an high Qcrit energy particle hitting a sensitive node VQB storing 1 of Iinj (uA) a SRAM cell is given in inset
0 Time (ns)
0.9 VQ
Vcrit
0 VQB
Tcrit Time (ns) calculated by assuming all other parameters unaffected 3.1.2 Inter Cell SERR except Qcrit for particular operating temperature. Hence, An inter cell SERR is calculated to analyze the soft error SERsuper threshold SER0.9V SERRV = = (5) rate of the SRAM cell as compared to a 6T SRAM cell for SER SER subthreshold @T 0.5V @T the extreme conditions of the supply voltages and operating Or, temperatures. The approximate inter cell soft error rate ratio (SERR#) for the considered SRAM cell normalized ≈ @0.5V − @0.9V SERRV Antiloge Qcrit Q (6) crit @T to 6T SRAM cell is introduced, and it can be calculated by assuming all other parameters unaffected except Q for where SER and SER are the soft error rates, crit 0.5V 0.9V particular operating temperature and supply voltage. Hence, and [email protected] and [email protected] are the critical charges at supply crit crit voltage of 0.5V and 0.9V, respectively. Similarly, the SER# SERR# = (9) SER approximate soft error rate ratio for room and elevated 6T @VDD and T temperature (SERRT ) is also introduced to analyze the Or, effect of temperature variations and it can be calculated by ≈ 6T − # assuming all other parameters unaffected except Q for SERR# Antiloge Qcrit Qcrit (10) crit @VDD and T particular supply voltage. Hence, # where SER# and SER6T are the soft error rates, and Qcrit 6T SER25 ◦C and Q are the critical charges for the considered SRAM SERRT = (7) crit SER ◦ cell and reference 6T SRAM cell, respectively. Here # 125 C @VDD indicates the considered SRAM cell for which SERR needs Or, to be analyzed. Lower the SERR# of any SRAM cell means ◦ ◦ ≈ @125 C − @25 C the less effect of the soft error on the considered SRAM SERRT Antiloge Qcrit Qcrit (8) @VDD cell. where SER25 ◦C and SER125 ◦C are the soft error rates, and @25 ◦C @125 ◦C Qcrit and Qcrit are the critical charges at operating temperature of 25◦C and 125◦C, respectively. Lower the 4 Leakage Current Estimation SERR means better radiation hardening enhancement of the design considering supply voltage and temperature The leakage current during the HOLD operation of the variations. SRAM cell is the major issue in the scaled CMOS 260 J Electron Test (2020) 36:255–269 technology. The leakage current is the major contributor to logic 0 and 1 are stored at the storage nodes Q and QQB, the total power dissipation of the circuit, especially during respectively, as shown in Fig. 5b and are given by: HOLD operation. In any of the SRAM cells, subthreshold = + + + IsubAS10T IsubMLA IsubMLP IsubMRN IsubMV2 (15) leakage current (Isub), junction leakage current (Ijn), and gate leakage current (Ig) are the major components of short channel effects in the devices [20]. The major leakage Ig = Igd + Igd + Igd + Igs + Igs current components in the 6T SRAM cell during HOLD AS10T MLA MLP MLN MLN MRP +Igd + Igd + Igd + Igs + Igs mode considering logic 0 and 1, are stored at the sensitive MRP MRN MRA MRA MR2 +Igd + Igs + Igd + Igd nodes Q and Q , respectively, as shown in Fig. 5aandare MR2 MV1 MV1 MV2 QB (16) given by: I = I + I + I (11) sub6T subMLA subMLP subMRN I = I + I + I + I jnAS10T jndMLA jndMLP jndMRN jndMRA (17) +Ijns + Ijnd I = I + I + I + I + I MRA MV2 g6T gdMLA gdMLP gdMLN gsMLN gsMRP (12) +Igd + Igd + Igd + Igs = + + MRP MRN MRA MRA ILeakageAS10T IsubAS10T IgAS10T IjnAS10T (18) From Fig. 5a and b, we observe that the proposed AS10T I = I + I + I + I + I (13) jn6T jndMLA jndMLP jndMRN jndMRA jnsMRA SRAM cell has more leakage components as compared to the 6T SRAM cell. Most of the additional components = + + ILeakage6T Isub6T Ig6T Ijn6T (14) are from Ig, which slightly increases the effective leakage Similarly, the major leakage current components in the pro- power dissipation in the proposed circuit. All the additional posed AS10T SRAM cell for HOLD operation considering components are because of the read decoupled and voltage
Fig. 5 Significant leakage Isub current components during WL = 0 V VDD WL = 0 HOLD mode of operation DD Ig considering logic 0 and 1 are Ijn stored at the storage nodes Q and QB for (a) 6T SRAM cell (b) AS10T SRAM cell Q = 0 Q B = 1
Gnd Gnd BL = 1 BLB = 1 (a)
Isub V VDD WWL = 0 WWL = 0 DD Ig RWL = 0
Ijn
x = 0 Q = 0 Q B = 1
Gnd Gnd BL = 1 BLB = 1 RBL = 0
Voltage Booster
(b) J Electron Test (2020) 36:255–269 261
Fig. 6 Critical charge at storage At node Q At node Q nodes of SRAM cells 15 B considering logic 0 and 1 are stored at nodes Q and QB 12 respectively 9
6 Critical charge (fC) 3
0 6T RD8T AS8T AS10T SRAM Cell
booster circuit used in the proposed AS10T SRAM cell to Figure 6 shows the critical charge at nodes Q and QB for improve the read stability and storage node critical charge. all the considered SRAM cells. From results it is observed that the critical charge at node Q is higher than the critical charge at node QB, and the proposed AS10T cell shows 5 Simulation Results and Discussions highest critical charge among all the considered cells. From results it is also observed that the critical charge of proposed With reference to the effectiveness of the proposed AS10T AS10T SRAM cell is 75.83%, 75.41%, and 0.14% higher SRAM cell, PTM 32 nm CMOS technology is used [15]. than the 6T, RD8T, and AS8T SRAM cells respectively. All the simulations are performed using HSPICE simulator Based on the above observation, for further analysis we have ◦ considering 0.9V of supply voltage at T = 25 C operating considered QB as a most sensitive node of the SRAM cell. temperature unless specified. We started our analysis with Further, we also calculated the critical charge with supply the critical charge as discuss below: voltage and temperature variations for 6T and proposed AS10T SRAM cells as shown in Fig. 7. From results it is 5.1 Critical Charge Analysis observed that the critical charge for proposed cell is higher for all the combinations of supply voltage and temperature. For the critical charge analysis, initially we identify the Higher the critical charge better the hardening from soft most sensitive node of the SRAM cell. To do this we errors; hence the proposed cell has enhanced soft error assuming that, 0 and 1 are stored at storing nodes Q and hardening compared to 6T SRAM cell. QB, respectively, for all the considered SRAM cells. Since the carrier mobility of NMOS transistor is higher than the 5.2 Process Variation Analysis PMOS transistor, the node storing 1 is more susceptible to soft error than node storing 0 [13]. Therefore, we consider For the investigation of process variations on the critical critical charge of QB as the Qcrit of the SRAM cells. voltage of considered SRAM cells, we perform 5000 Monte
Fig. 7 Critical charge varitation with different supply voltages and temperatures for (a)6T SRAM cell (b) AS10T SRAM cell
(a) (b) 262 J Electron Test (2020) 36:255–269
Fig. 8 5000 Monte Carlo 400 simulated Gaussian plot of V Q 6T Q and V critical voltages (V ) QB crit 6T Q for different SRAM cells B 300 RD8T RD8T AS8T 200 AS8T AS10T AS10T
# of Occurrences 100
0 0 0.15 0.3 0.45 0.6 0.75 0.9 Critical voltage (V)
Carlo simulations by varying the threshold voltage of voltage for the SRAM cells represent the sensitivity of the transistors. The threshold voltage of the transistors process variations which reduces the reliability of circuit. is generated randomly using a normal distribution with Table 2 shows the mean (μ) and standard deviation (σ)of ±10% maximum deviations from its original value [13]. the storage node critical voltages by performing 5000 Monte We calculated the standard deviation considering ±3σ Carlo simulations for all the considered SRAM cells. The deviation from the mean (μ) value. The calculation formula proposed cell has a deviation of 0.088V and 0.077V for Q of standard deviation (σ) for the critical voltage of the and QB, respectively, whereas, the 6T SRAM cell has the SRAM cells are given as deviation of 0.356V and 0.364V for Q and QB, respectively. The results demonstrate that the deviation of critical voltage (X − μ)2 from the mean value for proposed AS10T SRAM cell is σ = i (19) N minimum as compared to all other considered SRAM cells. From results, it is also observed that the 6T SRAM cell Where σ is the standard deviation (SD), N, Xi,andμ is maximum affected by process variations, whereas the denotes the number of sample values that is 5000, the proposed AS10T SRAM cell has better tolerance of process sample value, and the mean value, respectively. variations. For the analysis of soft error resilience and process Further, we also evaluated the process variability for the variations, Monte Carlo simulations for the storage node critical voltages of all the considered SRAM cells. The critical voltages of 6T, RD8T, AS8T, and AS10T SRAM process variability is the ratio of the standard deviation cells are shown in Fig. 8. Figure shows the distribution and the mean value of the critical voltages. For the better of critical voltages for each sample of various SRAM tolerance to the process variations, the variability should be cells. The simulation results show that the proposed AS10T as small as possible [21]. Figure 9 shows the variability for SRAM cell has less effect of process variations as compared the critical voltages of storage node Q and QB for all the to all other cells. The results demonstrate that the significant considered SRAM cells, and we observe that the AS10T has portion of critical voltage repeatability for 6T and AS8T less variability as compared to the all other SRAM cells. is near 0V, which shows that the flipping of logic in these Furthermore, our results demonstrate that the variability at SRAM cells is more easier as compared to RD8T and node VQ for AS10T is 3.61×,1.18×, and 2.02× lower AS10T SRAM cells. The scattered response of critical than the 6T, RD8T, and AS8T SRAM cells, respectively. Similarly, the variability at node VQB for AS10T is 4.56×, Table 2 Mean and standard deviation of storage node critical voltages 1.15×, and 2.05× lower than for 6T, RD8T, and AS8T (in volts) for different SRAM cells SRAM cells, respectively.
SRAM Cells ↓ QVcrit QB Vcrit 5.3 Soft Error Analysis μσ μσ To analyze the soft error robustness of SRAM cells with 6T 0.376 0.356 0.379 0.364 supply and temperature variations, we have calculated RD8T 0.334 0.103 0.364 0.088 intra cell SERR with both supply voltage and temperature AS8T 0.323 0.171 0.378 0.163 change, namely SERRV and SERRT , respectively. Table 3 AS10T 0.336 0.088 0.366 0.077 shows the soft error rate ratio with supply voltage change J Electron Test (2020) 36:255–269 263
Fig. 9 Process variability (σ/μ) 1.0 of VQ and VQB critical voltages at Q at QB (Vcrit) for different SRAM cells 0.8
() 0.6
0.4 Variability 0.2
0.0 6T RD8T AS8T AS10T SRAM Cell
(SERRV ) from 0.5V to 0.9V at different operating hardening as compared to the 6T SRAM cell. Figure 10 temperatures. From results it is observed that the SERRV shows the inter cell SERR for all the considered cells increases with the rise in temperature for all the considered normalized to the 6T SRAM cell for different extreme SRAM cells. However, the increase in SERRV for combinations of supply voltage and operating temperature. proposed AS10T SRAM cell is less as compared to all As we have two variables, VDD and T for calculating iner other considered cells. The change in SERRV with change cell SERR, there is a total of four combinations. Here, in temperature from 25◦C to 125◦C for proposed AS10T we have calculated SERR considering supply voltages of SRAM cell is 0.112 as compared to 0.223, 0.221, and 0.113 0.5V and 0.9V,and operating temperatures 25◦C and 125◦C. for 6T, RD8T, and AS8T SRAM cells, respectively. Hence, The results show that the inter cell SERR for RD8T is the proposed cell has less variation in SERRV as compared nearly the same as the 6T SRAM cell because of the to all other cells. Similarly, Table 4 shows the soft error rate equal critical charges at the sensitive nodes. The inter ratio with operating temperature change (SERRT ) from cell SERR for AS8T and proposed AS10T are also the 25◦C to 125◦C at different supply voltages. From results same because the voltage booster is connected between it is observed that the SERRT decreases with the rise in storage nodes to improve the critical charge in both the supply voltage for all the considered SRAM cells. However, cells but less than the 6T and RD8T SRAM cells. It is the SERRT for proposed AS10T SRAM cell is less as also observed that the inter cell SERR also depends on compared to all other considered cells. The decrease in the supply voltage and operating temperature. The results SERRT with change in supply voltage from 0.5V to 0.9V show that the maximum improvement in the SERR is for proposed AS10T SRAM cell is 0.7 as compared to when the operating temperature is 25◦C, and the supply 0.641, 0.639, and 0.699 for 6T, RD8T, and AS8T SRAM voltage is 0.9V. Higher supply voltage increases the current cells, respectively. Hence, the proposed cell is more resilient flowing through the circuit and leads to increase the critical to soft error at higher supply voltage as compared to all other charge at the sensitive node. Similarly, the critical charge cells. decreases with the increase in operating temperature; hence, Further, we also analyze the inter cell SERR for the the SERR at the higher temperature increases. From the effectiveness of the proposed SRAM cell on the soft error above discussions, the proposed SRAM cell performs well
Table 3 Soft error rate ratio with voltage change (SERRV )atvarious Table 4 Soft error rate ratio with temperature change (SERRT )at operating temperatures of different SRAM cells various supply voltages of different SRAM cells
Temperature SRAM cells ↓ Supply voltage SRAM cells ↓
6T RD8T AS8T AS10T 6T RD8T AS8T AS10T
25 ◦C 0.089 0.089 0.016 0.014 0.5V 0.903 0.899 0.785 0.782 50 ◦C 0.217 0.215 0.063 0.061 0.6V 0.719 0.701 0.498 0.496 75 ◦C 0.257 0.254 0.089 0.087 0.7V 0.553 0.551 0.298 0.295 100 ◦C 0.284 0.282 0.107 0.105 0.8V 0.406 0.402 0.170 0.167 125 ◦C 0.313 0.311 0.129 0.126 0.9V 0.262 0.260 0.086 0.082 264 J Electron Test (2020) 36:255–269
Fig. 10 Inter cell soft error rate ratio for different SRAM cells at 1.0 ο T=25 CandV =0.9V the four extreme combinations DD ο of supply voltage and operating T=125 CandV =0.9V 0.8 DD temperature. The SERR is ο normalized to 6T SRAM cell for T=25 CandV =0.5V 0.6 DD all the combinations ο T=125 CandV =0.5V DD 0.4
0.2 SERR Normalized to 6T
0.0 6T RD8T AS8T AS10T SRAM Cell
Fig. 11 Noise margins of 600 different SRAM cells WM HSNM RSNM
500
400
300
200 Noise Margin (mV)
100
0 6T RD8T AS8T AS10T SRAM Cell
Fig. 12 Power dissipation of 5 various SRAM cells during read Read Power ( W) Write Power ( W) Leakage Power (nW) operation, write operation, and hold operation 4
3
2
Power Dissipation 1
0 6T 8T AS8T AS10T SRAM Cell J Electron Test (2020) 36:255–269 265
Table 5 Normalized value of various performance parameters for different SRAM cells
SRAM cells ↓ Performance parameters ↓
Qcrit WM HSNM RSNM PW PR PL TWA TRA Area RSEAP
6T111 1 1111111 RD8T 1.002 1 1 3.357 1.001 1.249 1.001 1.044 1.20 1.49 1.77 AS8T 1.756 0.979 1.042 1.357 1.014 0.779 1.151 0.996 1.064 1.74 2.08 AS10T 1.758 1.000 1.042 3.286 1.014 0.974 1.151 1.029 1.277 2.14 2.83 in terms of soft error hardening if it is operated at room one of the effective way to increase RSNM due to presence temperature and subthreshold conditions. of separate path during read operation. The RSNM of RD8T, AS8T, and AS10T is increased by 3.36×,1.36×, and 3.29× 5.4 Stability Analysis as compared to 6T SRAM cell. The enhancement of RSNM for RD8T and AS10T is due to presence of separate read For the stabilty analysis of all the considered SRAM cells, decoupled path during read operation. we have calculated the hold static noise margin (HSNM), read static noise margin (RSNM) and write margin (WM) 5.5 Power Dissipation Analysis at 0.9V supply voltage as shown in Fig. 11. The stability is conventionally computed as the static noise margin. The The power dissipation of the SRAM cell is one of the major noise margin is gauged by tracing the overlapped voltage concerns for low power circuit designs. We calculated the transfer characteristics (Butterfly diagram) for the back to power dissipation of all the considered SRAM cells at the back connected inverters which form the memory cell. The 0.9V supply voltage and 25◦C for all three modes of the diagonal of the largest square that can fit in the eyes of the operations, namely, read, write, and hold modes, as shown butterfly diagram finally determines the noise margin [16]. in Fig. 12. The results show that the read power for the From results it is observed that the WM of 6T, RD8T and circuits having read decoupled circuit increases, whereas proposed AS10T are same whereas, the WM of AS8T is the voltage booster decreases the power dissipation during reduced by 2.1% as compared to 6T SRAM cell. The HSNM the read operation. The proposed AS10T has both read of 6T and RD8T are same whereas HSNM of AS8T and decoupled and voltage booster circuits hence effectively proposed AS10T increased by 4.17% as compared to 6T less read power dissipation as compared to 6T SRAM cell. SRAM cell. The increase in HSNM of AS8T and AS10T However, the read power dissipation for the RD8T and is due to presence of voltage booster connected between AS8T SRAM cells is less than the AS10T SRAM cell. storage nodes. The major problem with the 6T SRAM cell Results also show that the power dissipation during the write is small RSNM and researcher are mainly trying to increase operation for all the considered cells is almost the same. the RSNM of the SRAM cell. Read decoupled technique is This is because, during the write operation, all the cells
Fig. 13 Delay of various SRAM 120 cells during read operation and Read operation Write operation write operation 100
80 30.0 Delay (ps) 27.5
25.0 6T 8T AS8T AS10T SRAM Cell 266 J Electron Test (2020) 36:255–269
Fig. 14 Layout of (a) 6T SRAM cell (b) Proposed AS10T SRAM cell
(a)
(b)
6T 1× AS10T 1.77×
1× 1.21× have the same cross-coupled inverters to write the data at normalized values of all the power components can be seen the storage nodes. We also analyze the power during hold in Table 5. mode or leakage power of all the considered cells. Results demonstrate that the voltage booster increases the current 5.6 Delay Analysis paths, which leads to more leakage power dissipation in the AS8T and proposed AS10T SRAM cells. The components Read access time or read delay (TRA) is the time duration which are responsible for increasing the leakage power between the RWL activation to the instant when the ‘RBL’ for AS10T has already been discussed in Section 4.The voltage is discharged by 50 mV from its initial logic high. J Electron Test (2020) 36:255–269 267
Fig. 15 Normalized values of 3.0 cell area and RSEAP for Area RSEAP different SRAM cells 2.5
2.0
1.5
1.0 Normalized values 0.5
0.0 6T RD8T AS8T AS10T SRAM Cell
For the differential read SRAM cell, the 50 mV differential 5.8 Reliability, Stability to Energy Area Product Ratio between ‘BL’ and ‘BLB’ is good enough to be detected by a sense amplifier, thereby avoiding misread [12]. However, The performance parameters of SRAM cell has the trade-off in case of a single-ended read, TRA is the time required among them [19]. Therefore, to access the the performance for discharging the bitline voltage to (VDD -50mV)after of SRAM cell, we propose an Reliability Stability to Energy the activation of word line during a read operation [14]. Area Product (RSEAP) ratio to evaluate the overall novelty Similarly, the write access time or write delay (TWA )for of the SRAM cell as given by: writing ‘1’ is estimated as the time duration between the Q × RSNM × HSNM × WM WWL activation time to the time when a ‘0’ storing node RSEAP = crit,n n n n PW,n × TWA,n × PR,n × TRA,n×PL,n × An charges up to 90% of VDD. Similarly, TWA for writing ‘0’ is estimated as the time duration between the WWL activation (20) time to the time when a ‘1’ storing node discharges to 10% Where Qcrit,n, RSNMn, HSNMn, WMn, PW,n, PR,n, PL,n, of VDD. TWA,n, TRA,n and An are the normalized values of critical Figure 13 shows the read and write delay of all the charge, read SNM, hold SNM, write margin, write power, considered SRAM cells. THe results show that the circuits read power, leakage power, write delay, read delay and cell with read decoupled circuit slightly has more delay because area, respectively. All the parameters are normalized with the read decoupled circuit increases the overall capacitance, respect to 6T SRAM cell. Figure 15 shows the normalized which leads to increased delay. The effect of read decoupled RSEAP at 0.9V supply voltage of different SRAM cells circuit on the write delay is not very high because it considered in this work. From results it is observed that is not used during the write operation. However, the the normalized RSEAP of proposed AS10T SRAM cell is read decoupled circuit affects the read delay due to its highest among all other considered cells. The RSEAP of involvement during the read operation. The read delay of RD8T, AS8T, and AS10T are 1.77×,2.08×, and 2.83× the proposed AS10T SRAM cell is 27.7% higher than the higher than the 6T SRAM cell, respectively. The normalized 6T SRAM cell. value of all the performance parameters of considered cells are given in Table 5. It is also observe that the proposed 5.7 Area Comparison cell has higher critical charge and noise margin. Therefore, AS10T cell is an alternative option considering overall Cell area is one of the major concern while designing performance with the enhanced soft error hardening. energy efficient, reliable and high performance SRAM cell. Figure 14 shows the layout view of 6T and proposed AS10T SRAM cell. Both the cells have two sensitive nodes as 6 Conclusion indicated in the figures. Out of two sensitive nodes, one of the node is more sensitive to soft error depending on This paper presents an radiation hardened asymmetric 10T the stored data. Figure 15 shows the normalized area of (AS10T) SRAM cell to enhance the soft error hardening. different SRAM cells. The area of RD8T, AS8T, and AS10T The proposed cell uses read decoupled path to improve are 1.49×,1.74×, and 2.14× higher as compared to 6T read static noise margin and voltage booster connected SRAM cell. between storage nodes to improve node capacitance and 268 J Electron Test (2020) 36:255–269 hence enhanced radiation hardening. We demonstrated that 11. Kim JS, Chang IJ (2017) We-quatro: radiation-hardened SRAM the AS10T SRAM cell has higher critical charge at the cell with parametric process variation tolerance. IEEE Trans Nucl most sensitive node. We also calculated the soft error rate Sci 64(9):2489–2496 12. Kulkarni JP, Kim K, Roy K (2007) A 160 mV robust Schmitt with supply voltage and temperature change SERRV and trigger based subthreshold SRAM. IEEE J Solid State Circuits SERRT for SRAM cells and it is found that the AS10T has 42(10):2303–2313 less soft error rate ratio compared to all other considered 13. Lin S, Kim YB, Lombardi F (2010) Design and analysis of a 32 cell. To the end, we also introduce reliability stability to nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr VLSI J 43(2):176–187 energy area product (RSEAP) ratio as performance metric. 14. Pasandi G, Fakhraie SM (2014) A 256-kB T near-threshold Our analysis indicates that, AS10T cell has higher RSEAP SRAM with 1K cells per bitline and enhanced write and read compared to 6T, RD8T, and AS8T SRAM cells. Therefore, operations. IEEE Trans Very Large Scale Integr (VLSI) Syst the proposed SRAM cell can be used for the aerospace 23(11):2438–2446 15. Predictive Technology Model (PTM) (2017). http://ptm.asu.edu/. application which demands high speed, radiation hardened Accessed on December 12, 2017 and high stability with considerable area requirement. 16. Sanvale P, Gupta N, Neema V, Shah AP, Vishvakarma SK (2019) An improved read-assist energy efficient single ended PPN based Acknowledgments The authors would like to thank the University 10T SRAM cell for wireless sensor network. Microelectron J Grant Commission (UGC) New Delhi, Government of India under JRF 92(104):611 scheme with award no. 3528/(NET-DEC. 2014) for providing financial 17. Shah AP, Waltl M (2020) Bias temperature instability aware and support and CSIR, Government of India with research project grant no. soft error tolerant radiation hardened 10T SRAM cell. Electronics, 22/0651 /14/EMR-II, for simulation software. 1–11 18. Shah AP, Yadav N, Beohar A, Vishvakarma SK (2018) An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. Microelectron Reliab 87:15–23 References 19. Shah AP, Yadav N, Beohar A, Vishvakarma SK (2018) On- chip adaptive body bias for reducing the impact of NBTI 1. Ahmad S, Alam N, Hasan M (2018) Pseudo differential multi-cell on 6T SRAM cells. IEEE Trans Semicond Manuf 31(2):242– upset immune robust SRAM cell for ultra-low power applications. 249 AEU-Int J Electron Commun 83:366–375 20. Shah AP, Yadav N, Beohar A, Vishvakarma SK (2018) Process 2. Alouani I, Elsharkasy WM, Eltawil AM, Kurdahi FJ, Niar S variation and NBTI resilient Schmitt trigger for stable and reliable (2017) AS8-static random access memory (SRAM): asymmetric circuits. IEEE Trans Dev Mater Reliab, 1–9 sram architecture for soft error hardening enhancement. IET Circ 21. Sharma V, Gopal M, Singh P, Vishvakarma SK (2018) A 220 mV Dev Syst 11(1):89–94 robust read-decoupled partial feedback cutting based low-leakage 3. Chang L, Fried DM, Hergenrother J, Sleight JW, Dennard RH, 9T SRAM for internet of things (IoT) applications. AEU-Int J Montoye RK, Sekaric L, McNab SJ, Topol AW, Adams CD, Electron Commun 87:144–157 Guarini KW (2005) Stable SRAM cell design for the 32 nm node 22. Yan A, Huang Z, Yi M, Xu X, Ouyang Y, Liang H (2017) Double- and beyond. In: Proc. of IEEE symposium on VLSI technology. node-upset-resilient latch design for nanoscale CMOS technology. Digest of Technical Papers, 128–129 IEEE Trans Very Large Scale Integr (VLSI) Syst 25(6):1978– 4. Ding Q, Luo R, Wang H, Yang H, Xie Y (2006) Modeling the 1982 impact of process variation on critical charge distribution. Proc IEEE Int SOC Conf, 243–246 Publisher’s Note Springer Nature remains neutral with regard to 5. Dodd PE, Massengill LW (2003) Basic mechanisms and modeling jurisdictional claims in published maps and institutional affiliations. of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583–602 6. Granlund T, Granbom B, Olsson N (2003) Soft error rate increase Ambika Prasad Shah was born in Singrauli, Madhya Pradesh, for new generations of SRAMs. IEEE Trans Nucl Sci 50(6):2065– India. He received B.E. degree in Electronics & Telecommunication 2068 Engineering and M.E. degree in Electronics Engineering from Institute 7.GuoJ,ZhuL,SunY,CaoH,HuangH,WangT,QiC,ZhangR, of Engineering & Technology, Devi Ahilya University, Indore, India in Cao X, Xiao L, Mao Z (2018) Design of area-efficient and highly 2009 and 2015 respectively. He received PhD degree from Electrical reliable RHBD 10T memory cell for aerospace applications. IEEE Engineering Department, Indian Institute of Technology Indore, India Transactions on Very Large Scale Integration (VLSI) Systems in 2019. Before joining his Ph.D. degree, he was Assistant Professor in 8. Hughes H, Benedetto J (2003) Radiation effects and hardening Electronics & Telecommunication Engineering Department, Institute of MOS technology: devices and circuits. IEEE Trans Nucl Sci of Engineering & Technology, Devi Ahilya University, Indore, India 50(3):500–521 from 2010 to 2016. Currently he is working as a Postdoctoral Fellow 9. Ibe E, Taniguchi H, Yahagi Y, Shimbo Ki, Toba T (2010) Impact at Institute for Microelectronics, TU Wien, Austria. of scaling on neutron-induced soft error in SRAMs from a 250 His current research interest includes reliability analysis of digital nm to a 22 nm design rule. IEEE Trans Electron Dev 57(7):1527– circuits, reliable SRAM design, low power high performance digital 1538 circuit designs. He has authored/co-authored more than 35 research 10. Jahinuzzaman SM, Sharifkhani M, Sachdev M (2009) An papers in peer reviewed international journals and conferences. He is analytical model for soft error critical charge of nanometric the recipient of Young Scientist award by M.P. Council of Science and SRAMs. IEEE Trans Very Large Scale Integr (VLSI) Syst Technology in 2018. He is the member of IEEE, lifetime member of 17(9):1187–1195 IAENG and associate member of UACEE. J Electron Test (2020) 36:255–269 269
Santosh Kumar Vishvakarma received B.Sc. degree in electronics Michael Hubner ¨ received the Diploma degree in electrical engi- from University of Gorakhpur, Gorakhpur, M.Sc. degree in electronics neering and information technology and the Ph.D. degree from the from Devi Ahilya Vishwavidyalaya, Indore, India, M.Tech. degree in University of Karlsruhe, Karlsruhe, Germany, in 2003 and 2007, microelectronics from Punjab University, Chandigarh, India, in 1999, respectively, and the Habilitation degree in reconfigurable comput- 2001, and 2003, respectively, and the Ph.D. degree from the Indian ing systems from the Karlsruhe Institute of Technology, Karlsruhe, Institute of Technology Roorkee, India, in 2010. From January 2009 to in 2011. He has been the Chair for Embedded Systems for Infor- July 2010, he was with University Graduate Center, Kjeller, Norway, mation Technology, Ruhr-University of Bochum, Bochum, Germany, as an Postdoctoral Fellow under European Union project “COMON”. since 2012. His current research interests include reconfigurable com- He is currently working as an Associate Professor with the Department puting and particularly new technologies for adaptive FPGA run-time of Electrical Engineering, Indian Institute of Technology Indore, reconfiguration and on-chip network structures with application in India where he is leading Nanoscale Devices and VLSI Circuit and automotive systems, including the integration into high-level design System Design Lab. His current research interests include nanoscale and programming environments. devices and circuits, Reliable SRAM designs, multigate and multifin MOSFET, and tunnel FET and their circuit applications.