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CoreConnect
An Architecture and Compiler for Scalable On-Chip Communication
On-Chip Interconnect Schemes for Reconfigurable System-On-Chip
AXI Reference Guide
Wishbone Bus Architecture – a Survey and Comparison
An Overview of Soc Buses
Vitex-II Pro: the Platfom for Programmable Systems
Computing Platforms Chapter 4
Xilinx XAPP1000: Reference System : Plbv46 PCI Express in a ML555
Design and Implementation of Clocked Open Core Protocol Interfaces for Intellectual Property Cores and On-Chip Network Fabric
New Virtex™-II Pro Family Extends Platform FPGA Capability with Multi
View of the Thesis
Automated Bus Generation for Multi-Processor Soc Design
Synopsys Powerpc for Developerworks
Topic 10 Bus Architecture & Interconnects Introductions & Sources
XC2VP30-6FFG896C Xilinx Inc. IC FPGA 556 I/O 896FCBGA
Introduction to Embedded System Design Using Field Programmable Gate Arrays Rahul Dubey
Xilinx DS639 Logicore IP XPS Universal Bus 2.0 Device (V5.00A)
A Modular Peripheral to Support Self-Reconfiguration in Socs
Top View
HW-SW Components for Parallel Embedded Computing on Noc-Based Mpsocs Keywords
Xilinx UG077 Virtex-4 ML450 Networking Interfaces Platform User
Parallel Ultra Low Power Embedded System
Selecting Memory Controllers for DSP Systems by Deepak Shankar, Mirabilis Design
Datasheet Search Engine
Transaction-Level Modeling for Architectural and Power Analysis of Powerpc and Coreconnect-Based Systems
Power, Performance and Reliability Optimisation of On-Chip Interconnect by Adroit Use of Dark Silicon
Xilinx DS734 XPS USB Host Controller
Dynamic Assertion-Based Verification
FPGA Design Framework for Dynamic Partial Reconfiguration
Using Proportional-Integral-Differential Approach for Dynamic Traffic Edictionpr in Wireless Network-On-Chip
Coreconnect™ - a Simplistic Overview Powerpc 405
Fast Exploration of Bus-Based On-Chip Communication Architectures
UNIVERSITY of THESSALY Exploiting Reconfigurable
Core Communication Interface for Fpgas
Amba Avalon Coreconnect Wishbone
Xilinx XAPP1040 Reference System: Plbv46 Endpoint Bridge for PCI
Open Ingchao Final.Pdf