DOCSLIB.ORG

Diss Petrovic Neu 2

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Diss Petrovic Neu 2 Design Methodology for highly Reliable Digital ASIC Designs Applied to Network-Centric System Middleware Switch Processor Von der Fakultät für Mathematik, Naturwissenschaften und Informatik der Brandenburgischen Technischen Universität Cottbus - Senftenberg zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften (Dr.-Ing.) genehmigte Dissertation vorgelegt von Diplom Ingenieur Vladimir Petrovic Geboren am 13.12.1982. in Pozarevac, Serbien, Jugoslawien Gutachter: Prof. Dr.-Ing. Rolf Kraemer Gutachter: Prof. Dr.-Ing. Heinrich Theodor Vierhaus Gutachter: Prof. Dr. Sergio Montenegro Tag der mündlichen Prüfung: 12.12.2013. Design methodology for highly reliable digital ASIC designs 1 Design methodology for highly reliable digital ASIC designs Acknowledgments I would like to express my sincerely gratitude to my supervisor Prof. Rolf Kraemer for support and opportunity to conduct my research work at the IHP through last years. While working in IHP I had support from many other colleagues and on this place I would like to thank them all. Before I express my gratitude to all people which were important during the thesis writing, I would like here specially to thank Prof. Dr. Vanco Litovski for the provided knowledge and support since 2001, when I started seriously to learn electronics. Specially thanks to Gunter Schoof and Ulrich Jagdhold for constructive discussions, interesting ideas and very helpful support during practical tests and thesis development. Dr. Zoran Stamenkovic put a lot of effort during thesis writing and he helped me a lot to bring a scientific form of the work provided in thesis. Therefore, I owe special gratitude to him and also to Dr. Michael Methfessel for support. I would like to thank Dr. Milos Krstic for very important discussions, thesis organization and great support in last years. The measurements and other tests would be impossible without Horst Frankenfeldt, Irina Matthaei, Silvia Hinrich, Christoph Wolf, Mahdi Khafaji and Florian Teply. I would like to express my sincerely gratitude to all of you. I would like to give my warmest thanks to my brother, parents, family and all friends, especially from KUD Kostolac for tremendous support all these years. This work is especially dedicated to my wife Danica. Her love, motivation and support have created the confidence that is needed to complete such a huge and complex task. Vladimir Petrovic 22.01.2014. 2 Design methodology for highly reliable digital ASIC designs 3 Design methodology for highly reliable digital ASIC designs Contents Abstract ................................................................................................................... 6 Zusammenfassung ................................................................................................. 7 1. Introduction ........................................................................................................ 8 2. Topic Definition and State-Of-The-Art .............................................................11 2.1. Irradiation Effects and Circuit Faults ........................................................11 2.2. SEU and SET Fault Models and Injection Techniques .............................13 2.3. SEL Model and Characterization ...............................................................17 2.4. Fault-Tolerant Circuits ................................................................................20 2.5. Standard Design Flow ................................................................................29 2.6. Open Issues .................................................................................................34 3. Fault-tolerant Circuits for Highly Reliable ASIC Designs ..............................35 3.1. Latchup Protection Circuits .......................................................................35 3.1.1. SPS Type 1 ........................................................................................38 3.1.2. SPS Type 2 ........................................................................................42 3.2. Redundant Circuits with Latchup Protection ...........................................45 3.2.1. TMR Circuit with Latchup Protection ..............................................45 3.2.2. Self-voting DMR Circuit with Latchup Protection ..........................51 3.3. Power Network Controller ..........................................................................57 4. Fault-Tolerant Circuit Simulation and Analysis ..............................................59 4.1. Fault Injection ..............................................................................................59 4.1.1. Transient Fault Library .....................................................................61 4.1.2. Upset Fault Library ...........................................................................63 4.1.3. Fault Injector .....................................................................................64 4.1.4. Fault Injection Mechanism ...............................................................67 4.2. Test Circuits ................................................................................................68 4.2.1. SET/SEU test circuits .......................................................................68 4.2.2. SEL test circuits ...............................................................................70 4.3. Simulation Results ......................................................................................73 5. Modified Design Flow and Circuits Implementation.......................................79 5.1. Modified Design Flow .................................................................................79 5.1.1. Netlist Parser ....................................................................................81 5.1.2. SPS cell automated placement and routing ...................................83 4 Design methodology for highly reliable digital ASIC designs 5.2. Implemented Test Circuits .........................................................................85 5.2.1. SPS network......................................................................................85 5.2.2. SPS cell .............................................................................................89 5.2.3. DMR Redundant Circuits with Latchup Protection ........................89 5.3. Results and Analysis ..................................................................................91 5.3.1. Power Network Controller ...............................................................91 5.3.2. Redundant circuits analysis ............................................................91 5.3.3. SPS cells analysis ............................................................................93 5.3.4. Measurements ..................................................................................96 6. A Case Study: Middleware Switch Processor ...............................................106 6.1. Introduction ...............................................................................................106 6.2. Middleware Switch Architecture ..............................................................108 6.2.1. Functional Description ...................................................................110 6.2.2. Middleware Switch Implementation ..............................................129 6.3. Fault-tolerant Middleware Switch Processor ..........................................131 6.4. Fault-tolerant MW Switch Implementation Characteristics ...................131 7. Conclusion .......................................................................................................135 Appendix A ...........................................................................................................137 Appendix B ...........................................................................................................141 Appendix C ...........................................................................................................147 Appendix D ...........................................................................................................150 Appendix E ...........................................................................................................152 References ...........................................................................................................159 List of acronyms ..................................................................................................165 Bibliography .........................................................................................................169 5 Design methodology for highly reliable digital ASIC designs Abstract The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits
Load more

Recommended publications
  • Presentazione Di Powerpoint
    Noise measurements on 65 nm CMOS transistors at very high total ionizing dose V. Rea,c, L. Gaionia,c, L. Rattib,c, E. Riceputia,c, M. Manghisonia,c, G. Traversia,c c aUniversità di Bergamo bUniversità di Pavia INFN Sezione di Pavia Dipartimento di Ingegneria e Scienze Applicate Dipartimento di Ingegneria Industriale e dell’Informazione V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 1 Motivation 65 nm CMOS technology is a candidate for mixed-signal readout of high granularity silicon pixel sensors, with potential to meet the requirements of diverse applications such as particle tracking in the innermost layers of ATLAS and CMS at HL-LHC and photon imaging at very high brilliance and high rate light sources Tolerance to extremely high levels of ionizing radiation is a key requirement for both application fields, up to 1 Grad Total Ionizing Dose (TID) during chip lifetime. RD53 collaboration has carried out an extensive study of the behavior under irradiation of a 65 nm CMOS technology, with which a first generation of demonstrator chips is being designed The goal of this paper is to find out if 65 nm CMOS analog front- end circuits can still provide an adequate noise performance even at extremely high total doses. Study of radiation effects on noise can give very important hints about damage mechanisms. V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 2 Test devices and irradiation procedure A test chip was submitted and fabricated with the TSMC 65 nm
    [Show full text]
  • Circuit Optimisation Using Device Layout Motifs
    Circuit Optimisation using Device Layout Motifs Yang Xiao Ph.D. University of York Electronics July 2015 Abstract Circuit designers face great challenges as CMOS devices continue to scale to nano dimensions, in particular, stochastic variability caused by the physical properties of transistors. Stochas- tic variability is an undesired and uncertain component caused by fundamental phenomena associated with device structure evolution, which cannot be avoided during the manufac- turing process. In order to examine the problem of variability at atomic levels, the `Motif ' concept, defined as a set of repeating patterns of fundamental geometrical forms used as design units, is proposed to capture the presence of statistical variability and improve the device/circuit layout regularity. A set of 3D motifs with stochastic variability are investigated and performed by technology computer aided design simulations. The statistical motifs compact model is used to bridge between device technology and circuit design. The statistical variability information is transferred into motifs' compact model in order to facilitate variation-aware circuit designs. The uniform motif compact model extraction is performed by a novel two-step evolutionary algorithm. The proposed extraction method overcomes the drawbacks of conventional extraction methods of poor convergence without good initial conditions and the difficulty of simulating multi-objective optimisations. After uniform motif compact models are obtained, the statistical variability information is injected into these compact models to generate the final motif statistical variability model. The thesis also considers the influence of different choices of motif for each device on cir- cuit performance and its statistical variability characteristics. A set of basic logic gates is constructed using different motif choices.
    [Show full text]
  • Intel's Core 2 Family
    Intel’s Core 2 family - TOCK lines Kaby Lake to Coffee Lake Dezső Sima Vers. 3.1 October 2018 Contents (1) • 1. Introduction • 2. The Core 2 line • 3. The Nehalem line • 4. The Sandy Bridge line • 5. The Haswell line • 6. The Skylake line • 7. The Kaby Lake line • 8. The Kaby Lake Refresh line • 9. The Coffee Lake line • 10. The Coffee Lake line Refresh Contents (2) • 11. The Cannon Lake line (outlook) • 12. References 7. The Kaby Lake line • 7.1 Introduction to the Kaby Lake line • 7.2 Major enhancements of the Kaby Lake line • 7.3 Major innovation of the Kaby Lake line: The Optane memory • 7.4 Kaby Lake-based processor lines 7.1 Introduction to the Kaby Lake line 7.1 Introduction to the Kaby Lake line (1) 7.1 Introduction to the Kaby Lake line • The 7th generation Kaby Lake line is actually a Skylake refresh line (Tock line) manufactured on 14 nm technology. • Note that Intel designates it as a new generation in contrast to the Devil’s Cannon models that were similar optimizations then of the Haswell (4. generation) line. 22 nm 14 nm Ivy Bridge Haswell Broadwell Skylake Kaby Lake 3. gen. 4. gen 5. gen. 6. gen. 7. gen. Figure: Enhancing the Tick-Tock model with an optimization phase [225] • It is important to note that with the 14 nm technology the cadence of Intel’s technology transitions slowed down to about 2.5 years, as Kranich, Intel’s CEO stated at Intel’s Q2 2015 Investor's conference call (07/2015).
    [Show full text]
  • Advanced Source/Drain and Contact Design for Nanoscale CMOS
    Advanced Source/Drain and Contact Design for Nanoscale CMOS Reinaldo Vega Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2010-84 http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-84.html May 20, 2010 Copyright © 2010, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Advanced Source/Drain and Contact Design for Nanoscale CMOS by Reinaldo Vega A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Chenming Hu Professor Junqiao Wu Spring 2010 Advanced Source/Drain and Contact Design for Nanoscale CMOS Copyright © 2010 by Reinaldo Vega Abstract Advanced Source/Drain and Contact Design for Nanoscale CMOS by Reinaldo Vega Doctor of Philosophy in Engineering – Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The development of nanoscale MOSFETs has given rise to increased attention paid to the role of parasitic source/drain and contact resistance as a performance-limiting factor. Dopant-segregated Schottky (DSS) source/drain MOSFETs have become popular in recent years to address this series resistance issue, since DSS source/drain regions comprise primarily of metal or metal silicide.
    [Show full text]
  • A Case for Packageless Processors
    A Case for Packageless Processors Saptadeep Pal∗, Daniel Petrisko†, Adeel A. Bajwa∗, Puneet Gupta∗, Subramanian S. Iyer∗, and Rakesh Kumar† ∗Department of Electrical and Computer Engineering, University of California, Los Angeles †Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign fsaptadeep,abajwa,s.s.iyer,[email protected], fpetrisk2,[email protected] Abstract—Demand for increasing performance is far out- significantly limit the number of supportable IOs in the pacing the capability of traditional methods for performance processor due to the large size and pitch of the package- scaling. Disruptive solutions are needed to advance beyond to-board connection relative to the size and pitch of on- incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. We argue chip interconnects (∼10X and not scaling well). In addition, that packages reduce the potential memory bandwidth of a the packages significantly increase the interconnect distance processor by at least one order of magnitude, allowable thermal between the processor die and other dies. Eliminating the design power (TDP) by up to 70%, and area efficiency by package, therefore, has the potential to increase bandwidth a factor of 5 to 18. Further, silicon chips have scaled well by at least an order of magnitude(Section II). Similarly, while packages have not. We propose packageless processors - processors where packages have been removed and dies processor packages are much bigger than the processor itself directly mounted on a silicon board using a novel integra- (5 to 18 times bigger). Removing the processor package tion technology, Silicon Interconnection Fabric (Si-IF).
    [Show full text]
  • The Microarchitecture of Intel, AMD and VIA Cpus: an Optimization Guide for Assembly Programmers and Compiler Makers
    3. The microarchitecture of Intel, AMD, and VIA CPUs An optimization guide for assembly programmers and compiler makers By Agner Fog. Technical University of Denmark. Copyright © 1996 - 2021. Last updated 2021-08-17. Contents 1 Introduction ....................................................................................................................... 7 1.1 About this manual ....................................................................................................... 7 1.2 Microprocessor versions covered by this manual ........................................................ 8 2 Out-of-order execution (All processors except P1, PMMX) .............................................. 10 2.1 Instructions are split into µops ................................................................................... 10 2.2 Register renaming .................................................................................................... 11 3 Branch prediction (all processors) ................................................................................... 12 3.1 Prediction methods for conditional jumps .................................................................. 12 3.2 Branch prediction in P1 ............................................................................................. 18 3.3 Branch prediction in PMMX, PPro, P2, and P3 ......................................................... 21 3.4 Branch prediction in P4 and P4E .............................................................................. 23 3.5 Branch
    [Show full text]
  • Embedded/Iot Solutions
    Embedded/IoT Solutions Connecting the Intelligent World from Devices to the Cloud Long Life Cycle · High-Efficiency · Compact Form Factor · High Performance · Global Services Intelligent Transportation On Demand Video Digital Industrial Signage Automation Embedded Cloud Internet Storage of Things Medical Imaging U U Retail Sales Digital Communication Surveillance and Networking Fanless Systems System on Chip 45-Bay Storage Supermicro Building Block Solutions for Embedded Applications, Supermicro Next Generation Solutions The Internet Of Things and based on Intel® Processors The Intelligent Edge June 2018 www.supermicro.com/embedded Embedded Building Block Solutions X11 Intel® Xeon® Processor D-2100 NEW! High Core, High Performance (FCBGA 2518 SoC) Supermicro X11 Generation of Motherboards/Servers support Intel Xeon Processors D-2100 (Formerly Skylake-DE) series system-on-chip (SoC) Processors. Based on new Intel® Xeon® D-2100 processors with a range of 4 to 18 cores and up-to 512 GB of addressable memory with error-correcting code (ECC), this system-on-a-chip (SoC) has an integrated Platform Controller Hub (PCH), integrated high-speed I/O, up-to four integrated 10 Gigabit Intel® Ethernet ports, and a thermal design point (TDP) of 60 watts to 110 watts. Enhanced Intel® QuickAssist Technology (Intel® QAT), available as an integrated option, delivers up to 100Gbps of hardware acceleration, for growing cryptography, encryption, and decryption workloads offering greater efficiency while delivering enhanced transport and protection across server, storage, and network infrastructure. New Intel® Advanced Vector Extensions 512 (Intel® AVX-512) delivers workload-optimized performance and throughput increases for advanced analytics, compute-intensive applications, cryptography, and data compression.
    [Show full text]
  • Modeling the Effects of Systematic Process Variation on Circuit Performance
    Modeling the Effects of Systematic Process Variation on Circuit Performance by Vikas Mehrotra Bachelor of Science, Wright State University, 1993 Master of Science, The Ohio State University, 1995 Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirem . for the degree of OF TECHNOLOGY Doctor of Philosophy JUL 11 2001 at the LIBRARIES MASSACHUSETTS INSTITUTE OF TECHNOLOGY BARKER41 May 2001 ©2001 Massachusetts Institute of Technology. All Rights Reserved. A u th o r ................................................................................................... Department of Electrical Engineering and Computer Science May 21, 2001 C ertified by ............................ ........... Duane S Boning Associate Professor of Electrical Engineering and Computer Science Theis Supervisor Accepted by .............. ..... Arthur C. Smith Chairman, Department Committee on Graduate Studies Department of Electrical Engineering and Computer Science I Modeling the Effects of Systematic Process Variation on Circuit Performance by Vikas Mehrotra Submitted to the Department of Electrical Engineering and Computer Science on May 21, 2001 in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science Abstract As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques typically represent the interconnect and device parameter variations as random variables. However, recent studies have shown that strong spatial pattern dependencies exist, especially when considering interconnect variation in chemical mechanical polishing (CMP) processes. Therefore, the total variation can be sep- arated into systematic and random components, where a significant portion of the varia- tion can be modeled based on layout characteristics.
    [Show full text]
  • Qubit Control-Pulse Circuits in SOS-CMOS Technology for a Si:P Quantum Computer
    Qubit control-pulse circuits in SOS-CMOS technology for a Si:P quantum computer Author : S. Ramesh Ekanayake 1, 2 Degree : Doctor of Philosophy (Ph.D.) Supervisors : Dr Torsten Lehmann 1, 2 Co-supervisor : Prof. Andrew S. Dzurak 1, 2 Submitted : 31 Jul, 2008 1 Australian Research Council Center of Excellence for Quantum Computer Technology 2 School of Electrical Engineering and Telecommunications Intentionally left void THE UNIVERSITY OF NEW SOUTH WALES Thesis/Dissertation Sheet Surname or Family name: EKANAYAKE First name: SOBHATH Other name/s: RAMESH Abbreviation for degree as given in the University calendar: Ph.D. School: Electrical Engineering and Telecommunications Faculty: Engineering Title: Qubit control-pulse circuits in SOS-CMOS technology for a Si:P quantum computer Abstract 350 words maximum: (PLEASE TYPE) Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non- adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full- digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process – a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators. Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes.
    [Show full text]
  • Charge Trapping Dynamics Associated to MOSFET
    Abstract The evolution of semiconductor industry and material science has proven to be of great importance in most aspects of contemporary society. Metal-Oxide- Semiconductor (MOS) transistors in Integrated Circuits (IC) have assumed acentralpositioninmodernelectronicdevicesasthebrickunitsthatbuild this gigantic industry. The integration density has grown exponentially since their introduction in the 1960s with the aim of increasing their performance. Gordon Moore identified this trend in 1965, predicting the doubling of compo- nents in each technological generation in what we know as the Moore’s Law, leading to uninterrupted and stringent efforts to comply with it. To keep track with the roadmap, we have observed technological innovations such as the shrinking of the device dimensions from the micrometer to the nanome- ter scale, the introduction of new materials in the fabrication steps and the progressive abandonment of the planar design in favor of three-dimensional (3D) structures. Regrettably, the long-term reliability of the transistor perfor- mance was compromised with the introduction of these advances. On top of that, the fundamental physical background behind the transistor’s detrimental performance is still not entirely understood but the general agreement on the explanation is defect generation during the device operation over time, partic- ularly in the semiconductor-oxide interface. These oxide charges and interface traps dynamically interacting with the semiconductor charge contribute sig- nificantly to the electrical degradation. Eventually, the simulation, modeling, and characterization of defects degrading the transistor performance became an unavoidable subject of study. In the past, as purely electrical characteri- zation techniques could not entirely explain the complex phenomena affecting either the gate-oxide or the interface between the gate-oxide and the silicon substrate, some studies have employed a second variable additionally to the electrical techniques to fill the gaps in the comprehension of trapping effects (e.g.
    [Show full text]
  • Improvement of Silicon Oxide Quality Using Heat Treatment
    University of Kentucky UKnowledge Theses and Dissertations--Electrical and Computer Engineering Electrical and Computer Engineering 2012 IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT Lei Han University of Kentucky, [email protected] Right click to open a feedback form in a new tab to let us know how this document benefits ou.y Recommended Citation Han, Lei, "IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT" (2012). Theses and Dissertations--Electrical and Computer Engineering. 5. https://uknowledge.uky.edu/ece_etds/5 This Master's Thesis is brought to you for free and open access by the Electrical and Computer Engineering at UKnowledge. It has been accepted for inclusion in Theses and Dissertations--Electrical and Computer Engineering by an authorized administrator of UKnowledge. For more information, please contact [email protected]. STUDENT AGREEMENT: I represent that my thesis or dissertation and abstract are my original work. Proper attribution has been given to all outside sources. I understand that I am solely responsible for obtaining any needed copyright permissions. I have obtained and attached hereto needed written permission statements(s) from the owner(s) of each third-party copyrighted matter to be included in my work, allowing electronic distribution (if such use is not permitted by the fair use doctrine). I hereby grant to The University of Kentucky and its agents the non-exclusive license to archive and make accessible my work in whole or in part in all forms of media, now or hereafter known. I agree that the document mentioned above may be made available immediately for worldwide access unless a preapproved embargo applies.
    [Show full text]
  • Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems
    Journal of Low Power Electronics and Applications Article Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems Jennifer Hasler *, Sihwan Kim and Farhan Adil Electrical and Computer Engineering (ECE), Georgia Institute of Technology, Atlanta, GA 30332-250, USA; [email protected] (S.K.); [email protected](F.A.) * Correspondence: [email protected]; Tel.: +1-404-894-2944; Fax: +1-404-894-4641 Academic Editor: Tony Tae-Hyoung Kim Received: 4 March 2016; Accepted: 19 July 2016; Published: 27 July 2016 Abstract: This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50–100 MHz frequency ranges could be envisioned to operate at 500 MHz–1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths. Keywords: floating-gate devices; FPAA; hot-electron injection; electron tunneling; scaling FPAA architectures This paper discusses scaling of Floating-Gate (FG) devices, and the resulting implication to larger systems, such as large-scale Field Programmable Analog Arrays (FPAA). Figure1 shows our high level figure, connecting the properties of FG circuits and systems in one technology (e.g., 350 nm CMOS), and predicting the behavior and advantages in smaller technologies.
    [Show full text]