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Charge Trapping Dynamics Associated to MOSFET

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Charge Trapping Dynamics Associated to MOSFET Abstract The evolution of semiconductor industry and material science has proven to be of great importance in most aspects of contemporary society. Metal-Oxide- Semiconductor (MOS) transistors in Integrated Circuits (IC) have assumed acentralpositioninmodernelectronicdevicesasthebrickunitsthatbuild this gigantic industry. The integration density has grown exponentially since their introduction in the 1960s with the aim of increasing their performance. Gordon Moore identified this trend in 1965, predicting the doubling of compo- nents in each technological generation in what we know as the Moore’s Law, leading to uninterrupted and stringent efforts to comply with it. To keep track with the roadmap, we have observed technological innovations such as the shrinking of the device dimensions from the micrometer to the nanome- ter scale, the introduction of new materials in the fabrication steps and the progressive abandonment of the planar design in favor of three-dimensional (3D) structures. Regrettably, the long-term reliability of the transistor perfor- mance was compromised with the introduction of these advances. On top of that, the fundamental physical background behind the transistor’s detrimental performance is still not entirely understood but the general agreement on the explanation is defect generation during the device operation over time, partic- ularly in the semiconductor-oxide interface. These oxide charges and interface traps dynamically interacting with the semiconductor charge contribute sig- nificantly to the electrical degradation. Eventually, the simulation, modeling, and characterization of defects degrading the transistor performance became an unavoidable subject of study. In the past, as purely electrical characteri- zation techniques could not entirely explain the complex phenomena affecting either the gate-oxide or the interface between the gate-oxide and the silicon substrate, some studies have employed a second variable additionally to the electrical techniques to fill the gaps in the comprehension of trapping effects (e.g. temperature, radiation). This thesis has focused on experimentally study- ing the trapping/de-trapping dynamics in the semiconductor-oxide interface by iii iv introducing a second-order effect applying magnetic fields. The two main types of defects, slow (or deep) and fast (or shallow) traps, are addressed through this novel experimental approach. The coupled magneto-conductivity effect may help to gain insight in the trapping effects that lead to the degradation in the performance of the transistor, and subsequent implication in the circuit reliability. Resumen La evolución en la industria de semiconductores y ciencia de materiales ha probado ser de gan importancia en muchos aspectos de la sociedad con- temporánea. Los transistores Metal-Óxido-Semiconductor (MOS) en circuitos integrados (IC) han asumido un papel central en dispositivos electrónicos mod- ernos como las unidades básicas que construyen esta industria. La densidad de integración de estos dispositivos ha crecido exponencialmente desde su intro- ducción en los años sesenta, con el propósito de incrementar su rendimiento. Gordon Moore identificó esta tendencia en 1965, donde predijo el incremento de componentes al doble en cada nueva generación tecnológica, en lo que cono- cemos como la Ley de Moore, y que requiere esfuerzos constantes y rigurosos para cumplirla. Para continuar con la hoja de ruta, hemos observado algunas innovaciones tecnológicas como la reducción de las dimensiones de los disposi- tivos desde la escala micrométrica a la nanométrica, la introducción de nuevos materiales en los procesos de fabricación y el abandono gradual del diseño planar hacia estructuras tridimensionales. Lamentablemente, la fiabilidad a largo plazo del rendimiento del transistor se vio afectada con la introducción de estos avances tecnológicos. Por si fuera poco, aun no se comprende del todo la física fundamental responsable de la deficiencia del rendimiento del transis- tor, aunque hay un acuerdo general en que la explicación está relacionada a la generación de defectos durante la operación del dispositivo a lo largo del tiempo, particularmente en la interfaz óxido-semiconductor. Estas cargas en el óxido y trampas en la interfaz que interactúan constantemente con la carga en el semiconductor contribuyen a la degradación eléctrica. Era de esperar que la simulación, el modelado y la caracterización de defectos que desgastan el rendimiento del transistor se volvieran temas de estudio. Anteriormente, debido a que las técnicas de caracterización puramente eléctricas no podían explicar completamente el fenómeno que afectaba tanto al óxido de compuerta como a la interfaz con el sustrato de silicio, algunos estudios utilizaron una segunda variable adicional a la caracterización eléctrica para llenar los hue- cos que existían en los efectos de atrapamiento (temperatura, radiación, etc.). v vi Esta tesis se enfoca en estudiar de manera experimental la dinámica de atra- pamiento/liberación de carga en la interfaz óxido semiconductor a través de la introducción de un efecto de segundo orden aplicando campos magnéti- cos. Los dos tipos principales de defectos se estudian utilizando esta novedosa aproximación experimental: trampas "lentas" (o profundas), y "rápidas" (o superficiales). El efecto combinado de magneto-conductividad podría ayudar acomprendermejorlosefectosdeatrapamientoquellevanaladegradación del rendimiento del transistor, y sus consecuencias en la confiabilidad a nivel circuital. Acknowledgements Me gustaría agradecer al Consejo Nacional de Ciencia y Tecnología (CONA- CyT) por haberme otorgado la beca durante mis estudios de doctorado. Quisiera expresar mi gratitud principalmente al Dr. Edmundo A. Gutiérrez D. por su guía y apoyo a través del programa doctoral. Esta gratitud la extiendo también al Dr. Francisco Gámiz y sus colaboradores, especialmente al Dr. Carlos Márquez, por haberme dado la oportunidad de trabajar bajo su supervisión en el Laboratorio de Nanoelectrónica en CITIC-UGR (Granada, España), muchos de los resultados reportados en este trabajo vienen del tiempo que trabaje ahí. Me gustaría además agradecer a GlobalFoundries por los fondos que financiaron este y otros proyectos. Este trabajo refleja también muchas discusiones con gente del área y mis ami- gos, expreso mi gratitud al Dr. Joel Molina, Dr. Reydezel Torres, Dr. Adrián Tec, Dr. Héctor Uribe, Jairo Méndez y René Valderrama, y al resto de amigos de INAOE. ALizbethRoblesporsuapoyoypaciencia. Amispadresyhermanosporcreerenmi. vii Contents Abstract iii Resumen v Acknowledgements vii List of Figures xi 1Introduction 1 1.1 Background . 1 1.2 Outline................................ 5 2Theoreticalframework 7 2.1 Hot carrier degradation . 7 2.2 Bias temperature instability . 10 2.3 Gate-Oxidebreakdown . 12 2.4 Chargetrappingdynamics . 14 3Methodology 17 3.1 MOSFET devices and parameter extraction . 17 3.1.1 ThresholdVoltageextraction . 19 3.1.2 Maximum transconductance and subthreshold swing . 20 3.1.3 Mobilityextraction . 21 3.2 The charge pumping technique . 22 3.3 Random Telegraph Signals and noise measurements . 24 3.3.1 Random Telegraph Signals . 24 3.3.2 Noise measurements . 28 3.4 Experimentalprotocol . 31 ix Contents x 4Charge-pumpingmeasurementsundermagneticfields 35 4.1 Experimentalsetupandmethodology . 35 4.2 Results and discussion . 36 4.2.1 Analysis for B =0 ..................... 37 6 5RTNandnoisemeasurementsundermagneticfields 43 5.1 Experimentalsetupandmethodology . 44 5.2 Results and discussion . 44 5.2.1 Analysis for B =0T .................... 50 6 6Conclusions 57 Bibliography 61 List of Figures 1.1 General structure of the bulk MOS transistor. 2 1.2 TEM of a high- dielectric plus a metal gate. The complex dielectric stack includes a SiO2 transition layer. Reproduced from [1]. 3 1.3 Semiconductor band diagram illustrating the location and en- ergy position of interface traps. 4 2.1 The degradation and recovery phases in time. 10 2.2 The Reaction-Diffusion model. Si-H bonds are broken at the Si- SiO2 followed by a Hydrogen diffusion into the oxide, leaving electrically active interface traps. 11 2.3 a) The missing atoms generate unpaired valence electrons in the surface and generate interface traps. b) After oxidation, the majority of states are filled with oxygen atoms. c) After annealing, interface defects is reduced by the Hydrogen bonding withtheremainingstates. 13 2.4 Energy band diagram of a pMOS transistor in weak inversion. The Fermi energy level defines the filling and the net charge. 15 3.1 The experimental setup performs the measurement via Semi- conductor Device Analyzer connected to either a test fixture to characterize the INAOE transistors, or to a probe station to characterizethe250nmtransistors. 18 3.2 Examples of the I-V traces for two separate devices: INAOE and 250nm transistors. 19 3.3 Threshold voltage definition via the second derivative method. Extractedfrom[2]. ......................... 20 3.4 The charge pumping technique is performed through the above experimental setup. Usually, drain and source are tied together whenreversebiased. ........................ 22 3.5 The charge pumping technique yields the five-region curve. a) The biasing conditions that lead to the characteristic Icp current in b). 23 xi List of Figures xii 3.6 An example of a signal affected by the stochastic trapping/de- trapping into oxide traps. The ID current fluctuates between two levels when a single oxide trap is activated. 25 3.7 Simplified energy band diagram for a transistor
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