Abstract
The evolution of semiconductor industry and material science has proven to be of great importance in most aspects of contemporary society. Metal-Oxide- Semiconductor (MOS) transistors in Integrated Circuits (IC) have assumed acentralpositioninmodernelectronicdevicesasthebrickunitsthatbuild this gigantic industry. The integration density has grown exponentially since their introduction in the 1960s with the aim of increasing their performance. Gordon Moore identified this trend in 1965, predicting the doubling of compo- nents in each technological generation in what we know as the Moore’s Law, leading to uninterrupted and stringent efforts to comply with it. To keep track with the roadmap, we have observed technological innovations such as the shrinking of the device dimensions from the micrometer to the nanome- ter scale, the introduction of new materials in the fabrication steps and the progressive abandonment of the planar design in favor of three-dimensional (3D) structures. Regrettably, the long-term reliability of the transistor perfor- mance was compromised with the introduction of these advances. On top of that, the fundamental physical background behind the transistor’s detrimental performance is still not entirely understood but the general agreement on the explanation is defect generation during the device operation over time, partic- ularly in the semiconductor-oxide interface. These oxide charges and interface traps dynamically interacting with the semiconductor charge contribute sig- nificantly to the electrical degradation. Eventually, the simulation, modeling, and characterization of defects degrading the transistor performance became an unavoidable subject of study. In the past, as purely electrical characteri- zation techniques could not entirely explain the complex phenomena affecting either the gate-oxide or the interface between the gate-oxide and the silicon substrate, some studies have employed a second variable additionally to the electrical techniques to fill the gaps in the comprehension of trapping effects (e.g. temperature, radiation). This thesis has focused on experimentally study- ing the trapping/de-trapping dynamics in the semiconductor-oxide interface by
iii iv introducing a second-order effect applying magnetic fields. The two main types of defects, slow (or deep) and fast (or shallow) traps, are addressed through this novel experimental approach. The coupled magneto-conductivity effect may help to gain insight in the trapping effects that lead to the degradation in the performance of the transistor, and subsequent implication in the circuit reliability. Resumen
La evolución en la industria de semiconductores y ciencia de materiales ha probado ser de gan importancia en muchos aspectos de la sociedad con- temporánea. Los transistores Metal-Óxido-Semiconductor (MOS) en circuitos integrados (IC) han asumido un papel central en dispositivos electrónicos mod- ernos como las unidades básicas que construyen esta industria. La densidad de integración de estos dispositivos ha crecido exponencialmente desde su intro- ducción en los años sesenta, con el propósito de incrementar su rendimiento. Gordon Moore identificó esta tendencia en 1965, donde predijo el incremento de componentes al doble en cada nueva generación tecnológica, en lo que cono- cemos como la Ley de Moore, y que requiere esfuerzos constantes y rigurosos para cumplirla. Para continuar con la hoja de ruta, hemos observado algunas innovaciones tecnológicas como la reducción de las dimensiones de los disposi- tivos desde la escala micrométrica a la nanométrica, la introducción de nuevos materiales en los procesos de fabricación y el abandono gradual del diseño planar hacia estructuras tridimensionales. Lamentablemente, la fiabilidad a largo plazo del rendimiento del transistor se vio afectada con la introducción de estos avances tecnológicos. Por si fuera poco, aun no se comprende del todo la física fundamental responsable de la deficiencia del rendimiento del transis- tor, aunque hay un acuerdo general en que la explicación está relacionada a la generación de defectos durante la operación del dispositivo a lo largo del tiempo, particularmente en la interfaz óxido-semiconductor. Estas cargas en el óxido y trampas en la interfaz que interactúan constantemente con la carga en el semiconductor contribuyen a la degradación eléctrica. Era de esperar que la simulación, el modelado y la caracterización de defectos que desgastan el rendimiento del transistor se volvieran temas de estudio. Anteriormente, debido a que las técnicas de caracterización puramente eléctricas no podían explicar completamente el fenómeno que afectaba tanto al óxido de compuerta como a la interfaz con el sustrato de silicio, algunos estudios utilizaron una segunda variable adicional a la caracterización eléctrica para llenar los hue- cos que existían en los efectos de atrapamiento (temperatura, radiación, etc.). v vi
Esta tesis se enfoca en estudiar de manera experimental la dinámica de atra- pamiento/liberación de carga en la interfaz óxido semiconductor a través de la introducción de un efecto de segundo orden aplicando campos magnéti- cos. Los dos tipos principales de defectos se estudian utilizando esta novedosa aproximación experimental: trampas "lentas" (o profundas), y "rápidas" (o superficiales). El efecto combinado de magneto-conductividad podría ayudar acomprendermejorlosefectosdeatrapamientoquellevanaladegradación del rendimiento del transistor, y sus consecuencias en la confiabilidad a nivel circuital. Acknowledgements
Me gustaría agradecer al Consejo Nacional de Ciencia y Tecnología (CONA- CyT) por haberme otorgado la beca durante mis estudios de doctorado.
Quisiera expresar mi gratitud principalmente al Dr. Edmundo A. Gutiérrez D. por su guía y apoyo a través del programa doctoral. Esta gratitud la extiendo también al Dr. Francisco Gámiz y sus colaboradores, especialmente al Dr. Carlos Márquez, por haberme dado la oportunidad de trabajar bajo su supervisión en el Laboratorio de Nanoelectrónica en CITIC-UGR (Granada, España), muchos de los resultados reportados en este trabajo vienen del tiempo que trabaje ahí.
Me gustaría además agradecer a GlobalFoundries por los fondos que financiaron este y otros proyectos.
Este trabajo refleja también muchas discusiones con gente del área y mis ami- gos, expreso mi gratitud al Dr. Joel Molina, Dr. Reydezel Torres, Dr. Adrián Tec, Dr. Héctor Uribe, Jairo Méndez y René Valderrama, y al resto de amigos de INAOE.
ALizbethRoblesporsuapoyoypaciencia.
Amispadresyhermanosporcreerenmi.
vii
Contents
Abstract iii
Resumen v
Acknowledgements vii
List of Figures xi
1Introduction 1 1.1 Background ...... 1 1.2 Outline...... 5
2Theoreticalframework 7 2.1 Hot carrier degradation ...... 7 2.2 Bias temperature instability ...... 10 2.3 Gate-Oxidebreakdown ...... 12 2.4 Chargetrappingdynamics ...... 14
3Methodology 17 3.1 MOSFET devices and parameter extraction ...... 17 3.1.1 ThresholdVoltageextraction ...... 19 3.1.2 Maximum transconductance and subthreshold swing . . 20 3.1.3 Mobilityextraction ...... 21 3.2 The charge pumping technique ...... 22 3.3 Random Telegraph Signals and noise measurements ...... 24 3.3.1 Random Telegraph Signals ...... 24 3.3.2 Noise measurements ...... 28 3.4 Experimentalprotocol ...... 31
ix Contents x
4Charge-pumpingmeasurementsundermagneticfields 35 4.1 Experimentalsetupandmethodology ...... 35 4.2 Results and discussion ...... 36 4.2.1 Analysis for B =0 ...... 37 6 5RTNandnoisemeasurementsundermagneticfields 43 5.1 Experimentalsetupandmethodology ...... 44 5.2 Results and discussion ...... 44 5.2.1 Analysis for B =0T ...... 50 6 6Conclusions 57
Bibliography 61 List of Figures
1.1 General structure of the bulk MOS transistor...... 2 1.2 TEM of a high- dielectric plus a metal gate. The complex dielectric stack includes a SiO2 transition layer. Reproduced from [1]...... 3 1.3 Semiconductor band diagram illustrating the location and en- ergy position of interface traps...... 4
2.1 The degradation and recovery phases in time...... 10 2.2 The Reaction-Diffusion model. Si-H bonds are broken at the Si- SiO2 followed by a Hydrogen diffusion into the oxide, leaving electrically active interface traps...... 11 2.3 a) The missing atoms generate unpaired valence electrons in the surface and generate interface traps. b) After oxidation, the majority of states are filled with oxygen atoms. c) After annealing, interface defects is reduced by the Hydrogen bonding withtheremainingstates...... 13 2.4 Energy band diagram of a pMOS transistor in weak inversion. The Fermi energy level defines the filling and the net charge. . 15
3.1 The experimental setup performs the measurement via Semi- conductor Device Analyzer connected to either a test fixture to characterize the INAOE transistors, or to a probe station to characterizethe250nmtransistors...... 18 3.2 Examples of the I-V traces for two separate devices: INAOE and 250nm transistors...... 19 3.3 Threshold voltage definition via the second derivative method. Extractedfrom[2]...... 20 3.4 The charge pumping technique is performed through the above experimental setup. Usually, drain and source are tied together whenreversebiased...... 22 3.5 The charge pumping technique yields the five-region curve. a) The biasing conditions that lead to the characteristic Icp current in b)...... 23 xi List of Figures xii
3.6 An example of a signal affected by the stochastic trapping/de- trapping into oxide traps. The ID current fluctuates between two levels when a single oxide trap is activated...... 25 3.7 Simplified energy band diagram for a transistor having a single trap in the gate oxide...... 27 3.8 Schematics of the noise measurement. A single specialized in- strument performs the tasks...... 30 3.9 Noise spectrum density vs frequency for a transistor biased at VG =500mV . Inset shows different noise sources encountered inMOStransistors...... 30 3.10 Summarized experimental protocol to characterize interface an oxide traps under the influence of magnetic fields...... 31 3.11 The magneto-modulated performance parameters: a) ID,b) VTH and STH,c)gm,andd)mobilityfora20µm/20µm INAOE transistor...... 33 3.12 The proportional difference between the measurements at B = 0T and B =0T .Forthreeseparatedevices,themagneticfield 6 exerts a stronger effect when driven in the subthreshold regime. 34
4.1 The concentration of traps over the whole range of Vbase. The maximum current can be seen as two overlapping concentration of traps, each located in energy at different positions...... 37 4.2 When the rise/fall times of the gate pulse is higher, recombi- nation current reduces due to carriers needing more time to be energized into the trap states...... 38 4.3 a) The magneto-modulated trap concentration reveals that the maximum concentration of traps in the plateau is increased by the B field. b) Region marked as "2" is affected more than region marked as "1" by the magnetic field...... 39 4.4 In INAOE transistors, the trap concentration responds differ- ently to the application of the magnetic field. The "N" shaped characteristic is consistent with the extracted parameters in sec- tion3.4...... 40
5.1 a) Representative noise characteristic of a transistor, following a 1/f trend. b) the experimental and model normalized drain current power spectral density at f =10Hz ...... 45 2 5.2 The SID/ID VG plot extracts the bias range where the de- vice is affected by trapping phenomena from the bell shaped characteristic ...... 47 5.3 RTN Time traces for distinct gate voltages. The times spent in the high and low current state apparently vary with VG...... 48 List of Figures xiii
5.4 Time domain data represented in the TLP space at different VG. Two well-defined states appear in the diagonal in each graph, suggesting trapping occurs into a single oxide trap. The color scale indicates the weighted number of events. Results for a transistor with tox =14nm...... 49 5.5 a) ⌧c and ⌧e with the gate voltage in transistors with tox = 14nm.(b)thelogarithmoftheratiodefinesthelocationand energy position of the trap...... 50 2 5.6 The SID/ID VG plot under different magnitudes the magnetic field. The noise power increment at B = 200mT occurs with VG 700mV ...... 51 ⇡ 5.7 a) A 1/f 2 behavior is observed instead of the 1/f depicted at B =0T . b) The CNF and Hooge mobility models agree, al- though a slightly different than the case when B =0T .No- tice the pronounced increment and subsequent reduction of the 6 spectral density at around ID 10 A, which corresponds to ⇡ VG 0.7V ...... 52 ⇡ 5.8 The RTSs in the TLP space for a)B =+200mT ,b)B = 200mT ,c)B =110mT and d) B = 110mT , showing a weak effect of the B field. In the four cases, two states are well-defined. The color scale indicates the weighted number of events...... 53 5.9 Normalized spectral density of the noise with the gate voltage in the absence of the magnetic field (black) and under the influence of four perpendicular to channel magnetic fields. Frequency = 20Hz. Measurements for the transistor with tox =7nm...... 54 5.10 The TLP representation of a RTN signal at a)B =200mT , b)B = 200mT ,c)B =110mT and d)B = 110mT .One transition between two states is evident in b) and c). In a) and d), a second transition is induced, indicating a second trap joins in the trapping phenomena. The color scale indicates the weighted number of events. Inset of plots a) and c) shows the two-level drain current in time domain when a single trap is present, and the inset of plots b) and d) indicate the new trap emergence as a three-level drain current...... 56
6.1 a) The energy levels in a quantum well at B=0T. b) The energy levelsareshiftedatB=200mT...... 58
Chapter 1
Introduction
1.1 Background
Figure 1.1 illustrates the general structure of the MOS transistor. Typically, the four contacts (gate, drain, source and bulk) are electrically stimulated in order to control the charge concentration in the channel through the MOS capacitance, blocking or conceding the charge carriers to flow typically from source to drain. This is the fundamental phenomenon behind the operation of the transistor as a switch in digital applications. To maximize performance, that is, to increase the switching speed and reduce the consumed energy dur- ing operation, studies have focused on improving the control over the carrier transport in the channel region. The efforts aimed at shrinking the MOS tran- sistor dimensions to the nanometer range, primarily the gate oxide thickness in conjunction with the channel length. The development of technological tech- niques reached an impressive level at manufacturing a few SiO2 atomic layers as gate dielectric material [3, 4]. However, tunneling effects leading to gate leakage current impede further reducing beyond 1nmthickSiO2 as, below ⇠ this range, electric degradation could potentially make the device useless as a logic element [5, 6]. Second-order effects associated to tunneling phenomena degrade the device overall performance over time and, for this reason, the rate
1 Chapter 1 Introduction 2
Gate Oxide SSource Drain
Bulk
Figure 1.1: General structure of the bulk MOS transistor. of escalation was attenuated. Conversely, these issues increased the motivation for studying alternative materials or novel device structures. The introduction of high materials, as well as using metal gates as opposed to poly-silicon gates (used in SiO2 technology), solved some of the problems by making pos- sible to keep the same gate capacitance with lower leakage currents [7, 8]. On the other hand, high materials in direct bonding with silicon yields a high density of interface traps, and they were integrated in the fabrication process of the MOS transistor using a different approach. The need of an underlying
SiO2 layer to keep stability over the carrier transport in the channel [8] re- sulted in a complex dielectric stack (Figure 1.2), revealing previous and novel reliability phenomena, the most important being defect generation in the ox- ide, which can lead to undesired gate leakage current and trapping-induced instabilities. In this context, potential dielectric breakdown was one particular concern [5, 8]. In addition, transistors could also experience progressive para- metric degradation, led by the gradual trapping of charge in the oxide [3, 9].
Threshold voltage (VTH)shiftisusuallytheonsetofthisparametricdegrada- tion of the MOS transistor triggering instabilities in the transconductance, the maximum cut-off frequency, the subthreshold swing, and consequently affect- ing the maximum driving capability of the channel current. Furthermore, some of the trapping phenomena exhibit recovery effects, in which the generated ox- ide traps during operation get partially passivated -or electrically deactivated- when electrical stress is reduced, a phenomena termed Bias Temperature Insta- bility (BTI), a voltage and temperature dependent effect that hitherto remains Chapter 1 Introduction 3
Figure 1.2: TEM of a high- dielectric plus a metal gate. The complex dielectric stack includes a SiO2 transition layer. Reproduced from [1]. under debate. Hot carrier injection (HCI) is another major reliability concern in which highly energetic carriers in the channel generate defects in the oxide that could potentially lead to dielectric breakdown [10]. The highly energetic carriers are originated by impact ionization from the elevated electric fields as consequence of device dimensions reduction and implementation of high- materials.
The common factor in these degradation mechanisms are defects in the structure of the dielectric and the interface with the silicon substrate. Con- sequently, defect control and further characterization became relevant topics of research. When studied at atomic level, such defects refer to a vacancy, aself-interstitial,anantisite,animpurity,oranycombinationofthosesin- gular defects (clusters, interfaces, grain boundaries, surfaces, etc.), generated in the fabrication process, both intentionally and unintentionally, as well as during device regular operation. The latter arises from the bond breaking in the semiconductor-oxide interface by a combination of electric field and tem- perature variation (temperature fluctuates during high-performance IC opera- tion), resulting in oxide or interface traps. In terms of energy, they are located throughout the Si bandgap, as in Figure 1.3. That physical location and energy position very close to the inverted channel leads to continuous trapping/de- trapping of carriers, especially into those located in the semiconductor-oxide interface (interface traps). The interaction with the surface channel triggers Chapter 1 Introduction 4
Semiconductor D it E Empty c
Ef e d Ei Oxi
Ev Occupied
Figure 1.3: Semiconductor band diagram illustrating the location and energy position of interface traps. carrier injection into the oxide and contributes to gate leakage current, low fre- quency noise, reduced mobility and drain current driving capability, although the whole physical picture is not entirely understood [3, 11]. Despite the amount of data, there is still room for discussion. The critical energy that needs to be applied so that the traps can be activated, the origin of these traps (pre-existant before stress but not active or induced by electrical stress), how to determine whether trapping effects will lead to recovery (BTI) or not (HCI), and if recovery exists, which fraction of recovery comes from interface or oxide traps, are some of the aspects that remain unknown.
Much of the information regarding traps come from common characteri- zation techniques determining the interface traps, such as the Direct-current current-voltage method (DCIV), charge pumping, and capacitance-voltage plots. For oxide traps, there are some other like Low-Frequency-Noise (LFN), Deep- Level Transient Spectroscopy (DLTS) and Random Telegraph Noise (RTN) associated phenomena. However, these purely electrical characterization tech- niques proved hard to provide elemental and structural information on the charge trapping phenomenology and, by themselves, were insufficient to iden- tify the defects responsible for electrical activity. Therefore, much of the mi- croscopic information about these mechanisms now come from electrical tech- niques combining optical and/or thermal experimental approaches [12–14]. Chapter 1 Introduction 5
The use of magnetic fields is one particular tool that has gain visibility in recent years, used primarily in spintronics studies [15, 16]. The applica- tion of magnetic fields coupled with traditional electrical techniques can be used to investigate electronic properties of the trapping phenomenology. In- deed, there have been some studies that combine both the effect of trapping phenomenology with magnetic fields with the purpose of spin control in elec- tronic devices [17, 18]. In them, the magnetic fields are extensively applied at high magnitudes (> 1T )inalowtemperatureenvironment( 4K and be- ⇠ low). Here, however, we took an unexplored path to investigate trapping phe- nomenology by typical characterization techniques in conjunction with "low" magnetic fields (< 1T ), at room temperature. Some works [19, 20] have ex- hibited uncomprehended responses of the MOS transistor under these unique measuring conditions, especially in the channel and gate oxide current. We have introduced the experimental findings on the effect of the magnetic fields on the trapping phenomenology for several MOS technologies, under different magnetic field magnitudes.
1.2 Outline
This thesis guides the reader through the elemental physics of trapping phe- nomenology leading to the most important degradation mechanisms and how to gain insight into the phenomenon by performing some characterization tech- niques under the influence of magnetic fields:
Chapter 2 describes the most important degradation mechanisms found in literature, where the trapping phenomenology has proved to be a crucial effect implicated in all reliability issues (Hot carrier injection, Bias Tempera- ture Instability and Oxide breakdown). Consequently, this chapter addresses a general overview on the charge trapping dynamics. Chapter 3 introduces the experimental approach that serves to characterize traps in MOS transistors. They are studied to evaluate the quality of the semiconductor-oxide interface by forcing trapping/de-trapping effects using the charge-pumping technique Chapter 1 Introduction 6
(to study fast or shallow traps) and the RTN approach (to study slow or deep traps). Additionally, the complementary information we can obtain from applying magnetic fields is introduced. Chapter 4 focuses on the experimen- tal findings using the charge-pumping method under magnetic fields in MOS transistors fabricated in different technology nodes. Chapter 5 describes the experimental results by triggering RTN effects, under the influence of magnetic fields as well. The results are accompanied by noise measurements revealing information on oxide traps. The discussion revolves around the deviations found when contrasting the results in the absence and presence of magnetic fields. Finally, this thesis ends with Chapter 6 presenting the summarized ideas and challenges yet to overcome, as well as future directions. Chapter 2
Theoretical framework
To understand the physical processes implicated in the reliability evaluation of MOS transistors, the three well-accepted degradation mechanisms will be briefly discussed in this chapter. Additionally, it contains a review on some of the topics that remain unanswered. All the mechanisms described below are found in transistors with SiO2 as dielectric material, but the description can be extended to transistors with alternative materials, i. e. with high-. The most important characteristic considered as the cause for device degradation is the presence of traps inducing charge modulation in the channel that leads to carrier injection into the gate dielectric. For this reason, a general overview of the phenomenological description of the traps implicated in the trapping dynamics is presented as well.
2.1 Hot carrier degradation
Hot carriers are highly energetic charge particles flowing in the channel of a MOS transistor accelerated by high lateral electric fields, affecting both n-type and p-type transistors. When the channel is inverted and a drain-source volt- age is applied (VD =0), charge carriers travel from the source towards the 6
7 Chapter 2 Theoretical framework 8 drain, gaining energy from the applied electric field, primarily by those carri- ers in the region where the lateral electric field is the highest (this would be the drain end in case this electrode was biased). The distribution of the kinetic en- ergy of carriers in this area mimics a population at a temperature higher than the mean temperature of the silicon lattice, and those charge carriers are said to become "hot". Accelerated by the electric field, they can generate interface or oxide traps, followed by carrier injection into the gate dielectric that results in high gate leakage currents (in case a sufficiently large population reaches the gate), as well as high substrate currents (acting as an additional driving force for carriers in the surface). Both undesired currents are typically measured to evaluate the consequences of hot carriers. The presence of traps in the gate oxide and at the Si SiO2 interface yields local surface potential variations leading to parametric degradation of the MOS transistor, the most important being threshold voltage shifts. These phenomena significantly reduce the op- erating lifetime of the transistors, especially in modern devices with deeply scaled dimensions [6, 21]. There are four markedly injection mechanisms re- lated to hot carriers: channel hot electron (CHE), drain avalanche hot carrier (DAHC), secondary generated hot electron (SGHE) and substrate hot electron (SHE).
Channel hot electron injection: In here, electrons gain sufficient energy to surmount the Si SiO2 barrier at the drain end in the channel, when the gate voltage is approximately equal to the drain voltage (VG = VD). Under this condition, the gate current IG can be measured to calculate the CHE effect.
At VG Drain avalanche hot carrier injection: The DAHC injection is notable with high VD and mid VG.Avalanchemultiplicationbyimpactionizationisthe cause of this injection mechanism where carriers gain energy from the lateral electric field. The avalanche multiplication phenomena leading to electron-hole Chapter 2 Theoretical framework 9 pairs generation consequently contributes to the substrate current IB as well, complicating the measurement of DAHC injection. Secondary generated hot electron: Aside from the electron-hole pairs gen- erated by the high electric field in the drain region, photons are additionally generated, inducing a secondary generation process for electron-hole pairs, leading again to avalanche multiplication phenomena. Photo-induced gener- ated carriers contribute to SGHE injection. Substrate hot electron: Substrate carrier injection comes from substrate bias VB. Carriers in the bulk driven to the Si SiO2 interface gain kinetic energy in the surface, contributing to the generation-injection cycle described in the above mechanisms. In SHE, as the stress conditions are well-defined in the interface due to the energetic carriers being uniformly distributed along the channel (in contrast, the maximum of the injection occurs at the drain end in the above mechanisms), it is majorly forced to occur for reliability tests [21]. The oxide field, the carrier energy, and the current intensity can be adjusted independently to investigate the trapping dynamics in MOS transistors. In spite of the well-known qualitative description of hot carrier injection, some aspects remain unknown. Literature proves hard to describe the exact contribution from each injection mechanism to the total IG and IB.Addition- ally, the internal temperature variation as a result of the impact ionization, a variable often assumed to be constant, may lead to self-heating and phonon- assisted trapping effects [21]. This is particularly important as in real circuits transistors are subjected to gate and drain bias variating in time, where IG and IB will be the result of the combined effect of all the above injection mecha- nisms. If found, both currents could be treated as indicators for the energy and thermal distribution of carriers in the channel due to hot carrier stress. To complicate things even more, it is not clear how the gate oxide trapping effects are most affected by each type of carrier, as both electrons and holes are present in hot carrier degradation as minority and majority carriers. Chapter 2 Theoretical framework 10 stress stress removed ) most Vt (V recovered Vt (t=0) time Figure 2.1: The degradation and recovery phases in time. 2.2 Bias temperature instability Bias Temperature Instability (BTI) could reduce significantly the operating lifetime of the device, specially in deeply scaled down transistor dimensions with advanced materials, becoming a forefront reliability concern. By defini- tion, BTI is a reliability issue affecting the electrical characteristics of the MOS transistor by high voltages at elevated temperatures (often encountered during high performance IC), as consequence of trap generation at the Si SiO2 in- terface and the dielectric. The accelerated bond-breaking at the interface over time induces charge trapping effects that shift the threshold voltage, reduce the channel mobility due to scattering, and induce drain current degradation over time. The characteristics under study include recovery effects upon removal of stress (Figure 2.1), microscopics of degradation over time, the activation energies of trapping dynamics, frequency and material dependence. The recovery effects are the most important topic, still under debate, lead- ing to higher operating lifetimes for transistors at AC stress, but complicating the characterization techniques to investigate it [11, 22]. For the latter, ac- celerated characterization tests using higher bias and temperatures than the usual operating conditions are performed, where the characteristic BTI time- dependence is extracted, and the results are projected for estimating device lifetimes. Although some questions underlying this effect have since then be Chapter 2 Theoretical framework 11 Gate Dielectric Silicon Figure 2.2: The Reaction-Diffusion model. Si-H bonds are broken at the Si-SiO2 followed by a Hydrogen diffusion into the oxide, leaving electrically active interface traps. answered, others still remain open. Despite being around for decades [23], there is no consensus on the exact physical mechanism behind the performance insta- bilities (several models have been proposed), but there is general agreement on charge building up in the interface or in the oxide layer as the cause of the para- metric degradation of the MOS transistor, and the Reaction-Diffusion (R-D) model has been well-accepted to explain this trap generation under BTI stress [11, 22]. The model illustrated in Figure 2.2 is a two-step process: at first, afield-dependentelectrochemicalSi-Hbondbreakingtakesplace,followedby interface trap generation as consequence of releasing hydrogen during this re- action phase. Subsequently, in the diffusion phase, such hydrogen is drawn away from the interface into the gate oxide at a certain rate. Similarly, the inverse process is possible, where diffusion of hydrogen from the oxide back to the interface yields passivation of Si- dangling bonds. While there is little controversy on the acceptance of the R-D describing the BTI phenomenon, both the trap generation phase and the recovery mech- anism are not entirely clear yet. The discussion is centered around the experi- mental results strongly depending on the characterization methods, measuring conditions and the MOS transistor features such as geometry, size and materi- als. Moreover, the degradation effect has shown different behavior for different processing modifications such as dopants, thermal annealing treatments or nitridation techniques. At microscopic level, the gaps in our understanding Chapter 2 Theoretical framework 12 address the exact role of oxide charges in the dielectric, the contribution of each type of traps (electron and hole traps) and their origin (induced by stress or pre-existant). 2.3 Gate-Oxide breakdown The optimum operation of the MOS transistor relies on the excellent insula- tor properties of the gate oxide (poor electrical conductivity and large energy bandgap). There is a maximum electric field that the gate dielectric sustains before the insulator properties are irreversibly lost, allowing electrical current to flow through the oxide. This occurs by the formation of a conductive path in the dielectric material(s) and the phenomenon is known as the dielectric break- down, the ultimate outcome of degradation. Generally, the insulator wears out after some time under electrical stress until it finally breakdowns entirely. The mechanism is ascribed as a two-step process: at first, a progressive damage builds up in the oxide and finally, an abrupt generation of a breakdown path takes place. A wide variety of models have been proposed describing the degra- dation process, such as the anode-hole injection, the electron trap generation, or the percolation theory, to name a few. Anode-hole injection: This model suggests electrons tunneling through the gate oxide can transfer the excess energy to an electron in the valence band of the gate electrode, leaving a hot hole when promoted to the conduction band. Hence, this hole can tunnel back to the oxide, generating oxide traps. When a critical quantity is reached, breakdown occurs. Electron trap generation: In this model, breakdown occurs by the forma- tion of a conducting path of oxide traps. To trigger it, a critical electron trap density must be generated by electrical stress. This quantity is independent of the oxide thickness in this model. Percolation model: During electrical stress, oxide traps are generated at a certain rate and distributed at random positions in the dielectric. When two Chapter 2 Theoretical framework 13 a) b) c) Figure 2.3: a) The missing atoms generate unpaired valence electrons in the surface and generate interface traps. b) After oxidation, the majority of states are filled with oxygen atoms. c) After annealing, interface defects is reduced by the Hydrogen bonding with the remaining states. or more traps are located closely together, a conducting path is formed in which charge can flow from one trap to the other. Just in the same way, when collections of conducting paths hit a critical defect density with cumulative stress, these "clusters" will be arranged in such a way that charge may flow through the oxide towards the gate electrode followed by an instantaneous large gate current increase (for hard breakdown), a small gate current increase with a sudden gate current noise (for soft breakdown) or a progressive gate current increase (for progressive breakdown). From the microscopic point of view, it is well known that dielectric break- down is directly related to the formation of a chain of traps, interface states, defects, hole traps, and slow states linked to the origin of the mechanism. However, the random nature of the phenomena (varying from sample to sam- ple and dependent from the stressing conditions) has brought some topics that remain under investigation, such as the link between the hole carriers, the oxide thickness, the critical electron trap concentration and the breakdown events, including reversible breakdowns in Metal-Insulator-Metal structures (MIM) for memristive devices. Chapter 2 Theoretical framework 14 2.4 Charge trapping dynamics The discrepancy found in our understanding of the degradation mechanisms encourages researches to focus on the charge trapping/de-trapping effects, a fundamental phenomenon in all reliability issues. To understand the trapping phenomenology, we need to investigate the nature of Si SiO2 interface. In the crystalline structure, the silicon atom requires bonding with other neighboring silicon atoms to fully saturate the valance shell. However, at the surface (in the Si SiO2 interface), the silicon crystal does not perfectly bond with other atoms, and traps are generated (Figure 2.3). For MOS transistors with SiO2 as dielectric material, the density of these interface traps is approximately 10 2 1 10 cm eV after annealing techniques using hydrogen or nitrogen atoms [24, 25], giving first class Si SiO2 interfaces, albeit it is important to keep in mind that the Si-H and Si-N2 bonds generated after passivation are responsible for some degradation mechanisms. The resulting dangling bonds are termed Pb centers for Si3 Si in (111) oriented substrates, while in (100) orientations ⌘ • they are termed Pb0 for Si3 Si and Pb1 for Si2O Si .Allofthesedangling ⌘ • ⌘ • bonds reflect back in the forbidden silicon bandgap as trap levels, or shallow levels, being capable of both donating and accepting electrons from the sil- icon band edges [26], meaning they are of amphoteric nature. Their energy distribution is illustrated in figure (Figure 2.4). The charge state of the traps depend on whether they are occupied or empty and the type of the trap: Donor-like energy level: Located above the valence band edge in the lower half bandgap, the trap levels are neutrally charged when occupied by electrons and positively charged when emptied. Acceptor-like energy level: Located below the conduction band edge in the upper half bandgap, the trap levels are negatively charged when occupied by electrons and electrically neutral when emptied. Another important defect is the E’ center. Although the exact nature and physical location is still under debate [26, 27], they are known to be oxide Chapter 2 Theoretical framework 15 SiO2 Silicon Figure 2.4: Energy band diagram of a pMOS transistor in weak inversion. The Fermi energy level defines the filling and the net charge. traps in the SiO2, but electrically interacting with the Si SiO2 interface as well. The E’ centers reflect as trap levels close to the middle of the silicon band gap, referred to as deep levels. The charge state in all traps is given by the location of the Fermi level in the silicon. Correspondingly, the Fermi level moves with the application of voltages to the gate, source, drain and substrate electrodes as this process induces band bending in the surface in order to create the inversion channel and move carriers from point to point. This modulation effect in conjunction with the electrically active energy levels present in the MOS transistor are the origin of trapping/de-trapping effects that cause instabilities in the electrical characteristics of electronic devices. The reader must have in mind that the physical location as well the energy position of traps vary from transistor to transistor, and consequently each individual transistor exhibits a unique re- sponse to an specific trap. However, statistical values are reported throughout the literature. The charge trapping dynamics are well-represented by phonon transitions following the Shockley-Read-Hall recombination model [28, 29]. The trap- assisted process requires energy from phonons (the silicon lattice vibrations) Chapter 2 Theoretical framework 16 and releases energy in the same form. The process can be summarized in four possible mechanisms: Electron capture: From the conduction band, an electron is captured by an empty trap. Hole capture: Atrappedelectronmovestothevalancebandneutralizinga hole (a hole from the valance band is captured by a trap). Hole emission: From the valance band, an electron is trapped, leaving a hole behind (a hole is emitted from the trap to the valance band) Electron emission: Atrappedelectronmovestotheconductionband. Several characteristics can be determined from the SRH theory taking into account the nature of the trap (acceptor or donor like traps) and the electron or hole concentrations, as well as the trap concentration, in the band edges, assuming stationary conditions. However, in transient conditions often encoun- tered in the regular operation of the MOS transistor, the rate of trapping and de-trapping effects complicates the study by eliminating some simplifications in SRH theory, such as the capture and release rate being equal. The method- ology described in chapter 3 includes some of the characterization techniques performed to investigate trapping phenomenology, both for shallow and deep levels in MOS transistors. Chapter 3 Methodology This chapter introduces the experimental methodology used in order to inves- tigate the charge trapping dynamics implicated in reliability issues of MOS transistors. The characterization techniques address the two basic classes of defects that affect the electrical activity in the channel, the interface and ox- ide traps. The charge-pumping technique selected for the study of interface traps has proven to be a versatile tool for extracting accurate characteristics of such traps, while the RTN approach accompanied by noise measurements has accounted for investigating the phenomenology of trapping due to oxide traps. In extensive studies, the user does not often need a deep understand- ing of the fundamental principles involved in the characterization techniques, the measurement equipment does all the job. Instead, the basic measurement principles need to be fully comprehended to analyze the experimental results in detail in this thesis. Such electrical characterization techniques were performed whilst applying external magnetic fields at different magnitudes. 3.1 MOSFET devices and parameter extraction The selected MOS transistors as test vehicles to investigate the trapping effects under magnetic fields are: 17 Chapter 3 Methodology 18 DUT Semiconductor Device Analyzer DUT Figure 3.1: The experimental setup performs the measurement via Semi- conductor Device Analyzer connected to either a test fixture to characterize the INAOE transistors, or to a probe station to characterize the 250nm transistors. INAOE nMOSFET: The samples featuring poly-silicon as gate material have thermally grown SiO2 as dielectric material (tox =60nm). 250nm nMOSFET: Samples fabricated at IBM facilities feature a tox = 14nm and below. First, the electrical performance of the MOS transistor is conventionally evalu- ated from current vs voltage (I V )characteristics.Fromthesemeasurements, some of the electrical parameters of the device such as the threshold voltage (VTH), subthreshold swing (STH), maximum transconductance (gmmax), or mobility, can be extracted. Figure 3.1 illustrates the basic experimental set-up to carry out the electrical measurements. The INAOE transistors, encapsu- lated in package, were electrically characterized using an Agilent B1500a semi- conductor analyzer (SDA). The 250 nm MOS transistors, diced from the wafer, were characterized in a Janis probe station by the same SDA. The equipment biases the transistor electrodes and extracts the current or voltage charac- teristics through Source-Measurement-Units (SMU). Figure 3.2 illustrates the I V characteristics of the above transistors fabricated in different technology generations. Chapter 3 Methodology 19 30 Vg=3 V Tox=60nm Vg=2.6 V W=L=20µm Vg=2.2 V Vg=1.8 V 20 Vg=1.4 V ( µA) D I 10 0 0 1 2 3 Drain Voltage (V) 400 Vd = 0.4 V Vd = 0.8 V 300 Vd=1.2 V ( µA) 200 D I 100 Tox=14nm W=L=700nm 0 0 2 4 6 Vg(V) Figure 3.2: Examples of the I-V traces for two separate devices: INAOE and 250nm transistors. 3.1.1 Threshold Voltage extraction The threshold voltage is defined as the gate bias necessary to fulfill S =2 B, where S and B are the surface potential and the potential difference between the bulk Fermi-level and the intrinsic Fermi-level, respectively. This definition comes from a one-dimensional analysis of the MOS capacitor [30]. From the phenomenological point of view, it is the gate bias condition where the minority carrier density is equated to the bulk majority carrier density, driving the transistor from depletion into inversion. There are a number of experimental techniques to extract Vth[2], however only one method with proven accuracy was selected to avoid variability among results, the second derivative method. Chapter 3 Methodology 20 1 × 10−3 8 × 10−4 /V) S −4 ( 6 × 10 S G V /d −4 m 4 × 10 g d VT = 0.98 V 2 × 10−4 0v104 0 0.511.52 Gate Voltage (V) Figure 3.3: Threshold voltage definition via the second derivative method. Extracted from [2]. In the ideal case, where VG VTH. The non-ideal case (Id =0for VG 3.1.2 Maximum transconductance and subthreshold swing The channel transconductance shows the rate of change of the drain current with the gate bias for a given VD, directly calculated by the following equation using the measured ID VG characteristics at low VD: @ID gm = (3.1) @VG V =0 ✓ ◆ D6 The subthreshold swing STH allows to estimate how "fast" the ION /IOFF transition takes place by the gate voltage, represented as the shift in VG needed to change ID by one order of magnitude. By definition, it can be calculated Chapter 3 Methodology 21 from: kT Cox + CD STH = ln10 (3.2) q C ✓ ◆✓ ox ◆ where T is the temperature, k the Boltzmann constant, q the elemental charge, Cox the oxide capacitance, and CD the capacitance in depletion. In experi- mental measurements, a logID linear dependence with VG is observed in the subthreshold region for VD >kT/q,thecalculusoftheinverseofthisslope yields STH. 3.1.3 Mobility extraction A universal behavior of mobility of carriers in the channel is observed when uniquely analyzing the impact of the transverse electric field, applied to the gate electrode, on the carrier velocity [31]. This effective mobility µeff can be calculated as: gdL µeff = (3.3) WQn where L is the gate length, W the width, Qn the mobile channel charge density 2 (C/cm ), and gd the drain conductance, defined as: @ID gd = (3.4) @VD V =0 ✓ ◆ G6 The Qn extraction is carried out by the following expression: Qn = Cox(VG VTH) (3.5) Albeit having some deficiencies, experimental results have shown good agree- ments with this approach [2, 31–33]. From ID VG measurements, µeff is calculated with VD typically in the range of 50-100mV , or below, to ensure a channel charge uniformity from source to drain [2, 33]. Physically, µeff means the proportional constant between the carrier velocity and the total effective electric field affecting an average carrier, this effective field takes into account Chapter 3 Methodology 22 G Oxide S D B A Figure 3.4: The charge pumping technique is performed through the above experimental setup. Usually, drain and source are tied together when reverse biased. the full effect of the depletion layer, but only a portion of the inversion layer [33]. 3.2 The charge pumping technique The technique introduced in [34], widely used for precise estimations of the in- terface trap concentration (Nit), allows in-depth analysis of the semiconductor- oxide interface of the MOS transistor, often used for reliability evaluations of such devices. The charge-pumping method is considered a versatile tool to in- vestigate trapping phenomenology given the development of several variations of the basic technique in order to extract detailed information on the energy and physical distribution of interface traps [2, 35]. This experimental tool was selected to study fast traps due to the well-accepted phenomenological expla- nation of the method, the high sensitivity to the trap density, and the basic equipment required for the measurements. Figure 3.4 illustrates the basic ex- Chapter 3 Methodology 23 a) b) 5 ∆V 4 3 V Vg 3 TH Icp 2 4 2 Vfb 1 1 5 Vbase Vbase Figure 3.5: The charge pumping technique yields the five-region curve. a) The biasing conditions that lead to the characteristic Icp current in b). perimental set up for a nMOS transistor. Source and drain to substrate diodes are slightly reverse bias. The gate is then pulsed-bias, driving the surface from accumulation into inversion, while monitoring the substrate current. During the inversion phase, minority carriers (electrons in a nMOS transistor) injected from the source and drain regions occupy the channel area and some of them become trapped in interface states. When the surface is driven towards accu- mulation, the minority carriers leave the channel, flowing back to source and drain, except for those trapped carriers if the gate is rapidly pulsed, and the majority carriers from the substrate driven to the surface recombine with the trapped minority carriers. The identical process takes place in the accumu- lation back to the inversion phase, with opposite type of carriers, leading to anetchargepumpedateachcycle.Ifthecycleisrepeatedatacertainfre- quency, this charge leads to a constant measurable current proportional to the concentration of interface traps Nit. The approach introduced by Elliot in [36] was selected among the different methods performed for charge-pumping measurements [35], given its capability to determine the energy distribution of interface states. This method sweeps the base level of the gate voltage pulse Vbase to drive the MOS transistor from accumulation into inversion, assuming an amplitude of the pulse VA larger than VTH Vfb, where Vfb is the flatband voltage. The resulting measurement yields five regions, illustrated in Figure 3.5: Chapter 3 Methodology 24 Region 1: When Vbase&Vtop Region 2: With Vbase Region 3: At Vbase Region 4: When Vfb Region 5: During Vbase >VTH, the surface is permanently inverted with traps filled with minority carriers. Zero Icp is measured again, unless other leakage currents contribute as well [35, 38]. 3.3 Random Telegraph Signals and noise mea- surements 3.3.1 Random Telegraph Signals Random Telegraph Signal (RTS) consists of the drain current ID randomly switching between discrete levels by the stochastic trapping/de-trapping of carriers from the channel into traps located at a close tunneling distance from the inversion layer, a phenomenon first reported in [39]. The phenomena gained agreatdealofinterestduetomoderndevicesreducingtheoperationalcur- rent to levels comparable to the fluctuations induced by RTS, which resulted Chapter 3 Methodology 25 Vg = 400 mV Vd = 50 mV (0.1nA/div) D I Time (s/div) Figure 3.6: An example of a signal affected by the stochastic trapping/de- trapping into oxide traps. The ID current fluctuates between two levels when a single oxide trap is activated. in reliability issues that limit the performance of such devices, especially in submicron memories, CMOS image processors, and deeply scaled technologies (nanowires, carbon Nanotubes, etc.[40, 41]). However, when studied in detail, RTS provides valuable information regarding the transport properties of the MOS transistor, particularly on the semiconductor-oxide interface. The exper- imental characterization is carried out by monitoring the drain current ID in a long enough time window to observe as many trapping/de-trapping events as possible, since the analysis of RTS is often carried out through statistical approaches given the random nature of the phenomena [29, 42]. The equip- ment scans for capture/release events linked to a particular trap energy range by the proper selection of the sampling rate, i. e., slow states (oxide traps) reflect back to the drain current as fluctuations in the millisecond range, but fast states (interface traps) require sampling rates below this range. In the simple case often encountered in modern devices, the drain current fluctuates between two possible values by the presence of a single oxide trap [39]. Multi- level transitions reported as well, appear as consequence of fast traps affecting ID,duetoahigherdensityofinterfacetraps(Dit)closetothebandedges, but proven difficult to measure. The current signal is characterized by esti- mating the difference between the high and low current levels ID,thetimes spent between capture events, as well as the time between de-trapping events. With the appropriate characterization tools, important parameters, such as the nature of the trap (donor or acceptor like state), the energy level of the trap ET ,thebarrierforcarriercapture,orthedepthandthelateralposition of the trap respect to the channel, can be extracted. Most of the proposed Chapter 3 Methodology 26 approaches describe the carrier capture and emission by standard Shockley- Read-Hall (SRH) theory in many cases to extract such parameters [43, 44]. In this scenario, assuming a n-channel transistor, the average capture time for a carrier in the inversion layer is given by: 1 ⌧c = (3.6) nvth where n is the electron volume concentration (proportional with ID), vth the thermal velocity for electrons, and the capture cross-section; while the emis- sion time is described as: 1 EF ET ⌧e = exp (3.7) gnv ⇤ k T th ✓ B ◆ where EF is the surface Fermi level, kB the Boltzmann’s constant, T the tem- perature, g the trap degeneracy factor. The latter is usually unknown and assumed equal to 1 [29, 45]. The energy level of the trap can be determined by the ratio: ⌧c ET EF = g exp (3.8) ⌧ ⇤ k T e ✓ B ◆ The unknown parameter ET can be extracted from the analysis of the simplified band diagram illustrated in Figure 3.7. From this schematic: x E E = (E E ) (q q )+ T ( V + V q ) T F cox T s ox s t | fb| G s ox (3.9) where Ecox is the minimum of the dielectric conduction band, s the semi- conductor work function, ox the electronic affinity of the oxide, tox the ox- ide thickness, and xT the physical position of the trap calculated from the semiconductor-oxide interface. The following expression is obtained from equa- tion 3.8 and 3.9: ⌧ 1 x ln c = (E E ) (q q )+ T ( V + V q ) ⌧ k T cox T s ox s t | fb| G s e B ox (3.10) Chapter 3 Methodology 27 Figure 3.7: Simplified energy band diagram for a transistor having a single trap in the gate oxide. The derivative of equation 3.10 with respect to VG yields the trap position: t k T d ln(⌧ /⌧ ) d x = ox B c e + s T d s (3.11) 1! ⇤ q dVG dVG dVG ✓ ◆ With typical locations of oxide traps affecting the drain current around 1-2nm away from the interface [45], ET can be determined from equation 3.9. It be- comes evident from these equations that the process is thermally activated, and the room temperature condition is sufficient to energize the trapping/de- trapping process. From the foregoing, complementary measurements varying temperature while scanning RTSs provide additional information on the trap- ping phenomenology, but the temperature effect is out of the scope of this thesis. Chapter 3 Methodology 28 3.3.2 Noise measurements RTSs have an impact on the noise signature of MOS transistors, as such, it has been suggested that the typical Low-Frequency-Noise behavior found in MOS transistors is composed of multiple RTSs with different time constants [42, 46]. Consequently, in addition to time domain analysis of trapping phe- nomenology linked to RTSs, measurements in the frequency domain, required to investigate the noise characteristics, complement this study. The measure- ments are accompanied by the extraction of the noise power in the frequency domain, an essential characteristic defined as the noise power spectral density (PSD). Aside from the RTSs, some other fundamental sources of noise con- tribute to the characteristic behavior: thermal noise, shot noise, flicker noise, and Generation-Recombination (G-R) noise [2]. In brief, thermal noise is at- tributed to the random motion of charge carriers leading to small fluctuations in the current. Shot noise relates to the discrete nature of charge transport, considering the current is not a continuum but rather a sequence of carrier "packets" traveling towards an electrode. Both sources of noise exist in practi- cally all electronic systems but they are negligible in magnitude when measured against the following. Flicker noise,orLow Frequency Noise (LFN), arises from fluctuations in the charge transport caused by stochastic trapping/de-trapping of carriers in the channel into traps, which results in mobility and carrier density variations that lead to drain current fluctuations in a MOS transistor. There are es- sentially two competing models based on the individual contribution of each parameter (carrier or mobility fluctuations) on the noise signal. Those are the McWhorter number fluctuation theory and the Hooge mobility fluctuation approach [46]. Both are supported by experimental evidence despite the inter- twined effect between one and the other on the drain current characteristics. Flicker noise, identified sometimes as 1/f noise, prevails at low frequencies in the noise spectrum with a characteristic 1/f response. G-R noise is caused by the generation and recombination of electron-hole pairs, which results in the random variation of carrier density in the inversion Chapter 3 Methodology 29 layer. The noise spectrum proportional to the square of the current corresponds to a Lorentzian-like spectrum with the maximum at low frequencies, followed by a 1/f 2 roll-off. The noise signature of RTSs resembles that of the G- R noise, with a different physical origin attributed to carrier trapping/de- trapping in a single oxide trap. When many trapping events occur having different time characteristics, the summation of their individual RTSs yields a 1/f characteristic signature. Noise measurements demand specialized equipment in a controlled en- vironment to extract accurate results, for this reason this characterization method is neither extensively examined nor applied as often as other tech- niques. In recent years, however, noise gained visibility as a tool to get insight into the degradation mechanisms by studying trapping phenomenology. As mentioned earlier, noise signals in MOS transistors are characterized by the extraction of the current PSD in the frequency domain, but in different VG steps, to scan for traps in different energy ranges in the bandgap. First of all, an I-V amplifier magnifies the small magnitude current fluctuations. Then, the power of the augmented signal is calculated and most suitably expressed as the noise PSD using the Fast-Fourier-Transform algorithm. The tasks are performed through a low-noise programmable bias amplifier (BPA) controlled by a computer with a dedicated software. Figure 3.8 shows the experimental setup to perform the aforementioned tasks, whereas Figure 3.9 illustrates an example of the measurement. Chapter 3 Methodology 30 Figure 3.8: Schematics of the noise measurement. A single specialized instrument performs the tasks. Figure 3.9: Noise spectrum density vs frequency for a transistor biased at VG = 500mV . Inset shows different noise sources encountered in MOS transistors. Chapter 3 Methodology 31 -300 mT < B < +300 mT I-V characteristics Charge-pumping Noise measurements: Spectral Scanning Random Telegraph Noise Figure 3.10: Summarized experimental protocol to characterize interface an oxide traps under the influence of magnetic fields. 3.4 Experimental protocol The systematic characterization protocol is summarized in Figure 3.10. At first, measurements are performed at room temperature in the absence of the magnetic fields. The same characterization method is then repeated but under the influence of external magnetic fields at different magnitudes B,ranging from -300 mT to +300mT. The electrical parameters are subsequently exam- ined for every magnitude of B.Forin-packagedevices,themagneticfield is externally applied using a GMW 5403AC electromagnet, where the Device- Under-Test (DUT) is placed between two poles in such a way that the magnetic field hits the sample perpendicularly. The magnitude and sign of B is given by the direction and the intensity of the current flowing in the poles. For devices diced from the wafer, the DUT is placed in the center of neodymium permanent magnetic rings. In this case, the dimensions of the ring defines the magnitude of B, while the orientation determines the sign of B.Priortoanalyzethe charge trapping dynamics, the electrical characteristics and some performance parameters should be extracted in the selected devices using the conventional techniques described in section 3.1 to identify the classical Lorentz’ force, which deflects carriers in the channel by the application of magnetic fields. Chapter 3 Methodology 32 The next step in the characterization protocol is to analyze the dynamic trapping effects into interface states by performing the charge-pumping tech- nique described in section 3.2. By the variation of the frequency, the ampli- tude, and the rise/fall times of the gate pulse, additional information can be extracted from the Icp. Slow traps are then examined through the characterization protocol devel- oped by Marquez et al. [47], via noise measurements and RTSs. As described in section 3.3, noise measurements use an experimental setup which biases the DUT, and measures the current and the fluctuations by a low noise current/- voltage amplifier connected to a high-resolution Analog-Digital converter, then performs the Fourier analysis with a spectrum analyzer and, after all, records and displays the data. RTSs are then measured: following the description in section 2.4 and 3.3, only specific devices are suitable to be affected by RTSs, considering that the time constants and the current amplitude dependent on the trap energy level and the Fermi energy in the surface, which are properties that vary between samples and depend on the bias conditions. The use of the Spectral Scanning by Gate Bias( SSGB) approach [47], which analyzes the noise characteristic response of the drain current (detailed in chapter 5), pre- vents elongated and repetitive measurements in the selection of devices affected by RTSs. The method additionally determines the bias conditions where the device is most likely affected by individual traps. Upon selection of the device and determination of the optimum bias range, sampling measurements of the drain current are recorded at a 2ms sampling rate for 200s. As an example to demonstrate the magneto-modulation effect, the I-V characteristics and some of the performance parameters are contrasted in the absence and presence of B,depictedinFigure3.11.Recentworks[19,20]have examined this magneto-modulation effect, in which carrier re-allocation in the inversion channel due to carrier deflection results in localized modulations of threshold voltage, transconductance, and some other electrical parameters. Furthermore, carriers are forced to flow in a non-homogeneous channel with anisotropic conductance, due to variability in the fabrication process, which contribute to this localized parametric variations. These conclusions are the Chapter 3 Methodology 33 a) b) 1.56 134.00 5.8×10-7 ∆Id vs Vg 300mT Vth & S ∆Id = (Id - Id ) 50mT -7 B≠0 B=0 4.7×10 Vd = 2.4 V -50mT 133.00 -300mT 1.55 3.6×10-7 S (mV/Dec) Sub. Slope 132.00 -7 1.54 Id (A) 2.5×10 ∆ Vth (V) 131.00 1.4×10-7 Vth 1.53 3.0×10-8 130.00 -8.0×10-8 1.52 0 1 2 3 4 5 -300 -200 -100 0 100 200 300 Vg (V) B (mT) c) d) 10 Gmax vs B 2.14×10-6 ∆ Mobility at different B 2.12×10-6 5 /Vs) 2 2.10×10-6 0 Gmax (s) 2.08×10-6 Mobility (cm Δ -5 100mT 300 mT -6 2.06×10 -100mT -300mT 5 5 5 5 -300 -200 -100 0 100 200 300 5.50×10 5.74×10 5.98×10 6.22×10 E (V/cm) B (mT) eff Figure 3.11: The magneto-modulated performance parameters: a) ID, b) VTH and STH, c) gm, and d) mobility for a 20µm/20µm INAOE tran- sistor. basis of this work, as the parametric variation is closely related to trapping phenomenology. An example of this correlated effect is demonstrated in Figure 3.12. I-V measurements in various transistors fabricated under different tech- nology generations have confirmed that a transistor experiences the strongest magneto-modulation effect when driven in the subthreshold-weak inversion regime, which has proven conveniently to be the region with the most evident impact of trapping effects in the electrical characteristics. Chapter 3 Methodology 34 30.0 Octagonal nFET 250 nm nFET INAOE nFET 20.0 (%) D I ∆ Vth 10.0 ∆Id/Id(%) vs Vg B = -300 mT 0.0 0 1 2 3 4 5 Vg (V) Figure 3.12: The proportional difference between the measurements at B =0T and B =0T . For three separate devices, the magnetic field exerts 6 a stronger effect when driven in the subthreshold regime. Chapter 4 Charge-pumping measurements under magnetic fields An investigation into the dynamic trapping of interface states was conducted in nMOS transistors with the charge-pumping technique performed at room tem- perature under the influence of perpendicular-to-the-surface magnetic fields. Devices fabricated under two different technologies were characterized using the experimental method described in section 3.2. The concentration of in- terface traps was calculated from the charge-pumping current measured at different magnitudes of the B field. The analysis presented in this chapter re- vealed the pumped current was magneto-modulated as a result of the magnetic field probably altering the trapping dynamics. Furthermore, the experimental findings suggests that both electrons and holes are affected differently by the magnetic field. 4.1 Experimental setup and methodology The INAOE and the 250 nm transistors were selected as test vehicles. The former features a gate oxide thickness of 60nm, with a (W/L) aspect ratio of (20µm/20µm). The 250nm transistors, diced from the wafer and fabricated 35 Chapter 4 Charge-pumping measurements under magnetic fields 36 at IBM facilities, feature an oxide thickness of 14nm, with gate length and width of 700nm. All devices feature SiO2 as dielectric material. Following the methodology described in section 3.2, prior to characterize the interface states, the pulse-base-level method requires the extraction of the VTH, Vfb and VA > VTH Vfb. The reverse voltage is applied by a B1500A SDA through Source- Measurement-Units. The pulse signal is then applied to INAOE transistors via the HP33120A waveform generator, and to the 250 nm transistors through a Semiconductor Pulse Generator Unit (SPGU). The Nit is calculated from the maximum charge pumped current Icp in the Icp Vbase plot as: Icp = qAGfNit (4.1) The Icp was measured at two frequencies (100KHz and 1MHz), and the rise/fall times of the gate pulse was varied to extract further information. The experimental characterization protocol was repeated at room temperature but with static perpendicular-to-the-surface magnetic fields B ranging from -300 mT to +300 mT. 4.2 Results and discussion The results of the experimental measurements at B =0are depicted in fig- ures 4.1 and 4.2. The maximum Nit agrees with transistors having thermally oxidized silicon as gate dielectric material ( 1010, [24, 25]). The reduced ⇠ Nit for f =1MHz in all devices has indeed been widely reported [35, 48–50] and attributed to the time spent in inversion/accumulation being sufficiently short that only interface traps can contribute to the CP current, as opposed to shorter frequencies (f =100KHz), where traps located at a certain distance away from the interface may contribute to the measured data. Figure 4.1 additionally shows two possible maximum values of Nit,over aspecificVbase range. The explanation to this phenomenon is understood through the analysis of the Nit response when the fall/rise times of the gate Chapter 4 Charge-pumping measurements under magnetic fields 37 Figure 4.1: The concentration of traps over the whole range of Vbase. The maximum current can be seen as two overlapping concentration of traps, each located in energy at different positions. pulse is changed (Figure 4.2). As indicated in [51], the total Nit can be treated as two overlapping concentrations of traps where each individual curve would correspond to a trap concentration located in different energy ranges. This approach becomes further important when studying the effect of the magnetic field on the trapping dynamics in the interface. 4.2.1 Analysis for B =0 6 The application of the magnetic field while performing the charge-pumping technique resulted in a Nit displacement, dependent on the magnitude of the B field (Figure 4.3). The recovery in Nit to the original value upon removal of the magnetic field indicates no generation of new traps during the measurements, which suggests that the effect is associated to a modification of the charge trapping dynamics. Chapter 4 Charge-pumping measurements under magnetic fields 38 Figure 4.2: When the rise/fall times of the gate pulse is higher, recom- bination current reduces due to carriers needing more time to be energized into the trap states. Following section 3.4, the answered might be found in the re-allocation of charge carriers in the surface by the magnetic field. The reconstructed car- rier distribution would modify the surface potential and, therefore, the band bending in the surface. This characteristic ultimately determines the posi- tion of the surface Fermi-energy relative to the trap energy level, which in the end, defines the occupied/emptied state of the trap. The local shift on the Fermi-level as consequence of carrier re-distribution would then either block or favor trapping into specific interface traps, and this certainly would not fol- low a monotonic trend with B,butwouldratherdependontheinterfacetrap energy and space distribution. From the foregoing, the displacement of the Fermi-level to an energy position closer to the trap energy level than the case for B =0T would lead to an increment in the Nit. The opposite would occur when Nit reduces. This hypothesis is supported by Figure 4.3, which depicts the magneto-modulated interface trap concentration per unit area Nit,de- fined as Nit = NitB=0 NitB=0.The analysis over the entire Vbase range shows 6 Chapter 4 Charge-pumping measurements under magnetic fields 39 a) ) 1 2 -2 5.4 B=-200mT m c · B=-110mT 10 B=0 T E 5.1 (1 B=+110mT t i N B=+200mT 4.8 -0.45 -0.40 -0.35 -0.30 -0.25 Vbase(V) b) 1 2 0.2 B=-200mT B=-110mT it B=+110mT N 0.1 ∆ B=+200mT 0.0 -0.6 -0.4 -0.2 0.0 Vbase(V) Figure 4.3: a) The magneto-modulated trap concentration reveals that the maximum concentration of traps in the plateau is increased by the B field. b) Region marked as "2" is affected more than region marked as "1" by the magnetic field. amaximumvariationbetween 0.4V From Figure 4.3, Nit behaves differently with the magnetic field in the areas marked as ”1” and ”2”. The highest current contribution in region 1 comes from distribution A, whereas distribution "B" impacts the most in region "2". In the presence of magnetic fields, both distributions respond differently, in Chapter 4 Charge-pumping measurements under magnetic fields 40 Figure 4.4: In INAOE transistors, the trap concentration responds differ- ently to the application of the magnetic field. The "N" shaped characteristic is consistent with the extracted parameters in section 3.4. agreement with the hypothesis that the B field introduces a Fermi-level mod- ulation, affecting the trapping dynamics depending on the energy position of the traps. A higher modulation for the trap concentration is observed for the region highlighted as "2" (Vbase around 0.25V )thanregion"1"(Vbase around 0.4V ). Besides, the extracted Nit at B=200mT is higher than the Nit extracted at B=-200mT inside region "1" . The opposite occurs inside region "2". It is important to notice that Nit behaves differently outside the high- lighted regions. To the left of region "1", the surface is driven most of the time into depletion, where electrons are being pumped to recombine with the holes, indicating a slight increment in the Nit.However,totherightsideof region "2", the surface spends less time in depletion and the hole population to recombine with decreases significantly, the Nit reduces for the specific case of B = 200mT .Alltheseconsidered,themagneticfieldmayaffect electrons and holes differently. Additionally, the local mobility would be different as the population of carriers in the surface are different in both cases, which is an approach along the lines developed in this work. The INAOE transistors were measured as well under the influence of magnetic fields. Figure 4.4 shows that Chapter 4 Charge-pumping measurements under magnetic fields 41 the trap concentration responds with an asymmetric "N"-like characteristic with the B field, contrary to the observed response in the 250 nm transistors. This shape has been reported in section 3.4, exhibited by the electrical parame- ters of this specific transistor upon the application of the magnetic field as well. The alternate response may obey to the differences in the technology genera- tion in which they were fabricated. One possible explanation is attributed to the gate area differences between the two transistors, separated by almost two orders of magnitude. The gate area impacts on the distribution of carriers in the surface, which is more uniform in INAOE transistors, an important char- acteristic if carrier re-allocation is considered as the magnetic field primarily effect. Chapter 5 RTN and noise measurements under magnetic fields Random Telegraph Signals (RTSs), also known as Random Telegraph Noise (RTN), have been experimentally characterized in transistors fabricated in a 250 nm process technology under the influence of perpendicular-to-the-surface magnetic fields at room temperature. The experimental measurements re- ported in this chapter were performed following a systematic characterization protocol detailed in section 3.3. The technique requires from two methods known as the Spectral Scanning by Gate Bias (SSGB) approach, a noise charac- terization technique, and a modified Time Lag Plot algorithm, both described in this chapter. The protocol identifies the number of oxide traps implicated in RTSs and the optimum biasing conditions to facilitate trapping events, a use- ful tool to study the nature of traps. Noise measurements complete this study, providing valuable information in regard of the interaction between the semi- conductor and the oxide. First, the systematic experimental characterization is performed in the absence and, subsequently, in the presence of the magnetic fields. Afterwards, an analysis is presented to gain insight into the transport properties of the transistor under these specific measuring conditions. Exper- imental findings and analysis revealed that the drain-source current exhibits an unexpected Random Telegraph Noise trace, suggesting variations in the 43 Chapter 5 RTN and noise measurements under magnetic fields 44 trapping/detrapping mechanisms depending on the magnitude and direction of the magnetic field. Additionally, the contribution of carrier and mobility fluctuations to the noise signal, as a result of trapping events, is described. 5.1 Experimental setup and methodology A set of 250 nm transistors, whose parameters are described in section 4.1, were experimentally characterized. Prior to the selection of specific transistors affected by RTN, noise measurements are carried out by the SSGB approach [47], detailed in the next section, using the measurement setup described in section 3.3. These measurements yield the optimum bias condition where the transistor is likely to be affected by oxide traps. Upon selection of devices that present the highest trapping/de-trapping events, the time evolution of Random Telegraph Noise has been extracted using a B1500A SDA by monitoring the drain current at a 2ms sampling rate for 200s. For accurate results, the mea- surement was performed at low VD (50mV )toconsidercarriersinthechannel in thermal equilibrium with the lattice. 5.2 Results and discussion The emblematic Power Spectral Density (PSD), i.e. a well-defined Lorentzian- like spectrum, of a transistor with tox =14nm and W/L aspect ratio of 700nm/700nm is depicted in Figure 5.1(a). The 1/f characteristic spectrum of noise measurements is commonly the result of a transistor affected by multiple Random-Telegraph-Signals [52]. Figure 5.1(b) shows the normalized Power Spectral Density (PSD) varying with the drain current ID at a specific fre- quency (10Hz). This frequency is extracted from visual inspection at the point where the maximum of the drain current noise density SID begins to roll off in Figure 5.1(a). At this range, it has been generally accepted that the 1/f behavior in the SID can be described with the McWhorther number Chapter 5 RTN and noise measurements under magnetic fields 45 Figure 5.1: a) Representative noise characteristic of a transistor, following a 1/f trend. b) the experimental and model normalized drain current power spectral density at f = 10Hz fluctuation theory (CNF, [46]), where the SID is expressed as: 2 q Not 2 SID = gm (5.1) LW C 2f ⇤ ✓ ox ◆ Not is given by Not = kBTNt ox, where Nt is the oxide trap density and ox the average tunneling length [46]; the other parameters were defined in previous chapters. The factor in parenthesis is termed the gate voltage spectral density 2 SVG. The division of both sides of equation 5.1 over a ID factor yields a more 2 practical normalized current spectral density SID/ID . SID 2 2 = SVG gm/ID (5.2) ID ⇤ According to this model, electrons that are being trapped and emitted from gate oxide defects cause fluctuations in the channel potential energy, which is reflected back in the drain current ID as noise. However, correlated Chapter 5 RTN and noise measurements under magnetic fields 46 mobility fluctuations contribute to the measured signal as well [53], which in- 2 troduces a factor (1 + µeff CoxID/gm) in the right hand term of eq. 5.2, being ascatteringparameter.Accordingto[46],thesevariationscomefrom Coulomb scattering from carriers trapped in the gate oxide defects that induce afluctuationontheeffective mobility in the inversion layer. In Figure 5.1(b), the SVfb is a fitting parameter as well as and µeff .Inthiscase,modeland experimental data sustain that the carrier number fluctuation (with the corre- lated mobility factor included) contributes significantly to the LFN character- istic at low ID currents, but does not properly fit at larger values corresponding to a higher VG than the subthreshold voltage (VTH 0.5V for these devices). ⇡ Besides the predominantly CNF in Fig. 5.1(b), the Hooge mobility fluctuation model [46] contributes as well, and expressed as: SID aH µeff 2kT 2 = 2 (5.3) ID fL ID where aH is the Hooge parameter. This mobility fluctuation noise con- 7 tributes in the small region right before ID 10 A. The area around this ⇡ current corresponds to VTH so the better agreement is backed up by the diffu- sion to drift transition of the channel conductance in this range. The Spectral Scanning by Gate Bias approach introduced by Marquez et al. in [47], complements the analysis of the noise measurements. The method assumes that the noise spectral density of the transistor follows either a 1/f or 1/f 2 trend with the gate voltage, having maximum values at low frequencies, which is the case depicted in Figure 5.1(a). The SSGB approach is summarized as: 1. Noise measurements are performed as described in section 3.3. 2. The normalized spectral density of the current is calculated. The corner frequency is determined by direct visual inspection. 2 3. The SID/ID is plotted versus the gate voltage at this fc,leadingtoa 2 bell-shaped SID/ID VG curve. Chapter 5 RTN and noise measurements under magnetic fields 47 10-6 B= 0 mT Higher trapping events 10-7 L = 700nm ) 1 - W = 700nm -8 10 Tox = 14nm (Hz 2 Freq = 10Hz D I / Vd = 50 mV V ~ 500mV D -9 TH I 10 S -10 10 Lower trapping events 10-11 0.2 0.4 0.6 0.8 VG (V) Figure 5.2: The S /I 2 V plot extracts the bias range where the device ID D G is affected by trapping phenomena from the bell shaped characteristic 4. The noise power should be proportional to the number of trapping/de- trapping events, for both RTN and flicker noise, i.e., higher spectral densities means higher trapping events. The results from step 1 and 2 are depicted in Figure 5.1(a) and 5.2. The 2 latter illustrates the bell-shaped SID/ID VG curve from step 3 to show the gate bias where the device is affected by trapping phenomena. Step 4 determines that the gate bias range where the device is strongly affected by stochastic trapping/de-trapping is between 250 mV and 500 mV. Upon selection of the bias range, the evolution of RTN in time is char- acterized following section 5.1, to identify the number of traps implicated in the trapping/de-trapping of carriers from the channel, and to extract the time characteristics from the signal (average capture and emission times, a challeng- ing task considering the large amount of measurement data. Figure 5.4 shows some examples of the selected transistors with drain current presenting RTN. A mathematical tool often useful to analyze such data is the Time Lag Plot representation. An enhanced version of the method (wTLP) is performed in Chapter 5 RTN and noise measurements under magnetic fields 48 Figure 5.3: RTN Time traces for distinct gate voltages. The times spent in the high and low current state apparently vary with VG. this analysis, introduced in [47]. The TLP space represents the drain current samples ordered in time. Each point (X,Y) in such space is composed of a drain current sample taken at any instant in time t, and the next sample in time [(X, Y )=(ID(t),ID(t +1))]. Then, a definite area inside the TLP is weighted over the number of events. This approach is often used to rule out the ostensible random nature of events in time series by searching for patterns in the TLP space. For the specific case of RTN, the drain current levels are well identified as populated regions in the diagonal. The drain current time series from Figure 5.4 are represented in Figure 5.5 using the wTLP method. Chapter 5 RTN and noise measurements under magnetic fields 49 ) (nA 1 t+ t a 0.9 d I V = 280 mV VG = 240 mV G ) 0.1 (nA 1 t+ t a d I VG = 460 mV VG = 500 mV Id at t (nA) Id at t (nA) Figure 5.4: Time domain data represented in the TLP space at different VG. Two well-defined states appear in the diagonal in each graph, suggest- ing trapping occurs into a single oxide trap. The color scale indicates the weighted number of events. Results for a transistor with tox = 14nm. The two-level characteristic is the result of trapping into a single oxide trap, represented as two well-defined lobes in the diagonal of the sampling space. The probability to find one sample in either the high or low state is given by the colorful scale. Chapter 5 RTN and noise measurements under magnetic fields 50 Figure 5.5: a) ⌧c and ⌧e with the gate voltage in transistors with tox = 14nm. (b) the logarithm of the ratio defines the location and energy position of the trap. The average time at high- and low- current states correspond to the cap- ture (⌧c)andemission(⌧e) time respectively. These characteristic times are usually shown as a function of the gate bias (Figure 5.5) in order to determine the physical position and energy level of the trap inside the oxide, together with the acceptor (as in this particular case) or donor nature of the trap [52]. Higher VG significantly increases the inversion charge in this regime, which in the case for ⌧c,resultsinanincrementontheprobabilityforacarriertobecap- tured. For ⌧e,theemissionisindependentonVG over a wide bias range, which suggests a thermally activated de-trapping mechanism (thermoionic emission). The trap location in the oxide can be extracted through the characteristic time aspect ratio [Figure 5.3(b)] following Equation 3.11, and the energy of the trap through Equation 3.10. The calculation yields the position of the trap xT =1.05nm,locatedinenergyatEcox ET =2.94eV . 5.2.1 Analysis for B =0T 6 The above methodology, repeated under the influence of magnetic fields, re- 2 sults in the bell shaped characteristic in the SID/ID VG plot(Figure 5.6, Chapter 5 RTN and noise measurements under magnetic fields 51 Figure 5.6: The S /I 2 V plot under different magnitudes the mag- ID D G netic field. The noise power increment at B = 200mT occurs with V 700mV . G ⇡ with a 1/f 2 dependence (Figure 5.7.a). When B = 200mT ,apronouncein- crement and subsequent decrease emerges at the bias range between 650mV < VG < 750mV , which is the region where the normalized drain current spectrum behaves with 1/f 2 in Figure 5.7.a, instead of the 1/f response when B =0T . According to section 3.3, there are two possible explanations to the square frequency dependence. The first one considers the presence of a RTN signal attributed to a single trap, however, this can be discarded since VG is high enough to activate multiple traps, whose individual RTSs would sum to yield a 1/f response. The most likely explanation to this dependance is therefore the generation-recombination phenomena due to trapping centers in the bulk of the device. This noise mechanism is indeed back up in the PSD plot at B = 200mT ,emerginginFigure5.6atVG =0.7V . The exact physical ex- planation on the noise signal is yet under study, but first ideas point to carrier deflection into different crystallographic orientations. The electrical proper- ties depend on the specific orientation in which a traveling carrier is deflected, which in the case of B = 200mT ,mayincreasethegeneration-recombination Chapter 5 RTN and noise measurements under magnetic fields 52 10-5 10-4 (a) (b) Experimental 10-6 CNF 10-5 Mobility model 10-7 ) -6 1 10 - 10-8 1/ 2 (Hz f 2 V = 0.7V -7 -9 G 10 D I 10 / D I 10-10 -8 S 10 L = 700nm 10-11 W = 700nm Tox = 14nm 10-9 Freq = 10Hz 10-12 Vg = 700mV B= -200 mT B= -200 mT 10-10 10-13 100 101 102 103 10-10 10-9 10-8 10-7 10-6 Frequency (Hz) ID(A) 2 - Figure 5.7: a) A 1/f 2 behavior is observed instead of the 1/f depicted at B =0T . b) The CNF and Hooge mobility models agree, although a slightly different than the case when B =0T . Notice the pronounced increment and subsequent reduction of the spectral density at around I 10 6A, which D ⇡ corresponds to V 0.7V .. G ⇡ rate and, therefore, the noise power. If magnetodeflection occurs, then the parameters associated to mobility and scattering phenomena should change upon the application of the B field as well. Figure 5.7.b shows the CNF model and the Hooge mobility adjusted to the experimental results, but using val- ues 1% different than in figure 5.1. Additionally, this parameter adjustment improves the agreement between model and measurements at high VG. How- ever, the noise signal at B = 200mT remains on top of the rest at higher VG than 0.75V .Anincrementinthatareahasbeenattributedtotheseries resistance [54]. The latter reinforces the hypothesis that the carriers are de- flected in such a crystallographic orientation that leads to higher impact of the series resistance and higher trapping/detrapping events due to augmented generation-recombination effects by the magnetic field. The evolution in time of this device presenting RTN is characterized under the influence of magnetic fields. The results depicted in Figure 5.8 confirmed Chapter 5 RTN and noise measurements under magnetic fields 53 0.9 B=+200mT B=-200mT 0.1 B=+110mT B=-110mT 0.9 0.1 Figure 5.8: The RTSs in the TLP space for a)B = +200mT ,b)B = 200mT , c) B = 110mT and d) B = 110mT , showing a weak effect of the B field. In the four cases, two states are well-defined. The color scale indicates the weighted number of events. the observed in the noise measurements, at low VG (where trapping events is maximized) the magnetic field exerts no effect, apparently. The ⌧c and ⌧e additionally demonstrate almost no change in their characteristics as well, so the trapping/de-trapping of carriers into oxide traps basically remains the same. Another sample was analyzed. The selected devices feature tox =7nm with gate length and width of 400nm. The resulting plot from the SSGB approach is depicted in Figure 5.9. As opposed to the above transistor, no Chapter 5 RTN and noise measurements under magnetic fields 54 10-8 Vd=50mV Freq=20Hz W=L=400nm tox=7nm ) -1 10-9 (Hz 2 D B=-200mT / I ID B=-110mT -10 S 10 B=0mT B=+200mT B=+110mT 10-11 0.2 0.4 0.6 0.8 Gate Voltage (mV) Figure 5.9: Normalized spectral density of the noise with the gate voltage in the absence of the magnetic field (black) and under the influence of four perpendicular to channel magnetic fields. Frequency = 20Hz. Measurements for the transistor with tox =7nm. relevant differences are observed with the magnetic field. The lack of a bell-like characteristic suggests that trapping events exists from very low gate voltages. In addition, this transistor has a negligible series access resistance impact on the drain current characteristics at high VG, again with no apparent change by the magnetic field. Remarkably, the wTLP approach shows a deviation in the time signature of the drain current presenting RTN when contrasting the results in the ab- sence and presence of magnetic fields, illustrated in Figure 5.10. A secondary transition occurs, in turn, associated to the presence of a new trap state. This non-monotonic effect only arises at specific magnitudes of the B field (B=-110 and B=+200mT). The insets in Figure 5.10 show the drain current as affected by the newly active trap state. An observation on the axis of Figure 5.10 reveals a shift in the drain current, in agreement with results in section 3.4 (up to 3%). This is consequence of the parametric variation introduced by the re-allocation of carriers in the surface by the magnetic field. This modulation Chapter 5 RTN and noise measurements under magnetic fields 55 of the drain current however does not justify the appearance of the newly ac- tive trap state. Moreover, controversy arises when considering that this trap state, which introduces new trapping events, reflects back at noise measure- ments with no modulation effects, whereas the inverse occurs for the device with tox =14nm, in which an increment of the noise power shows apparently zero new trapping events in the time domain analysis. The opposite effects are analyzed with caution, considering that their respective magneto-modulation effect arises at different biasing conditions. In the transistor with tox =14nm, the applied bias drives the surface into moderate inversion, which may result in confinement related effects in the inversion layer. In the transistor featuring tox =14nm,thebiasdrivesthesurfaceintoweakinversion. These characteristic conditions are the most significant parameters to be analyzed when applying magnetic fields, considering that , in spite of the huge amount of available data, a simple and direct solution has not been found yet, Chapter 5 RTN and noise measurements under magnetic fields 56 (a) B=+200mT (b) B=-200mT 0.9 Id vs time Id vs time 0.1 (c) B=+110mT (d) B=-110mT 0.9 Id vs time Id vs time 0.1 Figure 5.10: The TLP representation of a RTN signal at a)B = 200mT ,b)B = 200mT , c)B = 110mT and d)B = 110mT .Onetransition between two states is evident in b) and c). In a) and d), a second transition is induced, indicating a second trap joins in the trapping phenomena. The color scale indicates the weighted number of events. Inset of plots a) and c) shows the two-level drain current in time domain when a single trap is present, and the inset of plots b) and d) indicate the new trap emergence as a three-level drain current. Chapter 6 Conclusions In recent years, the semiconductor industry has been looking into the mag- netic field effect on the electrical properties of semicondutor devices. The field that takes this opportunity is spintronics, in which the spin state of a charge carrier is controlled by the application of high intensity magnetic fields in a low temperature environment. In spite of the evidence, there is a small com- munity investigating the effect of the magnetic field with lower magnitudes at room temperature, and even a smaller one concerned about the reliability implications. In order to understand one of the most challenging aspects in modern devices, both the magnetic effect and reliability issues, this work has assessed the trapping phenomenology via the analysis of interface and oxide traps using an exhaustive characterization protocol, thoroughly described throughout this thesis. The charge pumping technique allowed to characterize interface states, but beyond the calculus of the trap concentration, the technique becomes a useful tool that provides information on the energy distribution of traps cor- related to the energy in the surface. Considering the re-allocation of charge carriers in the surface as the consequence of the magnetic field, the reported behavior may lead to first evidence on the reduction of trapping events by magneto-modulation effects. 57 Chapter 6 Conclusions 58 Figure 6.1: a) The energy levels in a quantum well at B=0T. b) The energy levels are shifted at B=200 mT. On the contrary, in regard of oxide traps, instead of the possibility of reducing trapping events, the activation of a new trap state became the object of study. The capability of the SSGB method and the wTLP approach to detect slight variations in the characteristics of the RTN, otherwise neglected in several other techniques, is remarkably advantageous in this approach. It saves valuable time in the statistical analysis of RTN that led to the rapid observation of the new active state participating in the trapping dynamics, as well as the noise power that indicated the increment in the trapping events. In addition, the examination of samples fabricated under different technology nodes was useful in the efforts of explaining the magneto-modulation effect. The unexpected behavior under the magnetic fields, yet to be fully ex- plained, highlights the limitations of current investigations in the phenomenol- ogy behind the magneto-deflection effect, especially with magnitudes lower than 1 T at a room temperature. In this context, a parallel investigation has taken place with the aim of attacking this issue through a purely theoretical approach. In the Ph. D. thesis by Adrian Tec [55], the MOS transistor was selected as the numerical device. For the sake of simplicity, the magnetic field was represented as a series of delta functions directly affecting the inversion layer (2DEG layer) in the semiconductor to mimic the experimental conditions. The incorporation of the magnetic field in the Schrödinger equation yields a magnetically induced virtual potential in the inversion layer that disrupts the internal energy of the system. As a result, the parameters that define the Chapter 6 Conclusions 59 transport properties of the structure are modulated by the magnitude of the magnetic field, such as the transmission probability or the confined quantum energy levels (Figure 6.1). Figure 6.1 shows that the magnetic field shifts the energy levels in a quan- tum well from their original positions. The proposed quantum well is an ideal representation of confinement in the surface of the inverse channel. Although atriangularwellisoftensuggestedasamorerealisticrepresentation,theout- come would certainly be the same, the shift of the energy levels by the magnetic field. This is in accordance with the suggested hypothesis in this thesis where the energy bands are shifted as well a result of carrier redistribution, which in turn may modify the interaction between the Fermi-level and the energy levels of traps. Through the implementation of the model in a numerical device, self- consistent simulations offering a qualitative representation to real experimental results become possible in the near future. From the experimental point of view, any future colleague in charge of this investigation may find pending lines to investigate trapping effects: 1. The spin effect is yet to be considered. This may lead to donor-like or acceptor-like states filtering specific carriers with suitable spin orienta- tions. 2. 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