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Presentazione Di Powerpoint Noise measurements on 65 nm CMOS transistors at very high total ionizing dose V. Rea,c, L. Gaionia,c, L. Rattib,c, E. Riceputia,c, M. Manghisonia,c, G. Traversia,c c aUniversità di Bergamo bUniversità di Pavia INFN Sezione di Pavia Dipartimento di Ingegneria e Scienze Applicate Dipartimento di Ingegneria Industriale e dell’Informazione V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 1 Motivation 65 nm CMOS technology is a candidate for mixed-signal readout of high granularity silicon pixel sensors, with potential to meet the requirements of diverse applications such as particle tracking in the innermost layers of ATLAS and CMS at HL-LHC and photon imaging at very high brilliance and high rate light sources Tolerance to extremely high levels of ionizing radiation is a key requirement for both application fields, up to 1 Grad Total Ionizing Dose (TID) during chip lifetime. RD53 collaboration has carried out an extensive study of the behavior under irradiation of a 65 nm CMOS technology, with which a first generation of demonstrator chips is being designed The goal of this paper is to find out if 65 nm CMOS analog front- end circuits can still provide an adequate noise performance even at extremely high total doses. Study of radiation effects on noise can give very important hints about damage mechanisms. V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 2 Test devices and irradiation procedure A test chip was submitted and fabricated with the TSMC 65 nm LP CMOS process, including NMOS and PMOS transistors (standard interdigitated layout) with W in the range 0.12 – 600 µm, L in the range 65 – 700 nm NMOS and PMOS transistors were irradiated with 10-keV X-rays from a 50 kV X-ray machine at INFN Laboratori Nazionali di Legnaro (Italy) and at CERN, with a dose rate of 2 krad(SiO2)/s MOSFETs were biased during irradiation in the worst-case condition, that is, with all terminals grounded, except the gate of the NMOS, which was kept at VDD = + 1.2 V Irradiation and following measurements were performed at room temperature. During the time between irradiation and measurements, the devices were kept at about 0 °C to prevent annealing effects V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 3 65 nm CMOS at extreme radiation levels . At the HL-LHC design luminosity, for an operational lifetime of 10 years, the innermost pixel layer will be exposed to a total ionizing dose of 1 Grad, and to an equivalent fluence of 1-MeV neutrons of 2 x 1016 n/cm2. If unacceptable degradation, a replacement strategy must be applied for inner pixel layers. Nanoscale CMOS (with very thin gate oxide) has a large intrinsic degree of tolerance to ionizing radiation: what happens at 1 Grad? Radiation induced electric charge is associated with thick lateral isolation oxides What is the effect on the noise performance of the transistors? V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 4 Operating region Under reasonable power dissipation constraints, a 65 nm CMOS transistor used as a preamplifier input device will operates in the weak inversion region 100 Operating point for Weak inversion law W/L Strong inversion law =400/0.2 (strips), ID = 40 A W/L =20/0.1 [1/V] 10 D (pixels), /I NMOS 130 nm m I = 4 A g D NMOS 90 nm * 2 NMOS 65 nm IZ 2COX nVT • μ carrier mobility • COX specific gate oxide capacitance 1 • VT thermal voltage 10-9 10-8 10-7 10-6 10-5 10-4 • n proportional to ID(VGS) I L/W [A] subthreshold characteristic D V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 5 Noise in NMOS: CMOS generations from 250 nm to 65 nm 1/f noise has approximately the same magnitude (for a same WLCOX) across different CMOS generations. White noise has also very similar properties (weak/moderate inversion). 100 1/f noise K W/L = 2000/0.45, 250 nm process S2 (f) f ] 1/f W/L = 1000/0.5, 130 nm process f 1/2 COXWLf W/L = 600/0.5, 90 nm process W/L = 600/0.35, 65 nm process • kf 1/f noise parameter • 1/f noise slope-related 10 C = 6 pF αf IN coefficient I = 100 A D Channel thermal noise 2 4kBT • kB Boltzmann’s constant S , • T absolute temperature W g NMOS m • αw excess noise coefficient 1 • γ channel thermal noise Noise Voltage Spectrum [nV/Hz Spectrum Voltage Noise Wn coefficient I 3 4 5 6 7 8 In weak D 10 10 10 10 10 10 gm inversion: Frequency [Hz] nVT V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 6 65 nm LP process: 1/f noise in NMOSFETs The 1/f noise parameter Kf does not show dramatic variations across different CMOS generations and foundries. K S2 (f) f 1/f NMOS COXWLf f f K • kf 1/f noise parameter • α 1/f noise slope-related -24 f 10 coefficient ( 0.85 in NMOS, 1 – 1.1 in PMOS) 10-25 350 nm 250 nm 180 nm 130 nm 90 nm 65 nm Technology Node V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 7 65 nm LP process: 1/f noise in PMOSFETs In the 65 nm LP process, NMOS and PMOS have similar 1/f noise (especially longer transistors), which did not happen in previous CMOS generations This could be explained by a “surface channel” behavior for both devices, and/or by the fact that gate dielectric nitridation decreases the barrier energy experienced by holes across the silicon-dielectric interface. This would make it easier for the PMOS channel to exchange charges with oxide traps. 100 100 ] ] 1/2 1/2 NMOS PMOS NMOS 10 10 PMOS 1 65 nm transistors W/L=600/0.35 1 65 nm transistors W/L=600/0.10 @ ID=50 A, VDS=0.6 V @ ID=50 A, VDS=0.6 V Noise Voltage Spectrum [nV/Hz Spectrum Voltage Noise Noise Voltage Spectrum [nV/Hz Spectrum Voltage Noise 103 104 105 106 107 108 103 104 105 106 107 108 Frequency [Hz] Frequency [Hz] V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 8 Ionizing radiation effects in sub-100 nm CMOS Radiation induced positive charge is removed from thin gate oxides by tunneling (which also prevents the formation of interface states) Isolation oxides remain thick (order of 100 nm) also in nanoscale CMOS, and they are radiation soft. With scaling, the effect of positive charge buildup in STI oxides appears to be mitigated by the higher doping of the silicon bulk. However, the radiation-induced noise degradation may be sizable, especially in NMOSFETs. This is associated to noisy lateral parasitic transistors. At high doses, radiation-induced interface states associated with STI oxides may play an important role: they trap negative charge in the case of NMOSFETs, positive charge in the case of PMOSFETs V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 9 NMOSFETs and lateral leakage In NMOSFETs edge effects due to radiation-induced positive charge in the STI oxide generate sidewall leakage paths. Shaneyfelt et al, “Challenges in Hardening Lateral Technologies using transistors have Shallow-Trench Isolation” IEEE TNS, Dec. 1998 L the same gate length as the main MOSFET NMOS finger Drain Multifinger NMOS n Gate Drain+ STI polyGate 1 2 m Source f n+ Source STI STI Lateral parasitic Main transistor devices finger V. Re – 10th International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 10 Modeling lateral leakage in NMOSFETs Radiation induced positive charge trapped in STI oxides may turn on lateral parasitic transistors. Initially, with increasing dose a larger and larger portion of the STI sidewall gets inverted. The effective gate width, oxide thickness and capacitance are determined by the extension of the inverted regions along sidewalls. At first, only the sidewall bottom is inverted because bulk doping is lower in that region; at increasing TID, the inversion region extends Main transistor towards the surface, involving Drain finger thinner STI oxide regions. Gate At higher doses, negative charge trapped at interface states compensates positive oxide Source charge, and then may even Lateral parasitic th become dominant V. Re devices– 10 International Meeting on Front-End Electronics, Krakow, May 30 – June 3, 2016 11 Total ionizing dose effects on noise in LP 65 nm CMOS V. Re, M. Manghisoni, L. Ratti, V. V. Re, L. Gaioni, M. Manghisoni, L. Speziali, G. Traversi: "Impact of Ratti, G. Traversi: “Mechanisms of lateral isolation oxides on radiation- noise degradation in low power 65 induced noise degradation in CMOS nm CMOS transistors exposed to technologies in the 100-nm regime”, ionizing radiation”, IEEE Trans. IEEE Trans. Nucl. Sci., vol. 54, no. Nucl. Sci., vol. 57, no. 6, 6, December 2007, pp. 2218-2226. December 2010, pp. 3071-3077. Main transistor Equivalent parasitic (gate oxide) transistor (STI oxide) A model (which worked well at 10 Mrad TID) for the contribution of lateral parasitic transistors to the total noise of an irradiated NMOS can be based on the following equations: White noise 1/f noise S2 g 2 æ ö 2 W,post m,main,pre S1/ f ,post Af ,lat gm,lat 2 = »1+ ç ÷ S g + g 2 W ,pre m,main,post m,lat S1/ f ,pre Af è gm ø V.
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