Introduction to very deep submicron CMOS processes: the 65 nm CMOS technology for mixed mode analog-digital circuits

Valerio Re

INFN Università di Bergamo Sezione di Pavia Dipartimento di Ingegneria

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 CMOS scaling and nuclear microelectronics

Industrial microelectronic technologies are today well beyond the 100 nm frontier bringing CMOS into the nanoscale world

65 nm CMOS has attracted a wide interest in view of the design of very compact front-end systems with advanced integrated functionalities, such as required by pixel sensors with low pitch for applications in high energy physics (silicon vertex trackers) and photon science experiments (high resolution imagers)

Digital figures of merit (speed, density, power dissipation) are driving the evolution of CMOS technologies. What about analog performance?

For analog applications in which speed and density are important, scaling can be in principle beneficial, but what about critical performance parameters such as noise, gain, radiation hardness…?

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 2 Advanced pixel detectors and readout microelectronics

Particle tracking at LHC- Phase II:

• Very high hit rates (1-2 GHz/cm2), need of an intelligent pixel-level data processing • Very high radiation levels (1 Grad Total Ionizing Dose, 1016 neutrons/cm2) • Small pixel cells to increase resolution and reduce occupancy (~50x50µm2 or 25x100 µm2)

 Large chips: > 2cm x 2cm, ½ - 1 Billion transistors X-ray imaging at free electron laser facilities:

. Reduction of pixel size (100x100 mm2 or even less), presently limited by the need of complex electronic functions in the pixel cell . Larger memory capacity to store more images (at XFEL, ideally, 2700 frames at 4.5 MHz every 100 ms) . Advanced pixel-level processing (1 – 10000 photons dynamic range, 10-bit ADC, 5 MHz operation)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 3 Microelectronics-oriented collaborative efforts in the high energy physics community: the AIDA project • AIDA WorkPackage3 (ending in January 2015) had the goal of facilitating the access of our community to advanced semiconductor technologies, from nanoscale CMOS to innovative interconnection processes.

• This included 65 nm CMOS for new mixed-signal integrated circuits with high density and high performance readout functions

• Design work was started at various institutions to develop blocks for analog and digital needs in HEP with full documentation and laboratory tests.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 4 RD53: an ATLAS-CMS-LCD collaboration • RD53 was organized to tackle the extreme and diverse challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments (LHC – phase II upgrade of ATLAS and CMS, CLIC)

• It relies fully on significantly improved performance from next generation pixel chips

A 50 µm x 50 µm mixed-signal pixel cell 65 nm CMOS is the candidate readout for the phase II upgrade of LHC in technology to address the 65 nm CMOS requirements of these applications. It has to be fully studied and qualified in view of the design of these chips.

• ATLAS: CERN, Bonn, CPPM, LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico, Prague, RAL, UC Santa Cruz. • CMS: Bari, Bergamo-Pavia, CERN, Fermilab, Padova, Perugia, Pisa, PSI, RAL, Torino. – Collaborators: ~100, ~50% chip designers V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 5

LHC- Phase II pixel challenges

• ATLAS and CMS phase 2 pixel upgrades very challenging – Very high particle rates: 500MHz/cm2 • Hit rates: 1-2 GHz/cm2 (factor ~16 higher than current pixel detectors) – Smaller pixels: ~¼ (~50x50um2 or 25x100um2) • Increased resolution • Improved two track separation (jets) • Outer layers can be larger pixels, using same pixel chip – Participation in first/second level trigger ? (no) A. 40MHz extracted clusters (outer layers) ? B. Region of interest readout for second level trigger ? – Increased readout rates: 100kHz -> ~1MHz • Data rate: 10x trigger X >10x hit rate = >100x ! – Low mass -> Low power Very similar requirements (and uncertainties) for ATLAS & CMS • Unprecedented hostile radiation: 1 Grad, 1016 Neu/cm2 – Hybrid pixel detector with separate readout chip and sensor. • Monolithic seems unfeasible for this very high rate hostile radiation environment – Phase2 pixel will get in 1 year what we now get in 10 years (10.000 x more radiation than space/mil !) • Pixel sensor(s) not yet determined – Planar, 3D, Diamond, HV CMOS, … – Possibility of using different sensors in different layers Complex, high rate and radiation hard pixel chips required V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 6 Analog front-end design for detector charge measurements Radiation detectors

A measure of the information appears in the form of an electric charge, induced on a set of two electrodes, for which ultimately only one parameter (capacitance) is important. Front- end electronics i(t) CD amplifying device (charge-sensitive preamplifier) E Q  i(t)dt filtering, signal shaping S S  optimize the measurement of a desired quantity such as signal amplitude as a measure of the energy loss of the particle, with the best possible accuracy compatible with noise intrinsically present in the amplifying system, and with the constraints set by the different applications (power, speed,…)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 7 Effect of electronic noise on charge measurements

Inherent to the conduction of current in an amplifying device is a random component, depending on the principle of operation of the device.

This random component (noise) associated with amplification gives an uncertainty in the measurement of the charge delivered by the detector or of other parameters such as the position of particle incidence on the detector.

Compromises must be made in very large and complex detector systems such as modern silicon trackers.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 8 Basic element of modern electronics: the MOSFET

• Three-terminal device: an electrode controls the current flow between two electrodes at the end of a conductive channel.

• The transconductance gm = dID/dVGS is the ratio of change in the output (drain) current and of the change in the potential of the

control (gate) electrode

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 9 MOSFET essential parameters: the transconductance gm

Under reasonable 100 Operating power dissipation point for Weak inversion law constraints, devices in W/L Strong inversion law =400/0.2 deep submicron CMOS

(strips), ID operate in the weak = 40 mA inversion region W/L

=20/0.1 [1/V] 10 D

/I In weak inversion:

(pixels), NMOS 130 nm m

I = 4 mA g D NMOS 90 nm ID NMOS 65 nm gm  nVT (n =1.2 in 100-nm scale 1 10-9 10-8 10-7 10-6 10-5 10-4 CMOS) I L/W [A] D

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 10 MOSFET essential parameters: channel thermal noise

Thermal noise arises from random velocity fluctuation of charge carriers due to thermal excitation. The spectral density (noise power per unit frequency bandwidth) is white, i.e. frequency independent. In a resistor, this can be modelled in terms of a fluctuating voltage across the resistor, or of a fluctuating current through the resistor.

R 2 diR 4kT de2  R  4kTR df R df

The channel of a MOSFET can be treated as a variable conductance. Thermal noise is generated by random fluctuations of charge carriers in the channel and can be expressed in terms of the transconductance gm.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 11 MOSFET essential parameters: channel thermal noise

Thermal noise in a MOSFET can be represented by a current generator in parallel to the device, or by a voltage generator in series with the gate (fluctuation of the drain current can be seen as due to fluctuations of the gate voltage).

en 2 2 den 4kT  i din  n  4kT gm df gm df k = Boltzmann’s constant, T = absolute temperature

 = coefficient ( 1) dependent on device operating region, short channel effects…

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 12 CMOS scaling

Digital performances (speed, density, power dissipation) are driving the evolution of CMOS technologies towards a continued shrinking of physical feature sizes.

Analog performance remains essential for the processing of signals delivered by semiconductor detectors.

For a full integration of analog and digital circuits in the most modern semiconductor technologies, design advances are needed to exploit the full potential: digital signal processing may be used to overcome analog limitations, analog circuits may be used to monitor the performance of digital circuits and their power consumption.

nd V. Re – 2 INFIERI International Summer School, Paris, July 16, 2014 13 CMOS scaling: why?

A. Marchioro, INFIERI 2013 • – Gate Source Drain Drain • – W L Poly • n+ n+ • µ P-substrate – SiO Insulator 2 •

W, L = gate width and length

nd V. Re – 2 INFIERI International Summer School, Paris, July 16, 2014 14 26 CMOS scaling: how

Shrinking of gate length leads to an increase in speed and circuit density. To avoid short-channel effects, drain and source depletion regions are made correspondingly smaller by increasing substrate doping concentration and decreasing reverse bias (reduction of the supply voltage)

Increasing substrate doping increases the device threshold voltage: this is overcome by decreasing the gate oxide thickness. Classical scaling ended because of gate oxide thickness limits: in very thin oxides, direct tunneling of carriers leads to a large gate leakageV. Re – 2 ndcurrent. INFIERI International Summer School, Paris, July 16, 2014 15 M. Bohr (Intel), “The new era of scaling in a SoC world”, ISSCC 2009.

How a hs Moore’s elaw be n possible ?

Mechanical stress (compressive or tensile strain) is introduced in the silicon channel to enhance carrier mobility and drive current. Gate dielectric is made thicker (still reducing gate capacitance) by using materials with higher

dielectric constant than SiO2.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 16 Nanoscale

Lewyn et al, “Analog circuit design in nanoscale CMOS technologies, Proc. IEEE, Vol. 97, no. 10, Oct. 2009.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 17 Analog front-end electronics and nanoscale MOSFETs: CMOS 65 nm and the Low Power flavor

After the 250 nm (LHC) and the 130 nm node (LHC upgrades, XFEL,…), our community appears to be very interested in the 65 nm CMOS generation: several prototypes have been already fabricated and tested.

Among the wide choice of options of this technology, the Low Power flavor is less aggressive than other variants (thicker gate oxide, smaller gate current, higher voltage), and is more attractive for mixed-signal chips where analog performance is an essential feature.

65nm LP (Low Power) transistors (VDD = 1.2 V) are optimized for a reduced leakage (different level of gate oxide nitridation with respect to other flavours, different silicon stress,… ).

Wireless and consumer based market rely on the use of LP transistors for mobile devices (low standby power), whereas high speed applications such as microprocessors have used dedicated HP (High Performance) technology.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014

18 Critical parameters for analog front-end design in 65 nm CMOS

This talk will discuss some critical aspects for analog and mixed-signal design in nanoscale CMOS (with focus on LP 65 nm) for detector readout integrated circuits. Among them:

Intrinsic gain Charge carriers in the device channel Thermal noise (short channel effects, strained silicon)

Gate leakage current Interaction of charge carriers with the gate oxide; tools for evaluating 1/f noise the quality of the gate dielectric

Radiation-induced positive charge in the Radiation hardness gate oxide and in lateral isolation oxides

Random components of local process Device matching parameters dependent on device size

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 19 Acquiring the signal from the sensor: the charge-sensitive preamplifier • The detector signal is a current pulse i(t) of short duration • The physical quantity of interest is the deposited energy, so one has to integrate the sensor signal

ES QS  i(t)dt i(t) CD

• The detector capacitance CD is dependent on geometry (e.g. strip length or pixel size), biasing conditions (full or partial depletion), aging (irradiation) • Use an integrating preamplifier (charge-sensitive preamplifier), so that charge sensitivity (“gain”) is independent of sensor parameters

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 20 Acquiring the signal from the sensor: the charge-sensitive preamplifier

Circuit for charge restoration on the feedback capacitor

C F Q/Cf 0 _ This guarantees a return to baseline Q i(t) CD of the preamplifier output, avoiding saturation.

It can be achieved with a resistor RF or, in an integrated circuit, with a CMOS circuit (transconductor). Compensation of detector leakage Output voltage signal voltage Output current can also be performed in the Time preamplifier feedback (dc coupling)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 21 Forward gain stage: basic single transistor amplifier • The forward gain stage is an inverting amplifier. Its most basic version can be in principle based on the common source configuration.

_ G D

g v r R V m GS DS DD S R vout vout  gm rDS // R vin v in -1 rDS  (ID)

rDS  L (device gate length)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 22 Forward gain stage: CMOS version • A higher forward gain can be achieved with a folded cascode configuration. A smaller current in the cascode branch makes it possible to achieve a high output impedance. • An output source follower can be used to reduce capacitive loading on the high impedance node and increase the frequency bandwidth (high gain in a large frequency span)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 23 Intrinsic gain gmrDS • It represents the maximum gain that can be achieved with a single transistor. It gives an indication concerning the design complexity that is necessary to implement a high gain amplifier.

gmrDS µaL • L is the transistor gate length, a is the CMOS process scaling

factor. If Lmin scales by 1/a in agreement with scaling rules, gmrDS stays constant.

• Keeping the intrinsic gain constant with scaling (when you depart from classical scaling rules in advanced technologies) is considered as a major challenge which affects the design of analog circuits in nanoscale CMOS

• But Low Power CMOS processes do not follow aggressive scaling trends closely… V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014

556 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 61, NO. 1, FEBRUARY 2014

Intrinsic gain gmrDS in LP 65 nm CMOS The valueFig .of3. theIntrin sintrinsicic voltage ga igainn is maintainedas a function of t hacrosse gate leng differentth for NMOS CMOS technologyand P nodesMOS de vfromices bia s130ed at nm to Lowand Power 65an dnmbel oifng iinversionng to the Fig. 1. Intrinsic voltage gain as a function of the inversion coefficient LP 65 nm technology ( m, V). for (a) NMOS and (b) PMOS devices with different channel lengconditionsths and are the same. belonging to the LP 65 nm technology ( m, V) .

M. Manghisoni, et al. “Assessment of a Low-Power 65 nm CMOS process Strong for analog front- end design”, IEEE inversio Trans. Nucl. Sci., vol. 61, no. 1, n February 2014, pp. 553-560.

Weak inversio n

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014

Fig. 4. Intrinsic voltage g ain as a function of the gate length for NMOS devices belonging to three technology nodes, and biased at (a) Fig. 2. Intrinsic voltage gain as a function of the gate length for and (b) ( m, V). (a) NMOS and (b) PMOS devices biased at three different values of and belonging to the LP 65 nm technology ( m, V). The impact of scaling on the intrinsic voltage gain has been evaluated in the plots reported in Fig. 4, which show the trend as expected. For longer channel devices, it shows a reduced of this parameter as a function of the gate length, for NMOS de- slope. Once again, this behavior can be ascribed to the dif- vices belonging to three different technology nodes. In Fig. 4(a), ferent effects that cause the non-zero output conductance: short devices are biased at the same inversion level , that is, channel effects, such as the DIBL, dominate on for short at the boundary between the weak and the moderate inversion, channel devices, while CLM mainly influences for devices where the gain is dominated by the DIBL component. As fore- with . For these devices the gain is found to be larger seen by equation (14), if the gate length does not scale, we have for NMOS with respect to PMOS. A direct comparison is re- an improvement in the intrinsic gain. Instead, if scales by the ported in Fig. 3 which shows the intrinsic voltage gain as a func- same factor as the technology node, the intrinsic gain is not de- tion of the channel length for NMOS and PMOS devices biased graded by scaling in agreement with a technology independent at and . For short channel devices NMOS coefficient in (14). The same considerations hold for the and PMOS exhibit almost the same gain in agreement with (14). data shown in the plot of Fig. 4(b), where devices are biased at As a concluding remark, we can observe that the gain is maxi- , that is at the onset of strong inversion. The reduced mized in weak inversion for long channel devices and is mini- slope accounts for the CLM component, which affects the gain mized in strong inversion for short channel devices. It has to be for devices biased in strong inversion. In Fig. 5 the comparison reminded that the intrinsic bandwidth, which is proportional to between the intrinsic voltage gain of NMOS devices belonging , has an opposite behavior [8]. Moreover, the gain is almost to the 65 nm and 130 nm nodes is extended to longer devices. independent of the device polarity for the narrow region where While keeping the intrinsic gain constant with scaling is con- the DIBL effect is dominant, while it is larger for NMOS in the sidered one of the major challenges in the design of High Perfor- conditions where the CLM is dominant. mance (HP) scaled-down technologies [14], negligible degra- Intrinsic gain from 130 nm to LP 65 nm CMOS I L Inversion coefficient I = D C 0 I * W Z

IC0 = 1 is the boundary between weak (IC0 << 1) and strong inversion (IC0 >> 1). For IC0 = 1 , ID = IZ*. IZ* is a characteristic parameter of a CMOS process. It has a similar value of about 0.5 µA in NMOSFETs from the general purpose and the LP 65 nm technology whose parameters are shown in previous plots. When the gate length L is reduced, the transistor stays in the same inversion conditions (equal value of IC0) if the drain current ID is correspondingly increased (at constant W). This means that, for the minimum gate length of the process, the same value of the intrinsic gain (see previous slide) is achieved at the expense of an increased

ID. If this is not allowed because of power dissipation constraints, a value of L larger than the minimum one has to be used. This is an example of the fact that in analog circuits it is often impossible to take full benefit from CMOS scaling in terms of a reduced silicon area.

This is true alsoV. for Re – other2nd INFIERI analog International parameters Summer School, (1/f Paris, noise, July 16, threshold 2014 dispersion,…) Gate current Charge carriers have a nonzero probability gate (larger for electrons with respect to holes) of directly tunneling through a silicon dioxide n+ poly layer with a physical thickness < 2 nm (100- Igso Igc Igdo nm scale CMOS). source drain A reduction of physical oxide thickness of a N+ N+ few Å may give several orders of magnitude P-sub increase in the gate current. This current results in an increase of the static power consumption (manageable limit of gate leakage current density = 1 A/cm2) for digital circuits and might degrade analog performance (shot noise in the gate current, discharge of storing capacitors, current load on global voltage references,…) Gate dielectric nitridation increases the dielectric constant, allowing for films with a larger physical thickness as compared with

SiO2 (COX = eOX/tOX). This mitigates the gate leakage current; however, its value can sizably change in devices from different foundries.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 27 Gate leakage current in nanoscale CMOS flavours and generations Interestingly, the gate leakage current is observed to decrease for the types of stresses adopted by the industry in advanced CMOS (tensile and compressive Gatestress leakage for NMOS current and PMOS, respectively)

These types of stresses increase 102

Theelectron gate current and density hole populationsis used to evaluate in the 2 1 1 A/cm impact of the gate oxide thickness reduction on ] 10 energy bands where they have low 2

the static power consumption m NMOS A c tunneling probability through SiO2 / 0 PMOS A

A 10 [ NMOS B JG is(in the addition IG/WL measured to enhancing at VDS =0their y |V |=1.0PMOS V B

t GS i IG ismobility due to discrete in the chargechannel) randomly crossing a s -1 V =V =0 n 10 DS BS

potential barrier e

D

t -2

We made tests on 130 nm and 90 n 10

e r nm GP (General Purpose) transistors r u -3 C 10

and on 65 nm LP (Low Power) Foundry B

e t

a GP devices transistors (VDD = 1.2 V). These LP -4 G 10 devices were optimized for a Foundry A LP devices reduced leakage (larger equivalent 10-5 oxide thickness, different level of 130 90 65 Technology Node [nm] nitridation with respect to other Oxynitrideflavours, differentgate allows silicon to reduce stress). tunneling effects The gate current V.changes Re – 2nd betweenINFIERI International 90nm processes Summer School, from Paris, two Julydifferent 16, 2014 foundries 28 65nm MOSFETs are in the same region of current density values of 90nm Foundry A and 130nm Foundry B devices This region is well below the commonly used limit of 1 A/cm 2 CMOS scaling beyond 100nm does not necessarily lead to very leaky devices

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 7 Gate current in LP 65 nm CMOS The value of the gate current is maintained across different CMOS technology nodes from 130 nm to 65 nm (Low Power version) 10-4

10-6

10-8 1 A/cm2

[A] G I 10-10 130 nm process

65 nm process 10-12 NMOS W/L = 200/0.70, V = 0 V DS 10-14 0 0.2 0.4 0.6 0.8 1 1.2 V [V] GS

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 Gate current and global design of a CMOS readout chip

Analog VDD In a single transistor in the LP , the gate current has a very small value (of the order of 100 pA/µm2 for the NMOS, 10 pA/µm2 for the PMOS).

However, when bias voltages for analog front-end circuits have to be distributed across a large chip (e.g., a 4 cm2 pixel readout integrated circuit), the total gate leakage current has to be taken into account in the design of reference voltage and current generators (typically, DACs) and current mirrors. Analog ground

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 1/f noise: gate stack fabrication process

Interaction between charge carriers in the gate MOSFET channel and traps close to the Si- oxide SiO2 interface leads to fluctuations in the drain current. This can be modeled with a 1/f term in the spectral density of the noise source drain voltage generator in series with the gate. substrate

The process recipe for the gate stack en (gate electrode and dielectric) may affect the density of oxide traps and their interaction with charge carriers de2 4kT G K in the channel, impacting on the 1/f n = + f noise spectral density. af df gm COXWLf For a physical oxide thickness < 2 nm (same order of the tunnelling distance) the traps at the interface between the gate dielectric and the gate electrode (fully silicided poly gates) can play a major role. 1/f noise may be affected by mechanical stress in the silicon channel (enhancedV. Re – 2nd INFIERI carrier International mobility Summer and School, drive Paris, current). July 16, 2014 31 1/f noise from 350 nm to 65 nm NMOS

The 1/f noise parameter Kf does not show dramatic variations across different CMOS generations and foundries in NMOS.

K S2 (f)  f NMOS 1/f a

COXWLf f

f K • kf 1/f noise parameter

• α 1/f noise slope-related -24 f 10 coefficient ( 0.85 in NMOS,  1 – 1.1 in PMOS)

10-25 350 nm 250 nm 180 nm 130 nm 90 nm 65 nm Technology Node

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 32 1/f noise in PMOS: CMOS generations from 250 nm to 90 nm

1/f noise appears to increase (for a same WLCOX) with CMOS scaling ]

1/2 90 nm Foundry B W/L = 600/0.35 130 nm Foundry A W/L = 1000/0.35 250 nm Foundry C W/L = 2000/0.36 10

C = 5 pF IN

PMOS 1 |V | = 0.6 V DS Noise Voltage Spectrum [nV/Hz Voltage Spectrum Noise I = 500 mA D

103 104 105 106 107 108 Frequency [Hz] V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 33 1/f noise: NMOS vs PMOS

In bulk CMOS, the fact that PMOSFETs feature a smaller 1/f noise with respect to equally sized NMOSFETs was generally related to buried channel conduction.

In deep submicron processes, it was expected that the PMOS would behave as a surface channel device, rather than a buried channel one as in older CMOS generations.

With an inversion layer closer to the oxide interface, 1/f noise is expected to increase. Ultimately, PMOSFETs should feature the same 1/f noise properties as NMOSFETs. However, this was not observed in CMOS generations down to 130 nm and 90 nm.

A possible interpretation can be related to the different interaction of electrons (NMOS) and holes (PMOS) with traps in the gate dielectric (different barrier energies experienced by holes and electrons across the Si/SiO2 interface) .

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 34 NMOS and PMOS in an FD-SOI technology

We previously found that NMOS and PMOS have the same 1/f noise only in one case, that is, in fully-depleted 180 nm CMOS SOI transistors. A possible explanation was that in a very thin silicon film

(40 nm) conduction takes place very close to the Si-SiO2 interface.

100

] NMOS 1/2

PMOS

10

FD-SOI CMOS devices W/L = 100/0.5 I = 50 mA D

Noise Voltage Spectrum [nV/Hz Voltage Spectrum Noise V = 0.6 V DS

1 103 104 105 106 107 Frequency [Hz]

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 35 1/f noise: NMOS vs PMOS

In bulk CMOS processes close to the 100 nm threshold, the PMOS still has a lower 1/f noise than the NMOS. However, this difference tends to decrease with newer CMOS generations.

100 100

] ]

1/2 NMOS 1/2 NMOS PMOS PMOS

10 10 I = 500 mA I = 500 mA D D

1 1 Noise Voltage Spectrum [nV/Hz Voltage Spectrum Noise 180 nm NMOS Foundry A [nV/Hz Voltage Spectrum Noise 90 nm NMOS Foundry B W/L = 2000/0.2 W/L = 600/0.35 103 104 105 106 107 108 103 104 105 106 107 108 Frequency [Hz] Frequency [Hz] 180 nm 90 nm

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 36 65 nm LP process: 1/f noise

In the 65 nm LP process by Foundry B, NMOS and PMOS have similar 1/f noise (especially longer transistors). This could be explained by a “surface channel” behavior for both devices, and/or by the fact that the gate dielectric nitridation decreases the barrier energy experienced by holes across the silicon-dielectric interface. This would make it easier for the PMOS channel to exchange charges with oxide traps.

100 100

]

]

1/2 1/2

NMOS PMOS NMOS 10 10 PMOS

1 65 nm transistors W/L=600/0.35 1 65 nm transistors W/L=600/0.10

@ ID=50 mA, VDS=0.6 V @ ID=50 mA, VDS=0.6 V

Noise [nV/Hz Spectrum Voltage Noise Noise [nV/Hz Spectrum Voltage Noise 103 104 105 106 107 108 103 104 105 106 107 108 Frequency [Hz] Frequency [Hz]

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 37 Thermal noise and CMOS scaling

The origin of thermal noise can be traced to the random thermal motion of carriers in the device channel.

When the MOSFET is biased in saturation (VDS > VDS,sat), the following equation can be used for the power spectral density of thermal noise in all inversion conditions:

2 1 SW  4kBT gm   aWn

• kB = Boltzmann’s constant • γ = channel thermal noise coefficient (depends on inversion region; varies • T = absolute temperature with the inversion layer charge: = gmb 1/2 in weak inversion, = 2/3 in  n 1 strong inversion) gm (n = 1 – 1.5; proportional to the

inverse of the slope of the ID-VGS curve in the subthreshold region) • αw = excess noise coefficient

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 38 Excess thermal noise coefficient

2 1 SW  4kBTn aW gm aW = 1 for long-channel devices. Short-channel devices can be noisier (aW > 1 ) mainly because of two effects related to high longitudinal electric fields (E = VDS/L) in the channel.

m – Reduction of charge carrier mobility: m  0 E at increasing field strength the carrier velocity is 1 saturated at v =m E (m low-field mobility, E sat 0 C 0 C EC critical field strength)

– Increase of charge carrier temperature: b T  E  at increasing field strength the temperature Te e  1  of carriers in the channel increases with respect   T  EC  to the temperature T of the device lattice

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 39 Excess thermal noise coefficient

In saturation, the longitudinal electric field is E = (VGS – VTH)/L. It can be shown that short-channel phenomena affect thermal noise only if the value of the ratio E/EC is not negligible, which does not happen if the device is biased in weak/moderate inversion.

350 nm CMOS

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 40 White noise in 65 nm CMOS Evaluated in terms of the equivalent channel thermal noise resistance:

2 • α excess noise coefficient SW n w R eq   aW • n proportional to ID(VGS) subthreshold characteristic 4k BT gm • γ channel thermal noise coeff.

600 800

Linear f it 700 Linear f it

500 

 off set = 4.75 +/- 7.71 off set = -7.85 +/- 8.92

[ [ slope = 1.09 +/- 0.03 600 slope = 1.04 +/- 0.03 400 500

300 400

300 200

NMOS 200 PMOS

L > 65 nm L > 65 nm E val ent qui N oiR se esi st ance E val ent qui N oiR se esi st ance 100 100

0 0 0 100 200 300 400 500 600 0 100 200 300 400 500 600 700 800 n/g [ n/g [ m m

aw close to unity for NMOS and PMOS with L > 65 nm  no sizeable short channel effects in the considered operating regions (except for 65 nm devices with aw ≈1.3 )

Negligible contributions from parasitic resistances

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 White noise in 65 nm CMOS

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 42 Noise in NMOS: CMOS generations from 250 nm to 65 nm

1/f noise has approximately the same magnitude (for a same WLCOX) across different CMOS generations. White noise has also very similar properties (weak/moderate inversion). 100 1/f noise K W/L = 2000/0.45, 250 nm process S2 (f)  f

] 1/f W/L = 1000/0.5, 130 nm process af 1/2 COXWLf W/L = 600/0.5, W/L = 600/0.35, 65 nm process • kf 1/f noise parameter • 1/f noise slope-related 10 C = 6 pF αf IN coefficient I = 100 mA D Channel thermal noise 2 4kBT • kB Boltzmann’s constant S  , • T absolute temperature W g NMOS m • αw excess noise coefficient 1 • γ channel thermal noise

Noise Voltage Spectrum [nV/Hz Voltage Spectrum Noise   aWn coefficient I 3 4 5 6 7 8 In weak D 10 10 10 10 10 10 gm  inversion: Frequency [Hz] nVT

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 43 Ionizing radiation effects in sub-100 nm CMOS Ionizing radiation generates electron-hole pairs in

SiO2 regions; a fraction of holes is trapped, with a buildup of positive charge. Holes reaching the interface with the silicon bulk may create interface states, which can trap electron or holes depending on the device bias and type

Radiation-induced positive charge is removed from thin gate oxides by tunneling (which also prevents the formation of interface states)

Isolation oxides remain thick (order of 100 nm) also in nanoscale CMOS, and they are radiation soft. With scaling, the effect of positive charge buildup in STI oxides appears to be mitigated by the higher doping of the silicon bulk. However, the radiation-induced noise degradation may be sizable. This is associated to noisy lateral parasitic transistors. The use of enclosed devices (when possible) for low-noise functions may help.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 44 Radiation effects in 65 nm CMOS

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 NMOSFETs and lateral leakage

In NMOSFETs edge effects due to radiation-induced positive charge in the STI oxide generate sidewall leakage paths.

Shaneyfelt et al, “Challenges in Hardening Lateral Technologies using transistors have Shallow-Trench Isolation” IEEE TNS, Dec. 1998 L the same gate length as the main MOSFET

NMOS finger Drain Multifinger NMOS

n Gate Drain+ polyGate Source n+ Source STI Lateral parasitic Main transistor devices finger

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 46 130nm and 65 nm core transistors in the 10 Mrad TID region

Radiation effects on ID vs VGS curves are considerably larger in 130 nm devices than in LP 65 nm transistors. This could be explained by a higher doping concentration in the p-type body for the 65 nm process, which mitigates the inversion of the surface along the STI sidewalls.

Doping of P and N-wells increases with CMOS scaling, to keep drain/source depletion regions small with respect to gate length. More scaled CMOS technologies appear to be less sensitive to lateral leakage effects associated to the STI oxides at a 10 Mrad TID. Enclosed devices may not be strictly required in rad-hard systems.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 47 Radiation effects on noise LP 65 nm technology – 10 Mrad

Moderate 1/f noise increase at low current density, due to the contribution of lateral parasitic devices At higher currents the degradation is almost negligible because the impact of the parasitic lateral devices on the overall drain current is much smaller No increase in the white noise region is detected

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 Radiation effects on noise 65 nm vs 130 nm technology – 10 Mrad

100 Parasitic sidewall transistors, 65 nm NMOS W/L=1000/0.13

besides affecting static ] and 130 nm NMOS W/L=1000/0.35 characteristics, are also noisy. 1/2 Id=100 mA @ Vds=0.6 V After irradiation, noise from the lateral parasitic transistors affects the overall noise voltage spectrum 10 when sidewall leakage current has a larger effect, that is, at small values of ID. 65 nm, before irradiation 65 nm, 10 Mrad An increase in the 1/f noise term is Noise Voltage Spectrum [nV/Hz 130 nm, before irradiation detected, dependent on the impact 130 nm, 10 Mrad 1 of these lateral transistors on the 103 104 105 106 107 overall device characteristics. Frequency [Hz] For 130 nm and 65 nm transistors, noise voltage spectra in the low frequency region are very similar before irradiation (similar gate capacitance)

A 1/f noise increase is clearly detectable for the 130 nm device at low current density,V. Re –whereas 2nd INFIERI for International the 65 Summer nm one School, the Paris, noise July degradation 16, 2014 is smaller 65nm transistors at extreme total ionizing dose: the PMOS

M. Barbero, G. Deptuch, FEE2014 workshop, Argonne Nat. Lab

• Among other effects, PMOSFETs (especially minimum size ones) show a large transconductance degradation, which becomes very steep at TID > 100 Mrad (partial recover after annealing) • Damage mechanisms at 1 Grad (LHC phase II upgrade, innermost pixel layer) have yet to be fully understood (including dependence on geometry and bias conditions under irradiation and annealing, dose rate, temperature, radiation source…) V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 Extracting a hit information from the sensor signal: the discriminator • Binary readout: hit/no hit information from a discriminator • This can also be associated to an ADC system, providing an information about the charge delivered by the detector PREAMPLIFIER CF SHAPER DISCRIMINATOR

Q . d CD Vth

Vth

• In a multichannel readout chip, channel-to-channel threshold variations due to device mismatch may degrade detection efficiency and spurious hit rate

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 51 Efficiency and noise occupancy

• An excessive threshold dispersion can lead to channels with high noise hit rate or reduced efficiency in signal detection.

Most probable value Noise depends on: gaussian Discriminator threshold distribution Landau detector thickness distribution (80 e-h pairs/mm (s = ENC) of detector for 300 mm charge for thickness) a M.I.P. charge collection efficiency Count rate Count (degraded in irradiated silicon)

Detector charge

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 52 Threshold dispersion

• Discriminator threshold dispersion is given by statistical variations of the threshold voltage of MOSFETs in the differential pairs used in the discriminator input stage: A2 s2V   vth A ¸t th WL vth OX + V (from stochastic dopant DD = fluctuations model)

Large area transistors M3 M4 help reduce the effect vOUT of threshold mismatch

vth

M1 M2 To maintain an adequate efficiency, a vin channel-by-channel threshold I adjustment is often necessary (threshold DAC in a pixel readout cell)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 53 Threshold dispersion in nanoscale CMOS Small feature size and low supply voltage increase the impact of variation of transistor properties on chip performance.

While Avth has the expected reduction with tox scaling until about 90 nm technologies, in more recent technology generations it has not been decreasing. This could be due to the reduction in tox scaling, the increase in channel doping required to reduce short channel effects, and the contribution of additional process steps.

S. Saxena: “Variation in transistor performance and leakage in nanometer-scale technologies”, IEEE Trans. El. Dev, vol. 55, no. 1, January 2008, pp. 131-144.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 54 Digital calibration of the discriminatorThreshold dthresholdispersion and No ise

120 Nonidealities of nanoscale CMOS 100 Before corr. ⇥ 5.45 mV⇥ transistors may be addressed by After corr. ⇥ 0.49 mV⇥

appropriate desing techniques. This 80 s includes the digital calibration of analog t

n 60 u

circuits. In an analog front-end channel, o C the discriminator threshold may be finely 40 adjusted by a local digital-to-analog 20 converter (DAC). 0.290 0.295 0.300 0.305 0.310 Threshold V⇥

Threshold dispersion b65efor enm cor rcontinuousection ! 380 e--time analog Threshold dispersion affrontter cor-rendection channel (ideal case) for ! 3 5HL e- -LHC

- Noise ! 115 e @ CD=100pixels fF

RD53 Analog Design WG Vidyo meeting, June 30 2014 8 of 9 Threshold dispersion: Before correction 380 e rms Lodovico After DAC correction 35 e rms Ratti, RD53 Analog WG V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 55 meeting System aspects of mixed-signal design of large chips in 65 nm CMOS

The local adjustment of the threshold in a pixel cell is an example of design strategies that can be adopted to overcome limitations associated with small area devices. Generally speaking, the design of a complex microelectronic system such as a 65 nm pixel readout chip has to devise solutions that allow analog and digital circuits to work together in a same substrate, complying with low noise and low power dissipation requirements (among others)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 56 Digital-to-analog interferences • There are many ways by which interferences can propagate through the chip substrate…

• These effects can be mitigated by using differential, low-level digital signals (LVDS), by isolation techniques, by layout tricks (separated analog and digital power and signal routing) … I. A. Young (Intel), “Analog mixed –signal circuits in advanced nanoscale CMOS technologies for microprocessors and SoC”, 2010 ESSCIRC

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 57 Integration of the analog readout cell in a (mostly digital) pixel matrix • In a 50x50 µm2 pixel cell, a correct layout is crucial to avoid digital interferences in the low-noise analog front-end

GNDD GNDD VDDD

VDDA VDDA GNDA

Quiet configuration logic

Abder Mekkaoui, RD53 Analog WG meeting

V. Re – 2nd INFIERI International Summer School,Quietconfiguration logic Paris, July 16, 2014 58 Clock distribution across a large 65 nm chip Clock distribution is a crucial aspect of modern multi-GHz microprocessor design. A single clock source is fed through hierarchies of clock buffers to eventually drive almost the entire chip.

Increasing process and device variations in deep sub-micron semiconductor technologies further adds to timing uncertainties known as clock skews.

The load of the entire chip is substantial, and sending a high quality clock signal to every corner of the chip can be very expensive in terms of power dissipation. This could be seen as a typical “mixed-signal” problem, that can be tackled by distributing an “analog-like” signal (aka a reduced swing digital signal) that is then regenerated close to the pixel readout cells.

Transmitter (TX) Receiver (RX)

Ebit = CVDDVswing

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 59 A backup solution

WeRow would n edistributioned a “backup solution” if schemethe VDDL supp lyof is n ota b ereduced available swing TX: The M3 nMOS transistor is inserted between the pMOS and nMOS trclockansistors o fsignal a simple in veinrte ra to pixelthe decre areadoutse the output vo lmatrixtage swing Reduced swing Applying VDD to its gate, the voltage on its source, and therefore on the clock transmitter output node of the driver, can not exceed the voltage value VDD – Vth3, (requires an Row distribution sche whermee Vth3 is the threshold voltage of M3 transistor In the simulated circuits -> Output Swing (Vout) ≈ 700 mV asymmetric RX: We used, as the receiver, an asymmetric inverter involving a LVT nMOS inverter in the and a HVT pMOS receiver to We evaluated the skew between the so called “First regenerate nominal Pixel” and the “Last Pixel” Backup solution: Simulation resdigitalults voltage We studied the skew as a levels) function of the width W of the vertical M9 line distributing the clock signal Total Power Consumption has In Out been simulated as well, taking into account power of pixel RX, row TX, intermediate Repeater and the Peripheral Clk 9 buffer

nd V. Re – 2 INFIERI International Summer3 School, Paris, July 16, 2014 60

Skew @ rising Skew @ falling Average Skew Total Power PSP edge [ps] edge [ps] [ps] Consumption [mW] 0.8V Solution 632 660 646 2.34 1512 1.2V Solution 435 447 441 5.41 2386 Backup Solution 489 636 562 4.34 2441 10 Conclusions

Nanoscale MOSFETs have very interesting new features in terms of device processing and physics.

At the 65 nm node, low-noise design of analog circuits in mixed- signal detector readout chips is challenging but, according to the study of key analog parameters, appears to be still viable in the Low Power technology flavor.

Microelectronic technology will drive the evolution of particle detection systems as it has done in the last decades

Classical analog problems (signal amplification and filtering, noise optimization, minimization of threshold dispersion) require clever solutions Technology watch for novel devices and processes has to continue, since the evolution of microelectronics is not going to end soon.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 61 Backup slides

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 62 Radiation effects in lateral isolation structures

In an interdigitated device, the lateral leakage can be modeled considering that two parasitic transistors for each finger are turned on

Main transistor finger Drain Gate

Source Lateral parasitic devices

The two lateral parasitic transistors have an effective gate width Wlat,finger, the same gate length L as the main device and gate oxide capacitance COX,lat inversely proportional to an effective oxide thickness tOX,lat The parasitic devices add a contribution to the total drain current and noise of NMOSFETs

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 Evolution of scaling Alternate gate dielectrics With a high dielectric constant (high-k) material, a much thicker gate dielectric can

be used, with the equivalent capacitance of much thinner SiO2-based structures (in ≤ 45 nm CMOS). Thicker dielectrics are more sensitive to ionizing radiation; as always, actual behavior will depend on process details. Hafnium-based dielectrics with good radiation tolerance have been reported New MOSFET Structures Advanced multiple-gate devices “3D” gate structures have been devised as a way to avoid short-channel effects in aggressively scaled MOSFETs (≤ 22 nm). Control of lateral gates on silicon channel may be beneficial in terms of radiation tolerance (no lateral leakage). However, radiation effects in these advanced devices may be more complex than in bulk MOS Carbon-based electronics (Beyond CMOS) Cylindrical FET Carbon nanotubes and graphene have generated much interest: not yet clear if they will be a replacement for Si CMOS. Because of their extremely low volumes (few atomic layers), their radiation response may mostly depend on interfaces and surrounding materials.V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 Ultra Thin Body SOI

4 Chenming Hu, July 2011 Channel thermal noise coefficient in various inversion regions

0.8

In weak strong inversion: 0.7 inversion the “classical” ID value of 2/3 gm  0.6 nVT  (n = 1 - 1.5 in 1/2, 0.5 100-nm scale see BJT weak inversion CMOS, n=1 in 0.4 bipolar transistors) 0.3 0.1 1 10 100

Inversion coefficient 2 4kT 2 1 VT SW  n  n 4kT gm 2 ID

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 65 Transconductance and Channel thermal noise coefficient

Transconductance in all inversion regions (*)

ID 2 IDL gm  , u  * nV T 1 4u 1 IzW

Channel thermal noise coefficient (*)

1 1 2  I L    u , u  D   * 1u 2 3  IzW

(*) G. De Geronimo, P. O'Connor, "MOSFET optimization in deep submicron technology for charge amplifiers ", IEEE Trans. Nucl. Sci., vol. 52, n. 6, Dec. 2006.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 NMOSFETs and lateral leakage Ionizing radiation leads to a large negative threshold shift of the equivalent parasitic transistor associated to the thick STI oxide

-2 10 Total ID LateralLateral after parasiticparasitic irradiation transistortransistor -4 10 after

irradiation

[A]

-6

D I 10 NMOS 130 nm process W=1000 m m 10 -8 L=0.2 m m ID before V =0.6 V irradiation DS 10 -10 0 0.5 1 V [V] GS V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 67 65 nm NMOS: white noise

100 100 1/f Slope (a =1) f ID=20 mA

] 1/f Slope (af=1)

ID=50 mA ]

1/2 1/2 ID=100 mA

ID=250 mA 10 ID=500 mA 10

1 1 I =20 mA NMOS W/L=1000/0.13 D NMOS W/L = 600/0.20 I =50 mA @ V =0.6 V D

@ VDS=0.6 V DS Noise Voltage Spectrum [nV/Hz Voltage Spectrum Noise Noise Voltage Spectrum [nV/Hz Voltage Spectrum Noise ID=100 mA

ID=250 mA 0.1 0.1 3 4 5 6 7 8 10 10 10 10 10 10 103 104 105 106 107 108 Frequency [Hz] Frequency [Hz]

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 68 65 nm process options CMOS 65 nm variants

Several variants of the 65nm process technology are available

High Speed: highest possible speed at the price o f v e r y h i g h l e a k a g e c u r r e n t ( f o r microprocessors, fast DSP, …). Lower operation voltage (Vdd=1V), low threshold voltage devices General Purpose: speed is not critical -> leakage current one order of magnitude lower than HS

Low Power (or Low Leakage): thicker gate oxide Low Moderate Fast thickness, Vdd=1.2V, higher threshold voltage (-50%) (0%) (+50%) devices (for low power applications)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 69

The characterization results of the 65nm technology shown in this talk are referred to a Low Power option (compared with 90nm LP, 90nm GP and 130nm GP from different foundries)

“SEE and TID. Radiation Test Results on ST Circuits in 65nm CMOS Technologies ”, Final Presentation of ESTEC Contract 2006-2007. No. 18799/04/NL/AG, COO-3. January 2009

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 3 Gate-leakage current noise

Noise in the gate current of a MOSFET shows white and 1/f components and can be represented through an equivalent parallel noise current source at the gate

] NMOS W/L = 600/0.60 1/2 @ Vgs=0.67 V, Vds=1.00 V, Ig=1.36 mA 2 2 2 10 SP(f)  SW S1/f (f) D G

1 2

SP Noise Current Spectrum [pA / Hz/ [pA Spectrum NoiseCurrent 0.1 S 100 101 102 103 104 105 Frequency [Hz] Gate-leakage current is the sum of three contribution  to evaluate the effect on the overall noise of single contributions, noise measurements have been performed in two bias conditions: @ Vds=0 and @ Vgs=0

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 Ionizing radiation effects on MOSFET 1/f noise

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 71 Noise spectra at minimum channel length in various CMOS generations

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 72 Charge measuring system and the effect of noise Filter minimizes the measurement error with respect to noise and the C F effect of pulse overlap e (finite duration) N Filter T(s) Shaper . i Q d CD N Ci

Vmax Q Ionization detectors Charge collection is can be modeled as tP very fast in capacitive signal semiconductor sources detectors

Noise arises from two uncorrelated sources at the input (series and parallel noise): A Bf    f S   B  Se   A I N W N W f f

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 73 Noise sources White series noise White parallel noise  White noise in the main current AW  4kT (drain, collector) of the input 4kT gm B  2qI  2qI  device W det G(B) R other components in the input stage Shot noise in detector leakage current stray resistances in series with the input shot noise in input device gate 1/f series noise (base) current thermal noise in feedback resistor Af A1/ f  1/f component in Parallel noise sources f the drain current Current generators at the Series noise sources preamplifier input Voltage generators at the preamplifier input

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 74 Equivalent Noise Charge (ENC)

2 2 A1 2 ENC  AWCT  Af CT A2  BW A3tP tP

White series noise: Neglecting noise in parasitic resistors: White parallel noise:  B  2qI A  4kT W W g m I = IB (BJT)  = 0.5 (BJT) I = IG (gate tunneling current  = 2/3 (Long channel FETs) in nanoscale CMOS)

  1 (Short-channel FETs) I = Ileak Detector leakage current

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 75 Equivalent Noise Charge (ENC)

2 2 A1 2 ENC  AWCT  Af CT A2  BW A3tP tP

Series 1/f noise (MOSFET): 1/f noise parameter; depends on the gate oxide Kf quality Af  Oxide capacitance C WL Transistor geometry per unit gate area OX (gate Width and Length)

The ENC contribution from 1/f noise is independent of the peaking time of the signal at the shaper output; it is weakly dependent on the shape of the transfer function of the shaper.

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 76 Ionizing radiation effects on signal-to-noise ratio: pixel readout with 65 nm electronics standard input NMOS – 10 Mrad

100

]

-

e

[

C N

E before irradiation 10 Mrad

NMOS W/L=27/0.2 C = 300 fF @ P = 5 µW D D 10 10-8 10-7 Peaking time [s]

An estimate based on measured noise parameters shows that 1/f noise degradation increases ENC by about 10% in the 25 – 50 ns peaking time region for the LP 65nm process

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 • As for the noise, the discriminator threshold and its dispersion (divided by the analog channel charge sensitivity) can be treated

in term of input-referred charges, Qth and sqth respectively.

• For a second-order semigaussian shaper, and series white noise as the dominant contribution to ENC, the frequency of noise hits can be calculated as: Q2  th 3 2ENC2 fn  e tP • In practical conditions, the number of noise hits can be kept at acceptably low values by satisfying this condition:

sig Q  4ENCs th  qth • To maintain an adequate efficiency, a channel-by-channel threshold adjustment may be necessary (threshold DAC in the pixel cell)

V. Re – 2nd INFIERI International Summer School, Paris, July 16, 2014 78