Qubit Control-Pulse Circuits in SOS-CMOS Technology for a Si:P Quantum Computer

Qubit control-pulse circuits in SOS-CMOS technology for a Si:P quantum computer

Author : S. Ramesh Ekanayake 1, 2 Degree : Doctor of Philosophy (Ph.D.) Supervisors : Dr Torsten Lehmann 1, 2 Co-supervisor : Prof. Andrew S. Dzurak 1, 2 Submitted : 31 Jul, 2008

1 Australian Research Council Center of Excellence for Quantum Computer Technology 2 School of Electrical Engineering and Telecommunications

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THE UNIVERSITY OF NEW SOUTH WALES Thesis/Dissertation Sheet

Surname or Family name: EKANAYAKE

First name: SOBHATH Other name/s: RAMESH

Abbreviation for degree as given in the University calendar: Ph.D.

School: Electrical Engineering and Telecommunications Faculty: Engineering

Title: Qubit control-pulse circuits in SOS-CMOS technology for a Si:P quantum computer

Abstract 350 words maximum: (PLEASE TYPE)

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non- adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full-custom mixed-mode and full- digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process – a radio-frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators.

The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 ps rise- times at 300 K, 4.2 K, and sub-K with a power dissipation of 12 µW at 100 MHz. The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking.

This research has demonstrated that SOS-CMOS technology is highly feasible for the fabrication of control microelectronics for a Si:P-based QC. I have demonstrated full-custom SOS-CMOS mixed-mode and full-digital control circuits at 300 K, 4.2 K, and sub-K which suitable for qubit control.

Declaration relating to disposition of project thesis/dissertation

I hereby grant to the University of New South Wales or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University libraries in all forms of media, now or here after known, subject to the provisions of the Copyright Act 1968. I retain all property rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.

I also authorise University Microfilms to use the 350 word abstract of my thesis in Dissertation Abstracts International (this is applicable to doctoral theses only).

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I hereby grant the University of New South Wales or its agents the right to archive and to make available my thesis or dissertation in whole or part in the University libraries in all forms of media, now or here after known, subject to the provisions of the Copyright Act 1968. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.

I also authorise University Microfilms to use the 350 word abstract of my thesis in Dissertation Abstract International (this is applicable to doctoral theses only). I have either used no substantial portions of copyright material in my thesis or I have obtained permission to use copyright material; where permission has not been granted I have applied/will apply for a partial restriction of the digital copy of my thesis or dissertation.

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Date ……………………………………………...... Preface

Preface

This thesis was inspired by my research interests since 2000 in exploring the fundamental science and engineering behind quantum and nanoelectronic devices, complimentary metal-oxide-semiconductor (CMOS) microelectronic integrated circuits (ICs), and their interconnection and integration. I approached my supervisors Dr Torsten Lehmann and Prof. Andrew Dzurak in the, now, Australian Research Council’s Center of Excellence for Quantum Computer Technology (CQCT) in 2004 with the vision of embarking on a journey of research that would take the first steps toward exploring my ideas. The work that ensued in this thesis has its concentration on the design, fabrication, and prototyping of full-custom CMOS-based qubit control-pulse generator (controller) circuits for operation at cryogenic temperatures for the center’s tentative Si:P-based qubits in a solid-state Si-based quantum computer (QC).

Chapter 1 presents a literature review of current work on solid-state qubit control and readout circuit design, focusing on the former, towards the development of solid-state controller-qubit-observer (CQO) circuits and interfaces. This includes a brief introduction to qubits, and why we need the control mechanisms discussed in this work. The discussion, then, follows on to present some background and related work. Following this, I systematically present the motivations of this work by introducing a foundry fabricated silicon- on-insulator (SOI) technology that was selected due to the merits it offers for high-speed controller design: the Peregrine Semiconductor Corporation’s (PSC) ultra-thin-silicon (UTSiTM), alternatively, UltraCMOSTM) silicon-on-sapphire complimentary-metal-oxide-semiconductor (SOS-CMOS) 500 nm and 250 nm processes.

i Preface

Chapter 2 presents a detailed discussion on characterizing active and passive devices from both PSC 500 nm and 250 nm SOS-CMOS processes and presents device operation and measurement results at 300 K (room temperature), 4.2 K (liquid helium temperature), and sub-K (3He-4He dilution temperatures). Herein, sub-K refers to the range 30 mK base temperature to about 1000 mK unless stated otherwise.

Chapter 3 presents the design and prototyping of a first generation control circuit in the 500 nm SOS-CMOS process. This design is based on a mixed- mode circuit design thus the objective is to shed light on this previously untried approach to qubit control using CMOS technology at low temperatures (sub-K and 1–4.2 K) and low-power dissipation levels (≤ 100 µW). Hence its complexity and device counts are minimized to maximize the probability of the circuit operating at sub-K and allow for the least possible power dissipation.

Chapter 4 presents the design and prototyping a second generation control circuit in the 500 nm SOS-CMOS process. This design is based on a full-digital circuit design thus the objective is to explore the use of a sophisticated and complicated control circuit at sub-K temperatures.

Chapter 5 is the conclusion encapsulating this body of work.

This thesis is dedicated to all humanity and its evolutionary gift for abstract thought and ingenuity that enables it to bring to “reality” what was once an “impossibility”. May we continue this trend well into a prosperous future as a species in sustenance and harmony with nature!

ii Abstract

Abstract

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated full- custom mixed-mode and full-digital fast control-pulse generators fabricated in a silicon-on-sapphire (SOS) CMOS commercial foundry process – a radio- frequency (RF) CMOS technology. These circuits are, fundamentally, fast monostable multivibrators.

The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 ps rise-times at 300 K, 4.2 K, and sub-K with a power dissipation of 12 µW at 100 MHz. The full- digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times settable via a control-word streamed synchronously to a shift-register. The design was based on a ripple-counter with provisions for internal or external clocking. iii Abstract

Listed below are the patents, publications, and awards that resulted from this research during 2004-2008. These are cited in the references section and some are attached in paper form in Appendix C, of this thesis:

Patents [1] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, and R. G. Clark, "Interfacing at Low Temperature using CMOS technology," US/AU Patent RP28, 2007.

Publications [1] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, and R. G. Clark, "Quantum bit controller and observer circuits in SOS-CMOS technology for gigahertz low- temperature operation," presented at the 7th IEEE International Conference on Nanotechnology (IEEE-NANO 2007), Wan Chai, Hong Kong, 02-05 Aug, 2007.

[2] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, R. G. Clark, and A. Brawley, "Characterization of SOI RF-CMOS FETs at ultra-low temperatures for the design of integrated circuits for quantum bit control and readout," IEEE Trans. Electron Devices, submitted, 2007.

[3] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, and R. G. Clark, "Single-shot qubit control electronics for sub-Kelvin operation," presented at the SPIE Microelectronics, MEMS, and Nanotechnology 2007, Canberra, ACT, Australia, 05-07 Dec, 2007.

iv Abstract

[4] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, and R. G. Clark, "Qubit control- pulse generator circuits for operation at cryogenic temperatures," presented at the 8th IEEE International Conference on Nanotechnology (IEEE-NANO 2008), Arlington, TX, USA, 18-21 Aug, 2008.

[5] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, and R. G. Clark, "Microelectronic circuits for solid-state quantum bit control," in preparation.

Awards and Prizes [1] First prize in the prestigious “Faculty of Engineering Dean’s Prize for Postgraduate Research Excellence 2006 ($3000)”. I was among the short- listed 50 research students (from an initial selection of 250) from all schools within the faculty. This award symbolizes the significance and uniqueness of my work presented in this thesis.

[2] Faculty of Engineering Postgraduate Research Support Scheme (PRSS) Conference Travel Grant ($1500), 2007.

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Declaration of originality

I hereby declare that this submission is my own work and to the best of my knowledge it contains no materials previously published or written by another person, or substantial proportions of material which have been accepted for the award of any other degree or diploma at UNSW or any other educational institution, except where due acknowledgement is made in the thesis. Any contribution made to the research by others, with whom I have worked at UNSW or elsewhere, is explicitly acknowledged in the thesis. I also declare that the intellectual contentIntentionally of this thesis is the productleft void of my own work, except to the extent that assistance from others in the project's design and conception or in style, presentation and linguistic expression is acknowledged.

Signed: ......

S. Ramesh Ekanayake

Date: ......

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viii Acknowledgements

Acknowledgements

I acknowledge the valuable contributions and supervision of Dr Torsten Lehmann, Prof. Andrew Dzurak, Prof. Bob Clark during this thesis. I also like to thank Dr Eric Gauja for his undivided availability and attention to train me and supervise me with my microfabrication work in the Silicon Nanofabrication Facility (SNF) microlab, Dr Fay Hudson for nanofabrication work performed in the SNF nanolab, Bob Starrett and David Barber for their invaluable insight, friendly assistance and advise with measurements performed in the National Magnet Lab (NML).

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x List of figures

List of figures

Fig. 1.1 The energy-time diagram of a charge qubit showing fast rise-time control-pulse based non-adiabatic control [15]...... 3 Fig. 1.2 (a) The overall quantum-classical control system showing where the classical CMOS may be positioned and what interfaces could be connected to the quantum processor. (b)required inputs and outputs of the control- pulse generator chip from loosely set guidelines as design requirements. Some or all of the shown inputs may be used in a design...... 16 Fig. 2.1 (a) The Kelvinox K-100 dilution refrigerator, warmed to 300 K with sample loaded. (b) the DSO8104A lower bandwidth digital-storage oscilloscope (DSO), Stanford Research Systems SR830 DSP Lock-In Amplifier and SIM-controller, Tektronix AFG320 Function Generator, (c) the Agilent 86100B DCA wide-band oscilloscope (WBO), and (d) the Anritsu MP1763C Pulse Pattern Generator...... 20 Fig. 2.2 The design methodology I used in my custom IC design approach. ....21 Fig. 2.3 (a) Experimental setup for direct current (DC) measurement and characterization of SOS-CMOS NFET, PFET devices from the PSC 500 nm and 250 nm, and n+-diffusion resistor from the PSC 500 nm process. (b) The LCC20 package onto which the test chips were Al wire- bonded...... 23

Fig. 2.4 The DC response ID(VGS) characteristics at (a) 300 K, (c) 4.2 K, (e) sub-

K, and ID(VDS) characteristics at (b) 300 K, (d) 4.2 K, (f) sub-K of the PSC 10/0.4 NFET devices shown for positive voltages, and 10/0.4 PFET devices shown for negative voltages on the voltage axes. All devices are from the

PSC 500 nm SOS-CMOS process. The VGS and VDS voltages are in steps of 0.2 V for 300 K and 4.2 K results, and in steps of 0.1 V for sub-K results...... 25 xi List of figures

Fig. 2.5 The DC response ID(VGS) characteristics at (a) 300 K, (c) 4.2 K, (e) sub-

K, and ID(VDS) characteristics at (b) 300 K, (d) 4.2 K, (f) sub-K of the PSC 10/0.25 NFET devices shown for positive voltages, and 10/0.25 PFET devices shown for negative voltages on the voltage axes. All devices are

from the PSC 250 nm process. The VGS and VDS voltages are in steps of 0.2 V for 300 K and 4.2 K results, and in steps of 0.1 V for sub-K results. 26 Fig. 2.6 (a) Experimental setup for rise-time measurement and characterization of PSC 500 nm PFET. Only a PFET was measured due to limited time to MPR cut-off and based on the reasoning that a NFET would have a similar or faster rise-time. (b) The RF-PCB enclosure onto which the PFET-chip (the thin strip visible at the translucent center) was Al-wire-bonded...... 28 Fig. 2.7 Extrapolated switching behavior and rise-time at (a) 300 K, and (b) 4.2 K, of the PSC 500 nm PFET wire-bonded to RF-PCB enclosure as shown in setup of Fig. 2.6...... 29 Fig. 2.8 DC response of 50/10 n+-diffusion resistor from 500 nm process at 300 K and 4.2 K. This reveals that the resistor retains its Ohmic characteristics thus is useful for low-temperature circuit design...... 31 Fig. 2.9 Differential-amplifier (DA) fabricate in the PSC 500 nm process during the second MPR...... 32 Fig. 2.10 Differential-pair test showing shift in I(V) characteristics as the chip is cooled from 300 K to 4.2 K. This is suggestive of mismatches in the transistors that may affect switching behavior at low-temperatures. This differential-pair was fabricated in the PSC 500 nm process...... 33 Fig. 2.11 The electric field in a (a) MOSFET without LDD structures may be high enough to generate hot-carriers that can cause impact ionization and avalanche breakdown in the oxide or hot-carrier induced punch-through (HCIP) in the substrate. The same MOSFET (b) with LDD structures increases the distance over which the electric field can distribute thus reducing the probability of hot-carrier generation. Note, in the figures, the size of the arrowheads represents the electric field strength, while the arrowhead density (electric field intensity) is constant, as should be...... 34 Fig. 3.1 Conceptual schematic diagram of first generation mixed-mode control- pulse generator...... 38

xii List of figures

Fig. 3.2 Timing diagram showing NAND-gate based pulse generation. A slow rising trigger pulse with noisy edge-transitions can be cleaned with a Schmitt-trigger the output of which is a pulse with fast and crisp edge- transitions. This can then be input into the pulse generation circuit as shown to produce the control-pulse...... 39 Fig. 3.3 The schematic design capture for layout generation. The ESD pad protection (ESDP) cells are also shown in the schematic. These are ESD- clamps with minimal protection...... 41 Fig. 3.4 Photomicrograph of first generation control-pulse generator. Die area is 3 mm x 3 mm. The large fin-like structures are the decoupling capacitors (a Vm2 and Vm1 combined equivalent capacitance of 121.87 pF). Four versions of the same circuit were included and connected to the pad on the right: version 1 (connected to pad 2) has a 20 µm output NFET switch with a 50 Ω triple-microstrip transmission line, version 2 (connected to pad 5) is the same circuit without a transmission line, version 3 (connected to 7) has a 200 µm output NFET switch without a transmission line, version 4 (connected to 10) is the same circuit with a 50 Ω triple-microstrip transmission line. As visible, only ESD-clamps are present at the input and no ESD structures are present at the output. The structure at the top– center is a ring oscillator test structure with 501 stages. The test structures at the bottom-center looking clockwise from top-left are an inverter, the differential-pair in Fig. 2.9, the current-starved inverter structures for individual testing, and individual NFET and PFET devices...... 42 Fig. 3.5 Simulation results of the first generation control-pulse generator. The dwell-time setting voltage Vtdwell = 1.1 V in this simulation...... 43 Fig. 3.6 (a) A model of the measurement setup for triggering and observing the control-pulse on a DSO/WBO with long coaxial cables (transmission lines), D-connectors, line wires, and bond wires manifesting significant delays for charge to be supplied on-demand at the controller chip solely by external power-supplies. This shows the significance of and undisputed need for internal and external decoupling capacitors positioned as close as possible to any IC with fast switching elements, but with a Faraday radius as in (3.10) below. Hence decoupling capacitors are needed for on-demand

xiii List of figures

charge storage for ICs that reside beyond a Faraday radius from the power-supplies. The decoupling capacitors therefore play a critical for supplying the necessary charge on-demand...... 45 Fig. 3.7 The input clamp cell included at each input pad, with no output protection at each output pad. A decision that had to be made due to many uncertainties, leading to risking the ESD-susceptibility of the chip to maximize chances of observing a fast rise-time pulse output...... 50 Fig. 3.8 The triple-microstrip transmission line model used in equation set in (3.11)...... 53 Fig. 3.9 (a) The first control-pulse generator rise-time of 100 ps at 4.2 K, and (b) the pulse-width when Vdwell = 1.2 V showing the jitter on the falling-edge...... 54 Fig. 3.10 Power-to-frequency curves at 300 K, 4.2 K (top), sub-K (middle), showing linear behavior for varying pulse frequency (repetition rates), and the related temperature rise (bottom) at the sample and in the mixing chamber, for sub-K measurements in the dilution refrigerator...... 56 Fig. 4.1 Conceptual schematic diagram of second generation full-digital control- pulse generator...... 60 Fig. 4.2 The schematic design capture for layout generation. The ESD pad protection (ESDPI for input and ESDPO output) cells are also shown in the schematic...... 63 Fig. 4.3 Photomicrograph of second generation control-pulse generator. Die area is 3 mm x 3 mm. The internally clocked version is the large structure on the top, and the externally clocked version at the bottom. The first generation block was also included as visible in the middle of the chip for further testing and investigation. That circuit now has ESD-shunt protection on its power-supply lines. The ESD-shunt structures are present where there are two visible METAL_THICK top-caps of the corresponding MIM- capacitors. In the structure at the top these top-caps are visible just under the power-supply pads at the center-top region of the chip. The structure at the left-bottom is a ring-oscillator (RO) identical to that included in the first generation design, however now with the ESD-shunt protection visible just above the two power-supply pads of the RO. The structure at the left-top is a collection of NFETs and PFETs for individual device characterization. xiv List of figures

The structure at the left-middle just adjacent to the RO power-supply pads is a large inverter (NOT-gate)...... 64 Fig. 4.4 Simulation results of the second generation control-pulse generator. The control-word is 0×0002 to produce the shortest pulse-width possible with this design...... 65 Fig. 4.5 The schematic of the positive-edge triggered 8-bit sequential synchronous flip-flop based shift register cell for control-word load and store with logic-LO set and logic-LO reset. The 16-bit register was designed by cascading two of these 8-bit register cells. Once the register is loaded the control-word is retained throughout the experiment for any repetition rate of the Vtrigger signal...... 66 Fig. 4.6 The buffered ring oscillator schematic design...... 67 Fig. 4.7 The ripple counter schematic design...... 68 Fig. 4.8 The (a) schematic and (b) layout designs of the positive-edge triggered D-type flip-flop register...... 69 Fig. 4.9 The level-triggered D-type flip-flop schematic...... 70 Fig. 4.10 An electrostatic discharge (ESD) event from the 3 kV-2 A standard human-body model [88] to the chip...... 71 Fig. 4.11 The input clamp cell included at each input pad (ESDPI), output clamp cell included at each output pad (ESDPO), and the bidirectional ESD shunt [89] cell included between the power-supply nodes closer to the power- supply (VDD and VSS) pads...... 72 Fig. 4.12 The schematic design of the ESD shunt circuit...... 74 Fig. 4.13 The MOS-diode based power-supply ESD shunt for dissipation of ESD currents and voltages, (a) schematic, (b) layout designs. Design based on a 3 kV–2 A human-body model...... 74 Fig. 4.14 The MOS-diode based input pad ESD clamp, (a) schematic, (b) layout designs for steering ESD current and voltages to the ESD shunt in Fig. 4.12...... 75 Fig. 4.15 The MOS-diode based output pad ESD clamp, (a) schematic, (b) layout designs for steering ESD current and voltages to the ESD shunt in Fig. 4.12...... 76

xv List of figures

Fig. 4.16 (a) An ESD simulation setup and (b) simulation results with a 500 V ESD spike entering the Vtrigger pad, through a 100 pF-1.5 kΩ standard human-body model...... 77 Fig. 4.17 The chip-level full-custom digital control-pulse generator schematic in Cadence®...... 79 Fig. 4.18 The second generation RF-PCB enclosure made for the second generation control-pulse generator chip lying on its mounting-face with its power-supply, input, and output ports labeled...... 80 Fig. 4.19 The enclosure with its mounting-face removed to show the second generation RF-PCB layout with the control-pulse chip bonded in the middle.

and provisions for an RF-SET. The 1206 SMD packaged RuO2 resistor is soldered exactly 5 mm away from the chip. This is the closest to the chip a 1206 SMD package can be placed on this enclosure...... 82 Fig. 4.20 The input trigger waveform (Vtrigger) showing non-ideal edge- transition due to reflections from the high-impedance gate input of the chip. However the significance of the Schmitt-triggers on-board the chip is evident as the chip is still triggered as if the Vtrigger edge transition did not have these anomalies...... 84 Fig. 4.21 Control-pulse output with 50 Ω terminated load showing signal attenuation due to higher loads and voltage division between the switch and the DSO input terminator...... 85 Fig. 4.22 Pulse with high-impedance load showing pulse swing between set- points of ±0.2 V...... 85 Fig. 4.23 The control-pulse output from the second generation circuit as measured using (a) an Agilent DSO8104A DSO with a 13 pF 1 MΩ input impedance, (b) an Agilent 86100B DCA WBO with a 13 pF 50 Ω input impedance; the low levels are due to voltage-division between the 50 Ω load and the output switches. The rise-time (212 ps) was measured at 300 K. What appears to be a second time constant towards the settling time of the pulse is an artifact of the measurement setup as discussed in the following section...... 86 Fig. 4.24 The 4.2 K rise-time and rising-edge-shape measurements of the second generation digital control-pulse generator showing (a) 212 ps rise-

xvi List of figures

time in a 1 ns window, and rising-edge pulse shape in (b) 2 ns, (c) 5 ns and (d) 10 ns windows...... 87 Fig. 4.25 The dilution refrigerator in which the sub-K measurements for the second generation were performed. The helium Dewar (He Dewar) and fridge control unit are also shown...... 88 Fig. 4.26 The sample and its wiring showing the potential heat load on the fridge from the many necessary cables (SMAs for singals, semi-rigid for fast signals, single-core for power-supply). It also shows the copper-powder filter used to filter high-frequency noise from the signals lines...... 89

Fig. 4.27 The temperature-resistance characteristics of a 1580 Ω RuO2 1206 surface-mount device (SMD) resistor...... 90

Fig. 4.28 The standard 4-terminal RuO2 bias and measurement circuit...... 90 Fig. 4.29 Demonstration of the pulse-width and standard deviation (due to sporadic jitter sources) as the control-word is set from 0×0002 to 0×000F. The waveforms and time measurements were obtained using the Agilent DSO8104A low-bandwidth DSO. These sporadic jitter sources are most likely self-heating effects of parts of the counter, or clock, and that heat not flowing evenly through the circuit surface. It was not possible to identify these issues in this generation as there was not enough time to make provisions for such diagnostics...... 92 Fig. 4.30 A pulse for control word of 0×0002 measured with the Agilent 86100B DCA WBO showing the setup time-constant effects. However the fast-rise time is distinguishable...... 93 Fig. 4.31 The same pulse as in Fig. 4.30 for control word of 0×0002 measured with the Agilent 86100B DCA WBO showing the fast-rise time measurable at about 212 ps. This is significant as the chip is producing these rise-times despite the large setup parasitic loads...... 94 Fig. 4.32 The effects of shunting the long 4 m pulse-output line with a shorter 1.5 m cable and (a) Vm2 and (b) Vm1 ports of the enclosure decoupled with 3 parallel-connected 4.7 nF capacitors. The 0x8000 pulse with ~5 µm dwell time was used to test the effects of disconnected the pulse-out line from the refrigerator setup and shunting it with the 1.5 m short cable to the Agilent DSO8104A low-bandwidth DSO...... 95

xvii List of figures

xviii List of tables

List of tables

Table 1.1 A summary of key characteristics of relevant qubit-control literature ..6 Table 2.1 The devices measured from test-chips in the PSC 500 nm and 250 nm processes...... 22

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xx Contents

Contents

Preface ...... i Abstract ...... iii Declaration of originality ...... vii Acknowledgements ...... ix List of figures ...... xi List of tables ...... xix Contents ...... xxi 1 Literature Review: Qubit Control ...... 1 1.1 Introduction...... 1 1.2 Project motivation ...... 2 1.3 The solid-state qubit ...... 4 1.4 Control circuits...... 4 1.4.1 Qubit-CMOS circuits...... 6 1.4.2 Quantum processor architectures...... 7 1.4.3 Nano-CMOS circuits...... 7 1.4.4 Methods of Nano-CMOS fabrication...... 9 1.5 Commercial CMOSFETs at cryogenic temperatures...... 10 1.6 Motivations for using CMOS ...... 12 1.7 The control-pulse generation concept used in this work...... 13 1.8 Specifications (design guidelines) ...... 14 2 Characterization Experiments ...... 17 2.1 Introduction...... 17 2.2 Infrastructure and equipment used ...... 18 2.3 Methodology: using Cadence® Design Systems...... 20

xxi Contents

2.4 I(V) characteristics of NFET and PFET...... 22 2.5 Rise-time characteristics...... 27 2.6 I(V) characteristics of n+-diffusion resistor ...... 30 2.7 Transfer characteristics of a differential amplifier ...... 31 2.8 Lightly-doped drains and contacts at low temperatures...... 33 2.9 Decision on the technology feasibility...... 35 3 First Generation Design ...... 37 3.1 Introduction...... 37 3.2 Schematic and layout designs ...... 37 3.2.1 Control-pulse generation concept...... 37 3.2.2 Control-pulse generator implementation...... 39 3.2.3 On-chip power-supply decoupling capacitors ...... 44 3.2.4 Output ringing due to fast pulse input feed-through...... 47 3.3 ESD protection ...... 48 3.4 Transmission-line design...... 50 3.5 Experimental results at 300 K, 4.2 K, and sub-K ...... 53 4 Second Generation Design ...... 59 4.1 Introduction...... 59 4.2 Schematic and Layout designs...... 59 4.2.1 Control-pulse generation concept...... 59 4.2.2 Control-pulse generator implementation...... 60 4.2.3 Shift-register (16-bit) design ...... 66 4.2.4 Ring oscillator design ...... 67 4.2.5 Ripple-counter design...... 67 4.2.6 Positive-edge triggered D-type flip-flop...... 68 4.2.7 Super-Buffer design...... 70 4.2.8 ESD protection design...... 71 4.2.9 Chip-level integration of cells...... 78 4.3 Experimental results ...... 80 4.3.1 The RF-PCB...... 80 4.3.2 Experimental measurements at 300 K...... 82 4.3.3 Experimental measurements at 4.2 K...... 86 4.3.4 Experimental measurements at sub-K...... 87

xxii Contents

4.3.5 Effects on pulse shape due to measurement setup...... 94 5 Conclusion...... 97 Appendix A – Acronyms and Abbreviations ...... 101 Appendix B – Symbol Index ...... 103 Appendix C – Patents and Publications ...... 105 References ...... 115

xxiii Contents

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xxiv 1 – Literature Review: Qubit Control

1 Literature Review: Qubit Control

1.1 Introduction

My research concentrates on prototyping quantum binary digit (qubit) control circuits for low-power and low-temperature operation. This chapter performs a thorough literature review of the current work in solid-state qubit control and readout systems towards the development of solid-state controller-qubit- observer (CQO) systems and interfaces for a quantum computer (QC). In doing so, it establishes the motivations for this research and provides direction to the discussion that ensues. The focus of this discussion is on current advances in control circuit design and the different process technologies that have been used so far to fabricate such systems. It, then, systematically presents the motivations of this work by introducing a foundry fabricated silicon-on-insulator (SOI) technology that was selected due to the merits it offers for high-speed low-power controller design: the Peregrine Semiconductor Corporation’s (PSC) ultra-thin-silicon (UTSiTM, alternatively, UltraCMOSTM) silicon-on-sapphire (SOS) radio-frequency complimentary metal-oxide-semiconductor (RF-CMOS) 500 nm process. Herein, the term SOS-CMOS refers to RF-CMOS unless stated otherwise.

The nomenclature used herein is based on classical control theory, and its accepted use for quantum control theory [1]. In modern classical control theory, a state-controller is a module that monitors and steers the operational states of the controlled-system, from a pre-defined initial state to a final state in a known time window, and a state-observer is a system that provides an estimate of the internal states of the controlled-system by its input and output measurements.

1 1 – Literature Review: Qubit Control

1.2 Project motivation

Currently, there is a highly motivated research and development momentum towards realizing a solid-state Si:P-based qubit that has the potential to be assembled into complex QC architectures [2], [3] to produce a quantum processor [4-6]. These qubits will require fast external control circuitry most feasibly fabricated and demonstrated in this work using SOS-CMOS technology, and highly electro-spin sensitive readout sensors such as the quantum capacitance coupled to single-electron transistors (SETs). A typical qubit gate operation will consist of initialize (write), rotate (write), execute/process (freely-evolve), and read operations [7], [8]. These quantum operations may be implemented on qubits acting as quantum control registers which intern perform operations on quantum operands implemented on qubits acting as quantum data registers. An examples of such qubit gate operations are the Controlled-NOT gate [9], [10] and the SWAP operation [11].

In solid-state donor-based quantum computers such as the proposed Si:P spin- based system [12], qubit operations are performed by non-adiabatic control [13]. That is, during a control operation a qubit is driven to a semiclassical degeneracy point non-adiabatically [13] (resulting in a state that is not a solution of the Hamiltonian of the quantum system). This causes the qubit to oscillate between the nearest eigenstates of the Hamiltonian of the system [14], as shown in Fig. 1.1. This can be used to characterize a solid-state qubit, once realized. The typical control-signal that enables such non-adiabatic driving is a high-speed control-pulse, either a voltage or a current pulse depending on the type of qubit, which has rise-times in the range of 101–102 picoseconds. Conventionally, these control-pulse signals were generated at 300 K and transmitted along very long coaxial cables to the sub-Kelvin (sub-K: 1 mK to 1000 mK) stage of a dilution refrigerator where an integrated circuit (IC) of qubits would be positioned. My control-pulse measurement experiments have involved typical coaxial cables lengths of about 4 m, so it is possible experiments by others use similar lengths of cable. It is, then, apparent that this approach of delivering control-pulse signals introduces non-idealities to the control and measurement setup. These may be a combination of (a) line- 2 1 – Literature Review: Qubit Control

parasitics such as capacitances, inductances, and resistances, (b) many points of connection increasing the probability of impedance mismatch between cable connections causing reflections, (c) need for attenuators in dilution refrigerator lines to thermalize those lines to the 1 K-pot stage, and (d) the need for terminators at the sample to prevent reflections that both attenuate control signals and increase power dissipation at the sub-K stage (also known colloquially as the “cold-stage”). In addition this method of signal delivery prevents operating on more than one or two qubits impeding on scalability to large-scale quantum computing.

My work, discussed herein, endeavors to exploit CMOS engineering to design and implement full-custom SOS-CMOS based control-pulse generator (controller) ICs for qubit control. These control circuits are, fundamentally, fast monostable multivibrators. The technology used, as mentioned in section 1.1, was the PSC UTSi 500 nm SOS-CMOS process, for which the design GDS-II files were sent to PSC in San Diego, CA and the fabrication and wafer-scribing was performed at the Peregrine Semiconductor Australia (PSA) foundry.

Fig. 1.1 The energy-time diagram of a charge qubit showing fast rise-time control-pulse based non-adiabatic control [15]. 3 1 – Literature Review: Qubit Control

1.3 The solid-state qubit

The solid-state qubit is the fundamental processing unit in a solid-state quantum computer. It is a two-level system used to implement the logic states 0 and

1 , the quantum logic equivalent of the classical logic "0" and "1" states with the added capability of mixing via superposition; a quantum mechanical property. The Si:P-based qubit was proposed as either a charge-based or spin-based qubit for developing a scalable Si-based QC [12], [16]. Recent progress has been made in demonstrating charge-based [13] and spin-based qubits [12], the latter being pursued because of their inherently longer coherence times relative to the former as mentioned above. In many ways, such a qubit can be viewed as a bias-controlled oscillator (BCO) with linear phase response (phase coherence) and noise acting as a phase distorter causing non-linear phase response (phase decoherence) [17-19]; the bias variable of a BCO can be either a voltage in a voltage-controlled oscillator (VCO), or a current in a current-controlled oscillator (CCO). In such a system, scaling will be done via a large number of interactive processing and ancillary qubits [2]. It has been shown in quantum control theory [20], [21], that a solid-state qubit, such as the Si:P-based qubit, is a feasible platform for scalable QC architectures [2], [3], [15], [22], [23] if they are to be realized into industrially viable applications [8]: numerical factoring, database searching, cryptography, and communication to name few. There are many qubit implementations in addition to the solid-state qubit, such as the flux qubit implemented on a superconducting cooper-pair-box [6], [24], [25], the ion-trap qubit [26], and the optical qubit [27]. However these are not elaborated here, as the thrust of this work is on the control-pulse generation design and demonstration at 300 K, 4.2 K, and sub-K.

1.4 Control circuits

There have been several reports of control circuits being implemented in rapid- single flux quantum (RSFQ) technology for superconducting flux qubits. In 2004, the Devoret and Martinis teams reported on their work on implementing qubits with superconducting ICs [28], and In 2005, Ohki et al. reported a RSFQ- 4 1 – Literature Review: Qubit Control

based qubit control circuit for their JJ-qubits with 50 ps rise-times [29]. Earlier, Nakamura et al. had demonstrated unipolar fast pulse measurement of a single- Cooper-pair box (SCB) qubit using a radio-frequency single-electron transistor (RF-SET) [6], [14]. Others have performed similar single-shot qubit measurements [13], [30], [31]. Some have even reported on Cooper-pair box (CPB) flux qubits fabricated for CMOS compatibility [24], [32] [33-35]. The CPB is usually accompanied by RSFQ control circuits and SQUID readout circuits both of which are superconducting Josephson-junction (JJ) based. However, these are bulky superconducting switching elements usually with the need for direct current (DC) biases and external applied magnetic fields. In some instances, single-electron transistors (SETs) are used for weakly-coupled readout as opposed to superconducting quantum interference devices (SQUIDs) used for strongly-coupled operating on switching-currents [13]. However all these devices and circuits were with JJ-based qubits and drivers. There has been much work [29], [36-39] towards taking superconducting JJ- based circuits towards the mainstream of fast low-temperature control of qubits.

However according to Semenov et al. [40], each JJ-gate dissipates about 0.1– 10 µW due to critical currents of 0.1–0.3 mA and DC biases of 0.3–3 mV per JJ- gate. Hence a typical circuit of say 100-gates with fairly low-complexity can easily reach dissipation levels of 1 mW and above. These are very high dissipation levels for low-functional circuits, and at such levels sub-K temperatures can only be maintained by large and expensive dilution refrigerators with high cooling power ratings. These reasons also limit the scalability of these technologies. So there is a clear need to explore other technologies, and the best mainstream contender for this is CMOS technology.

The main advantages of developing control circuits in CMOS technologies are their capability to produce large and stable voltage or current control signals with relatively low-power dissipation, very-large scale integration (VLSI), its technology maturity with the abundance of support from computer-aided design (CAD) tools (e.g. Cadence® and Mentor Graphics®) to foundry support and process development kits (PDKs). Also CMOS does not need externally applied magnetic fields to operate compared to other technologies in the quantum 5 1 – Literature Review: Qubit Control

control arena such as RSFQ. Hence it is a versatile technology to explore. These and other work specific to qubit-CMOS circuits are summarized with their key performance characteristics, where mentioned, in Table 1.1.

Table 1.1 A summary of key characteristics of relevant qubit-control literature

Qubit Controller The Key Performance Characteristic Reference Technology Technology Emulated on CMOS An 8-bit quantum-circuit processor (QCP) emulated [41] CMOS on a programmable logic device (PLD) with the capabilities and expected speeds of a quantum computer on performing the quantum Fourier transform. JJ CMOS CMOS-chip fabricated in 250 nm process of the [34] National Semiconductor Corporation (NSC). JJ-chip wire-bonded to CMOS-chip Ion-Traps CMOS Scalable ion-traps for CMOS-based addressability. [42], [43] JJ RSFQ 50 ps rise-times with pulse-widths as short as [29] 200 ps. JJ – 0.1–10 µW per JJ-gate. [40] JJ RSFQ 8 GHz clock for a non-destructive readout (NDRO) [36] memory cell and superconducting qubit. CPB RF-SET Fast pulse measurement of a single-Cooper-pair [6], [13], box (SCB) qubit using a radio-frequency single- [14], [30], electron transistor (RF-SET). [31]

1.4.1 Qubit-CMOS circuits

Reports on these types of circuits are scarce or non-existent. Scalable qubit- CMOS control circuits is a novel field of research in quantum control and interfacing, thus the literature on qubit-CMOS control circuits at cryogenic temperatures is scarce. Apart from the above citations, this work appears to be the only work directly in the area of qubit-CMOS control at low temperatures. This is, still, a field in its infancy with a solid-state Si:P qubit yet to be implemented on which the CMOS circuits demonstrated in this work can be used to perform a controlled-gate operation.

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However, in 2002, O’uchi et al. reported a very interesting piece of work on developing a CMOS based 8-bit quantum-circuit processor (QCP) which was reported to emulate the capabilities and expected speeds of a quantum computer on performing the quantum Fourier transform [41], [44]. They reported that they implemented their 8-bit QCP on a fractal hardware architecture in LSI within a programmable logic device (PLD). There have been distantly related qubit-CMOS work, but using superconducting junctions (JJ-CMOS) as also mentioned in the literature above [32-35]. Hence CMOS circuits can be used in place of these RSFQ control, SQUIDs readout, and SETs readout.

1.4.2 Quantum processor architectures

The spin qubit is preferred for quantum computation literally because of the longer quantum phase coherence times of spin relative to charge. Generally spin qubits have about three (or higher) orders of magnitude coherence times than charge qubits. This is advantageous from a practicality perspective. There has been recent progress in coherent manipulation of electron spins in semiconductor quantum dots [7], [11].

In our group, Clark et al. have been working on a Si:P-based platform towards realizing a spin qubit since the proposition of the Kane architecture [12]. Since then much work has been done on QC architectures. Hollenberg et al. have performed much work on quantum controllers for quantum systems [1]. Particularly interesting is the coherent transport thought adiabatic passage (CTAP) proposed by Hollenberg et al. [2], [3], [15], which uses Si:P two-level systems as both qubits and coherent pathways for inter-qubit communication; for a comprehensive discussion on the CTAP-based architecture, the reader is especially referred to [2] published in 2006 as the motivations for my wok in CMOS control circuits originate from the need to explore and exploit control concepts for qubits in these, and similar, architectures.

1.4.3 Nano-CMOS circuits

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Apart from qubits in proposed quantum computer architectures, other nanoelectronic devices can be driven using CMOS control and observe circuitry, which also forms an inertially ever-increasing need to explore CMOS control circuits for operation at many different temperature ranges. There have been many nano-scale devices being researched and developed since Richard Feynman’s famous lecture in 1959 on his vision for the future in nano-scale technologies [45], and just as many varied attempts to interconnect these nanoelectronic devices with CMOS monolithically [46].

The fundamental physical phenomenon of Coulomb blockade was observed in metal-insulator tunnel junctions in the 1980s [47], [48]. Following this discovery, Fulton and Dolan developed the first successful single-electron transistor demonstrating the Coulomb blockade in 1987 [47], [49]. Since then, there have been a myriad of SET architectures and fabrication processes that have been proposed [48], however the fundamental carrier transport mechanism is still based on the Coulomb blockade. The theory of SET devices is quite explicitly explained in [50]. There have been much work on attempts to integrate nano- CMOS devices using conventional and modern CMOS technologies, such as in SOI where single-electron transistors have been fabricated using point contacts [25], [47], [51], [52], on SOI.

In 1994, Matsuoka et al. from the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan reported their investigation of quasi-one-dimensional FETs (also referred to as quantum-wire FETs – QWRFETs) and Coulomb blockade FETs using MOS technology with dual gate structures [53]. Hiramoto et al., in collaboration with the Institute of Industrial Science, University of Tokyo, Tokyo, Japan, and Texas Instruments, Tsukuba, Japan, have developed an anisotropic etching technique for the fabrication of a QWRFET on SOI, which produced clear Coulomb blockade oscillations when characterized at 4.2 K (liquid helium temperature), 77 K (liquid nitrogen temperature), and 300 K (room temperature) [54].

Devoret and Schoelkopf from the Department of Applied Physics, Yale University, CT, USA, and Service de Physique de l’Etat Condense, CEA- 8 1 – Literature Review: Qubit Control

Saclay, France, respectively, have reported on the capability of SET devices to operate as both ultra-sensitivity electrometers and quantum signal amplifiers in situ, due to their ultra-high charge sensitivities of 10–5q Hz–1/2 currently experimentally measured, and 10–6q Hz–1/2 theoretical limit [55-58]. This means the SET can detect 10–5q within a 1 s measurement period (the precision increases proportional to the square-root of the measurement period). Additionally, recently the SET has been realized to perform operations on qubits, with minimal perturbation on their quantum evolution, rendering their SET as a quantum charge amplifier operating at the vicinity of the quantum limit. These characteristics of the SET make it an ideal candidate for electro- metrology, and quantum (spin) state sensors in solid-state qubit systems [55].

In 2004, Guimarães et al. had worked on developing a current-mirror model for SET based nanoelectronic devices [59]. Their model depends on biasing a dual-SET around a triple-state operating point determined by the gate-to-island capacitances and tunnel-junction capacitances. Biasing the dual-SET circuit at a particular DC quiescent point (Q-point) allows oscillating the circuit about the stability envelope of that Q-point using an AC incremental signal, such that the number of electrons on the two islands, denoted (n1, n2), oscillate sequentially between the states (0, 0), (1, 0), and (0, 1). At the end of each period the circuit pumps one electron to the load. This seems like an interesting concept for nanoelectronic current-mirrors, although at first glance the state machine appears to require high frequency switching improved models may provide feasible topologies for engineering such circuits for practicable use.

1.4.4 Methods of Nano-CMOS fabrication

Silicon-on-insulator (SOI) technology composes several fabrication mechanisms such as ELTRANTM, PADOX, SIMOX, and SIMON. The former, ELTRANTM, which is a trademark of Canon, Inc., Kanagawa, Japan, is an abbreviation for epitaxial layer transfer and was developed to produce SOI wafers from epitaxially grown porous Si for high quality, high stability, low-cost SOI wafers

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[60]. Although these are worth noting here, I will not be elaborating on them, as such processes are varied and readily available in the literature.

1.5 Commercial CMOSFETs at cryogenic temperatures

It is obvious that if CMOS is to be integrated with quantum or nano-devices, they must behave similarly at sub-K, 4.2 K, and 77 K, as they do at 300 K.

In 1994, K.-W. Ng from the Department of Physics and Astronomy, University of Kentucky, Lexington, KY, USA reported on first experimental results and a comprehensive discussion on the operation of an all-MOSFET operational amplifier (ICL76111) at 4.2 K [61]. He specifically clarifies the all-MOSFET aspect of the chip void of any bipolar junction transistors (BJTs) anywhere in the circuit. Hence he states that MOSFETs will operate without hindrance at 4.2 K, while that is impossible for diodes and BJTs. This is because any minority carrier device such as a BJTs or diodes will have localization of carriers within the bulk as well as at heterojunctions thus freezing-out at cryogenic temperatures [61]. He also notes that the operational amplifier ceases to operate between 30-40 K but resumes operation when the bipolar power supply was increased from the nominal ±9 V to ±14 V. However the latter rail-to-rail power supply voltage would have resulted in certain destruction of the amplifier at room temperature but was necessary for operation at 4.2 K. This requirement to increase the power supply voltage is attributed to the appearance of potential barriers between the channel and the highly doped drain and source contacts [61], [62].

Feng et al. from the University of California, Berkeley, designed and fabricated an interface circuit for operation at 4.2 K using the 250 nm National Semiconductor Corporation (NSC) process for their CMOS chip, and the UC Berkeley’s 6.5 kA·cm–2 niobium (Nb) process for their Josephson junction (JJ)

1 The ICL76XX series of industrial low-power all-MOSFET operational amplifiers are available from Maxim Integrated Products (Dallas Semiconductor Corp.) at http://www.maxim-ic.com. 10 1 – Literature Review: Qubit Control

chip. The functionality of the interface circuit has been tested and proved by wire-bonding the CMOS chip to the JJ chip. They also have demonstrated the design and fabrication of a 64-kbit JJ-CMOS hybrid memory prototype, which includes an ultra-high-speed interface, address buffers, word line decoders, 3T DRAM-type cells, and JJ-based sensing circuits. These were all fabricated in the above-mentioned 250 nm NSC CMOS process and the UC Berkeley Nb process. They have predicted sub-nanosecond access times by a conservative simulation using a room temperature model for the CMOS devices. Additionally, their approach has been to develop a stacked-die structure using very short wire bonding with which they attempted to measure the sub-nanosecond access times [34]: this approach may be suitable for multiple-chip module (MCM) wire bonded contacting of SET die to CMOS FET die, investigated in this work. This is a very good example of the resilience of CMOS FET devices even when used from a restrictively standardized commercial fabrication facility such as NSC. This seems to suggest that the operation of CMOS FET technology at 4.2 K is independent of the fabrication process: the CMOS transistors seem to operate as predicted by 4.2 K models.

On the contrary, Suzuki et al. from Nanoelectronic Research Institute in collaboration with Meiji University, seem to claim that the low-temperature operation of CMOS FETs is dependent on process by comparing MOSFETs in the 40 nm to 135 nm gate length range fabricated via epitaxial layer transfer (ELTRANTM), SIMOX, and wafer-bonding [63]. They claim that the ELTRANTM fabricated MOSFETs have no detrimental characteristic changes, thus deducing that this process yields uniform ultra-thin (4 nm) SOI MOSFETs without abnormal behavior from changes in the channel regions even at temperatures as low as 22 K. They claim that SIMOX produces structures that exhibit Coulomb oscillations at the same temperature, while the wafer-bonding process produces low yield [63]. This report seems to suggest that the operation characteristics of CMOS FETs at 4.2 K may be dependent upon the fabrication process used as well as the physical architecture of the device.

There are also reports of the well-known drain current kink in the ID(VDS) characteristics of commercially available, standard CMOS process fabricated, 11 1 – Literature Review: Qubit Control

MOSFET structures when operated at 4.2 K, due to hot-carrier effects (HCEs) such as the kink effect and impact ionization effect [64-68]. These HCEs seem to result from Coulomb scattering from the oxide-to-bulk interface or channel-to- bulk charges. This behavior seems to be speculated as being a direct consequence of carrier mean free path and mobility modulation: for low VGS

Coulomb scattering dominates, and for high VGS surface roughness scattering dominates [64]. It has also been suggested that lightly doped drain (LDD) transistors may have reduced kink effect 4.2 K, relative to non-LDD transistors [64]. Refer Chapter 2 for an analysis and investigation of the effects of operating commercial foundry fabricated MOSFETs with LDD structures at ≤ 4.2 K on their characteristics, to determine the feasibility of commercial MOSFET processes for nano-CMOS interfacing and integration.

On slightly unrelated matters, but still relevant to this literature review, there has been reports on fast duty-cycle control circuits and their application to frequency dividers that may be used with voltage-controlled oscillators (VCOs) in phase- locked loops (PLLs) [69]; which seems to be a common application of fast monostable multivibrator circuits.

Based on this discussion, I believe the operability of commercially processed CMOS FET technology at 4.2 K should be further investigated, experimentally, to clarify operational characteristics via a simple integrated circuit platform such as differential pairs or logic gates. I have demonstrated both of these, which will be discussed in Chapter 2.

1.6 Motivations for using CMOS

As evident from the above discussion, there has been progress on using superconducting devices and circuits for quantum computing such as the CPB to implement qubits, RSFQ circuits to implement the control circuits, and SQUIDs to measure the CPB qubit states; and until recently these were the technologies conventionally being proposed as the suitors for controlling and

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measuring qubits. However there are many hindering limitations to these technologies, as already mentioned in section 1.4.

My literature review showed that CMOS technologies had not been explored at all beyond mere curiosity, as a potential contender for qubit control. It was, then, my challenge to research and demonstrate that CMOS technology can be used for its many advantages (also discussed in section 1.4). As power dissipation is a critical limitation in qubit circuits and the control circuits they are coupled to, it was important to identify CMOS technologies available in commercial foundries that would allow low-power devices. I immediately identified that SOI-CMOS technologies were the leading candidates for the purpose of this project; the main reason being significantly lower device capacitances in SOI-CMOS devices compared to bulk-CMOS devices resulting in significantly lower power dissipation especially in switching circuits, and from the same reasoning significantly faster rise-times achievable. Further research following the wide literature review performed, revealed that the PSC SOS-CMOS 500 nm technology was the best candidate that subsequently made it possible to implement the low-power high-speed control circuits that, are discussed in Chapters 3 and 4.

1.7 The control-pulse generation concept used in this work

The core focus of my work [70-75] was to design a monostable multivibrator circuit that was capable of operating at cryogenic temperatures, along side qubits. As a strong believer of the well-known principle of Ockham’s razor [76], [77] that “all things being equal, the simplest solution is usually the best”, I based my designs on a standard-logic voltage-pulse generator [78] which his the simplest monostable multivibrator implementable. In this design, the control- pulse trigger input (Vtrigger) signal takes two paths to the pulse generating AND-gate (for specific designs refer Fig. 3.3 in Chapter 3 and Fig. 4.2 in Chapter 4): one through a delay element (i.e. logic-inverters or digital delay) to one input and the other direct to the other input such that while Vtrigger is either at logic-low (LO), logic-high (HI) or transitioning from HI to LO the output is LO.

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The only duration the AND-gate output toggles HI is from the time Vtrigger makes a transition from LO to HI until such time Vtrigger propagates through the delay element. Once this event occurs, the output toggles to LO again. The resulting AND-gate output is then boosted with a super-buffer stage. The super- buffer stages were designed to drive a qubit-gate load of about 100 fF to 1 pF maintaining rise-times of the order of the 100 ps estimated from Cadence® Spectre simulations. On-chip decoupling capacitors were used for charge- supply on-demand to the fast output switches as the power-supply lines would not be able to supply currents at timescales of the order of these rise-times.

1.8 Specifications (design guidelines)

The control-pulse generator will be designed to be triggered by an externally generated trigger-pulse. This trigger pulse may or may not be a fast pulse and can even be as slow as a sinusoid or a triangle. This allows for slow and low- cost trigger generators to be utilized if necessary such as 74-series logic, 555- timer, or slow function generators such as the Tektronix AFG320. In actual fact, the slower the trigger pulse the better it is for qubit control as there would be almost no ringing effects due to on-chip feedthrough from trigger input to pulse output. On this note, the second generation circuit in Chapter 4 can actually be driven using a sinusoidal trigger, which is significantly slower compared to the pulse produced. This circuit has high commercial viability, therefore the concepts herein have been patented [72]. The external trigger pulses are delivered to the control-pulse generator chip via an immersion column housing high-speed RF lines in the dilution refrigerator. Additionally, it may have analog and digital lines to control the amplitude and duty cycle (dwell time) of the output pulse. A top-level diagram of this concept is shown in Fig. 1.2b.

The design specifications are setout loosely as design guidelines rather than strict requirements, due to the uncertainties anticipated in the SOS-CMOS device and circuit performance at previously untested temperatures that they will be exposed to in this work. These design guidelines listed below, are

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governed by the anticipated qubit characteristics from theoretical studied by Hollenberg et al. and are available in [15]. The guidelines are i) 100 ps rise-times and fall-times or thereof; picosecond timescales are required to drive a qubit non-adiabatically: the rise-time is limited by the process used which is in-turn limited by the finances available ii) 100 µW power dissipation or thereof, limited only by the cooling power of the dilution refrigerator available (Kelvinox K-100): hot control circuits will be challenging to directly couple to qubits (say with bonding wire or transmission lines) as inevitably there will be heat propagation to the qubits. So the cooler a control-pulse generator chip is the better. iii) stable steady-state response between ∓ 100 mV and ± 500 mV: these are the voltage stated in [15], but not limited to these values. iv) pulse jitter roughly on order of the rise-time would suffice: jitter is unavoidable and ultimately limited by homogeneity of materials in circuit, however the lesser the jitter the more precise qubit control can be. v) repetition rate (trigger frequency) can be about 10-100 MHz or thereof: this is the rate of qubit control operations.

The tentative quantum-classical control system is shown in Fig. 1.2a. In this system, the CMOS controller and CMOS observer may be positioned at either the 1 K or 4.2 K stages of a dilution refrigerator. Placing them at these stages allows for higher power dissipation which lessens the constraints on the power budget available for the controller and observer designs. However some multiplexing may be positioned at 1 K or 4.2 K stages or even at the sub-K stage if needed. Multiplexing and demultiplexing will be needed as an realistic QC may have millions or more qubits hence millions or more control and measure bus lines.

The controller and observer may have communication interfaces with classical processors at 300 K, for control-word feed, setup, monitoring, and diagnostics purposes. However the qubit control will be done at the controller-observer level with the quantum information being processed at the quantum processor level.

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classical network classical 300 K processor processor communication bus

CMOS feedback CMOS 1−4.2 K controller observer

nm nm

1−4.2 K or multiplexer demultiplexer sub−K superconducting transmission line nk bus nk

sub−K quantum processor (a)

VDD Vm2

Vtrigger

CLK

DATA Vpulse Control−Pulse Generator Vdwell

SET

RESET

VSS Vm1 (b)

Fig. 1.2 (a) The overall quantum-classical control system showing where the classical CMOS may be positioned and what interfaces could be connected to the quantum processor. (b)required inputs and outputs of the control-pulse generator chip from loosely set guidelines as design requirements. Some or all of the shown inputs may be used in a design.

16 2 – Characterization Experiments

2 Characterization Experiments

2.1 Introduction

This chapter discusses the characterization of the Peregrine Semiconductor Corporation (PSC) 500 nm and 250 nm ultrathin-silicon (UTSi) silicon-on- sapphire complimentary metal-oxide-semiconductor (SOS-CMOS) processes. It discusses the experimental setups used to perform various device measurements that lead to the decision to use this technology for realizing integrated CMOS circuits for qubit control. It also discusses the design specifications setout quite loosely as design guidelines for the control-pulse generator circuits that ensued. These circuits are analyzed and discussed in Chapters 3 and 4. Limited by available funding and the calculated risks given the unknown nature of this work, the designs discussed in Chapters 3 and 4 were sent to the foundry before the multi-project reticle (MPR) cut-off at those stages of this thesis. The differential amplifier discussed in section 2.6 of this chapter was fabricated in the second run of the two MPR runs of this thesis.

Herein, device aspect ratios (W/L) are in micrometer/micrometer (µm/µm), and to maintain similar drive-strength in the PFETs as in the NFETs, the width of each PFET device is set to 1.4286 times the width of its complimentary NFET device in a cell. For instance, in the smallest inverter cell possible with the process used, the PFET W/L = 2.0/0.5 relative to the NFET W/L = 1.4/0.5, calculated according to the mobility of holes in the p-channel relative to the mobility of electrons in the n-channel.

17 2 – Characterization Experiments

2.2 Infrastructure and equipment used

All direct current (DC) measurements were made in 4.2 K Dewars for 300 K and 4.2 K measurements and in the Kelvinox K-100 dilution refrigerator, in Fig. 2.1a, for sub-K (sub-K – 30 mK base to about 1000 mK) measurements. The other equipment used are the Agilent DSO8104A lower bandwidth digital-storage oscilloscope (DSO), Keithley 236 Source-Measure Unit (SMU), Stanford Research Systems SR830 DSP Lock-In Amplifier, Stanford Research Systems SIM900 MAINFRAME, and the Tektronix AFG320 Function Generator in Fig. 2.1b, the Agilent Infinium 86100B DCA wide-band oscilloscope (WBO) in Fig. 2.1c, the Stanford Research Systems SR830 DSP Lock-In Amplifier, the Anritsu MP1763C 30 ps rise-time Pulse Pattern Generator in Fig. 2.1d.

These are the most frequently and extensively used resources, although there were other occasionally used equipment for related measurements. There were instances when an EG&G Instruments 5216 DSP Lock-In Amplifier was used instead of the SR830 with similar results, however the was a lot more user- friendly.

18 2 – Characterization Experiments

1 K-pot stage

Mixing– Chamber stage

Sample stage

(a)

(b)

19 2 – Characterization Experiments

Fig. 2.1 (a) The Kelvinox K-100 dilution refrigerator, warmed to 300 K with sample loaded. (b) the DSO8104A lower bandwidth digital-storage oscilloscope (DSO), Stanford Research Systems SR830 DSP Lock-In Amplifier and SIM-controller, Tektronix AFG320 Function Generator, (c) the Agilent 86100B DCA wide-band oscilloscope (WBO), and (d) the Anritsu MP1763C Pulse Pattern Generator.

2.3 Methodology: using Cadence® Design Systems

It is worth mentioning, briefly, about the design methodology used as this is complimentary in an engineering design project to the design itself which I strive to achieve with timely design-for-manufacturability (DFM) type product rollout. Cadence® is one of the most popular commercial custom IC design tools available. It is an integrated design environment (IDE) for IC design, design- rules check (DRC), simulation, extraction, layout-versus-schematic (LVS) check, and tape-out. My design approach involved the sequential design steps shown in Fig. 2.2. More specifically, each step was cycled through between several steps before and after it resulting in a very recursive design approach. This was necessary to ensure a fully-functional error-free IC GDS-II file at tape- out producing results as per the specifications setout earlier.

The schematic capture was done in Cadence® Schematic Composer, and the layout was compiled in Cadence® Virtuoso Layout XL. The simulations were done in Cadence® Virtuoso Spectre analog design environment (ADE) SPICE simulator. Extraction and LVS was performed in Layout XL. As mentioned

20 2 – Characterization Experiments

above, repetitive DRCs were performed on individual cell-blocks during compilation and testing, and the final DRC was performed after inclusion of all the chip cell-blocks in the “PSC_DIE_SEAL” cell from the PSC PDK; this is the layer that instructs the foundry where the chip scribe-boundaries are.

Design Specification

Schematic Capture

Create Symbols

Simulation

Layout

DRC

Extraction

LVS

Post-layout simulation

Fig. 2.2 The design methodology I used in my custom IC design approach.

21 2 – Characterization Experiments

2.4 I(V) characteristics of NFET and PFET

In order to gain a clear understanding of the feasibility of the PSC process for the above design guidelines (or requirements), I obtained some test chips from the PSC foundry (Peregrine Semiconductor Australia) with individually accessible NFET, PFET devices, and resistors as listed in Table 2.1.

Table 2.1 The devices measured from test-chips in the PSC 500 nm and 250 nm processes.

The VGS and VDS ramps were in steps of 0.2 V from 0.0 V to 2.0 V for the 300 K and 4.2 K results, and in steps of 0.1 V from 0.0 V to 1.0 V for the sub-K results of Fig. 2.4 and Fig. 2.5. This enabled me to characterize and demonstrate NFET and PFET devices from the above mentioned commercial SOS RF- CMOS 500 nm and 250 nm foundry process with measurements at 300 K, 4.2 K, and sub-K [71] that lead to the decisions to design the first and second generation full-custom control-pulse generators that resulted in several conference papers, journal papers, and patents [70-73], [75]. The acronym “SOS RF-CMOS” will, herein, be referred to as “SOS-CMOS”.

The setup in Fig. 2.3a was used to perform DC measurements on NFET and PFET devices as well as a n+-well resistor. Once the test chips are bonded onto a leadless-chip-carrier 20 pin (LCC20) package, the sample was mounted onto a 4.2 K immersion-column that allows immersion into a liquid-helium Dewar. Once mounted, 300 K tests were performed using a source-measure-unit (Keithley SMU 236) to ramp the drain voltage and measure the drain current and a DC ramp generator (EG&G Instruments 5210 Lock-In Amplifier DAC) was used to ramp the gate voltage, of either the NFET or PFET. Both the SMU and DAC were computer-controlled using GPIB (IEEE 488) via National 22 2 – Characterization Experiments

Instruments® LabView software. Fig. 2.3a shows the DC ramp generator driving the gate voltage in an upward ramp followed by a downward ramp; this was done to ascertain hysteretic effects during device operation while temperature cycling between 300 K and 4.2 K, or 300 K and sub-K. Fig. 2.3b shows the LCC20 onto which the test chips were aluminium (Al) wire-bonded. The signal cables were typically about 4 m long from the ports of the measurements equipment at 300 K to the test chip mount at the cold-finger of the immersion column.

(a)

(b)

Fig. 2.3 (a) Experimental setup for direct current (DC) measurement and characterization of SOS-CMOS NFET, PFET devices from the PSC 500 nm and 250 nm, and n+-diffusion resistor from the PSC 500 nm process. (b) The LCC20 package onto which the test chips were Al wire- bonded.

23 2 – Characterization Experiments

The measurements are shown in Fig. 2.4 for the 10/0.4 NFET and PFET devices from the PSC 500 nm SOS-CMOS process and in Fig. 2.5 for the 10/0.25 NFET and PFET devices from the PSC 250 nm SOS-CMOS process. The NFET and PFET devices tested from both processes showed slight deviations from their 300 K characteristics but these were more evident in the devices from the 500 nm process relative to those from the 250 nm process. These deviations [71] were

1) non-linear behavior in the normally-linear triode region, 2) what appear to be short-channel effects (SCEs) in the strong-saturation region, and 3) a slight increase in gain possibly due to lower charge scattering rates at lower temperatures.

The SCEs and higher gain were not that critical however the triode region non- linearity was a concern as the resulting higher resistance in the vicinity of the cut-off region can slow switching behavior (e.g. settling times) of the FETs thus affecting the design of switching circuits such as mixed-mode and full-digital control-pulse generator circuits. I emphasize that due to the non-disclosure agreement (NDA) and confidential nature of these foundry processed devices, I had limited information of the device design parameters to work with. However based on previously published material of similar triode-region kinks [64], [79], it is reasonable to speculate that these could be occurring at low temperatures due to carrier freeze-out in the lightly-doped drain (LDD) structures of modern poly-silicon CMOS processes or due to Schottky barrier formation at their Ohmic contacts. Such exaggerations of potential barriers along the current channel can cause non-linear conductance behavior in the I(V) curves at low applied drain-source biases. This LDD related kink-effect is further discussed in section 2.8 below. However more importantly, to deduce whether these devices were suitable for cryogenic control-pulse ICs, fast pulse response experiments had to be performed. The next section is on transient response thus performed.

24 2 – Characterization Experiments

2.5 2.5

2 2

1.5 1.5

1 1 PMOS W/L = 10/0.4 PMOS W/L = 10/0.4 V = [−2, 0] V V = [−2, 0] V 0.5 DS 0.5 DS ∆V = (−0.2) V ∆V = (−0.2) V DS DS 0 0 (mA) (mA) D D

I NMOS W/L = 10/0.4 I NMOS W/L = 10/0.4 V = [0, 2] V V = [0, 2] V −0.5 DS −0.5 DS ∆V = 0.2 V ∆V = 0.2 V DS DS −1 −1

−1.5 −1.5

−2 −2 300 K 300 K −2.5 −2.5 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 V (V) V (V) GS DS (a) (b)

2.5 2.5

2 2

1.5 1.5

1 1 PMOS W/L = 10/0.4 PMOS W/L = 10/0.4 V = [−2, 0] V V = [−2, 0] V 0.5 DS 0.5 DS ∆V = (−0.2) V ∆V = (−0.2) V DS DS 0 0 (mA) (mA) D D

I NMOS W/L = 10/0.4 I NMOS W/L = 10/0.4 V = [0, 2] V V = [0, 2] V −0.5 DS −0.5 DS ∆V = 0.2 V ∆V = 0.2 V DS DS −1 −1

−1.5 −1.5

−2 −2 4.2 K 4.2 K −2.5 −2.5 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 V (V) V (V) GS DS (c) (d)

0.1 0.1

0.08 0.08

0.06 0.06

0.04 0.04 PMOS W/L = 10/0.4 PMOS W/L = 10/0.4 V = [−1, 0] V V = [−1, 0] V 0.02 DS 0.02 DS ∆V = (−0.1) V ∆V = (−0.1) V DS DS 0 0 (mA) (mA) D D

I NMOS W/L = 10/0.4 I NMOS W/L = 10/0.4 V = [0, 1] V V = [0, 1] V −0.02 DS −0.02 DS ∆V = 0.1 V ∆V = 0.1 V DS DS −0.04 −0.04

−0.06 −0.06

−0.08 −0.08 ~30 mK ~30 mK −0.1 −0.1 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 V (V) V (V) GS DS (e) (f)

Fig. 2.4 The DC response ID(VGS) characteristics at (a) 300 K, (c) 4.2 K, (e) sub-K, and ID(VDS) characteristics at (b) 300 K, (d) 4.2 K, (f) sub-K of the PSC 10/0.4 NFET devices shown for positive voltages, and 10/0.4 PFET devices shown for negative voltages on the voltage axes. All devices are from the PSC 500 nm SOS-CMOS process. The VGS and VDS voltages are in steps of 0.2 V for 300 K and 4.2 K results, and in steps of 0.1 V for sub-K results.

25 2 – Characterization Experiments

5 5

4 4

3 3

2 2 PMOS W/L = 10/0.25 PMOS W/L = 10/0.25 V = [−2, 0] V V = [−2, 0] V 1 DS 1 DS ∆V = (−0.2) V ∆V = (−0.2) V DS DS 0 0 (mA) (mA) D D

I NMOS W/L = 10/0.25 I NMOS W/L = 10/0.25 V = [0, 2] V V = [0, 2] V −1 DS −1 DS ∆V = 0.2 V ∆V = 0.2 V DS DS −2 −2

−3 −3

−4 −4 300 K 300 K −5 −5 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 V (V) V (V) GS DS (a) (b)

5 5

4 4

3 3

2 2 PMOS W/L = 10/0.25 PMOS W/L = 10/0.25 V = [−2, 0] V V = [−2, 0] V 1 DS 1 DS ∆V = (−0.2) V ∆V = (−0.2) V DS DS 0 0 (mA) (mA) D D

I NMOS W/L = 10/0.25 I NMOS W/L = 10/0.25 V = [0, 2] V V = [0, 2] V −1 DS −1 DS ∆V = 0.2 V ∆V = 0.2 V DS DS −2 −2

−3 −3

−4 −4 4.2 K 4.2 K −5 −5 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 V (V) V (V) GS DS (c) (d)

0.1 0.1

0.08 0.08

0.06 0.06

0.04 0.04 PMOS W/L = 10/0.25 PMOS W/L = 10/0.25 V = [0, −1] V V = [0, −1] V 0.02 DS 0.02 DS ∆V = (−0.1) V ∆V = (−0.1) V DS DS 0 0 (mA) (mA) D D

I NMOS W/L = 10/0.25 I NMOS W/L = 10/0.25 V = [0, 1] V V = [0, 1] V −0.02 DS −0.02 DS ∆V = 0.1 V ∆V = 0.1 V DS DS −0.04 −0.04

−0.06 −0.06

−0.08 −0.08 ~30 mK ~30 mK −0.1 −0.1 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 V (V) V (V) GS DS (e) (f)

Fig. 2.5 The DC response ID(VGS) characteristics at (a) 300 K, (c) 4.2 K, (e) sub-K, and ID(VDS) characteristics at (b) 300 K, (d) 4.2 K, (f) sub-K of the PSC 10/0.25 NFET devices shown for positive voltages, and 10/0.25 PFET devices shown for negative voltages on the voltage axes.

All devices are from the PSC 250 nm process. The VGS and VDS voltages are in steps of 0.2 V for 300 K and 4.2 K results, and in steps of 0.1 V for sub-K results.

26 2 – Characterization Experiments

Even with the restrictions imposed by the NDA on publishable information, I was permitted to study the devices from an external characterization perspective. Even so, these experiments allowed me to study their behaviors sufficiently to make informed decisions on their use in LSI circuits. They also showed that these devices have repeatable behavior from temperature cycling suggesting they survive the resulting thermal shock [71].

2.5 Rise-time characteristics

Once the NFET and PFET devices were demonstrated to show favorable DC I(V) characteristics at 4.2 K and sub-K the next natural progression in their characterization was to obtain their rise-times and switching characteristics. Fig. 2.6a shows the experimental setup that was used to perform these tests, where the DSO is the Agilent 86100B DCA wide-band oscilloscope (WBO) with a 13 pF 50 Ω input impedance and the pulse generator is the Anritsu MP1763C. This is a PFET source-follower circuit with the DSO input and terminator resistances as its loads. Measurements on a PFET were preferred and sufficient, as an NFET would have been similar or better in performance. The terminators were essential to avoid reflections in the setup which were significant when tested without terminations. Even with the attenuation caused by the parallel combination of these loads, the measured switching signal still revealed useful information about the device characteristics when cooled. Fig. 2.6b shows the radio-frequency printed circuit board (RF-PCB) onto which the test chips were Al wire-bonded. This RF-PCB was used to avoid parasitic degradation of the measured signals if performed in a LCC20 package which are more suited for DC and low frequency tuned-circuit experiments. This RF- PCB was mounted onto an immersion column then driven with ~4 m of cables with 50 Ω characteristic impedance each to the three terminals of the PFET. Once the device was measured at 300 K showing the characteristics in Fig. 2.7a, it was cooled to 4.2 K to obtain the measurements shown in Fig. 2.7b. As these were early experiments no decoupling capacitors were used on any of the fast switching gate and source lines.

27 2 – Characterization Experiments

(a)

(b)

Fig. 2.6 (a) Experimental setup for rise-time measurement and characterization of PSC 500 nm PFET. Only a PFET was measured due to limited time to MPR cut-off and based on the reasoning that a NFET would have a similar or faster rise-time. (b) The RF-PCB enclosure onto which the PFET-chip (the thin strip visible at the translucent center) was Al-wire-bonded.

28 2 – Characterization Experiments

(a)

(b)

Fig. 2.7 Extrapolated switching behavior and rise-time at (a) 300 K, and (b) 4.2 K, of the PSC 500 nm PFET wire-bonded to RF-PCB enclosure as shown in setup of Fig. 2.6.

29 2 – Characterization Experiments

One issue was, as evident from Fig. 2.7, the PFET tended to show highly under-damped ringing behavior. This was possibly due to parasitic inductance of the Al bonding-wire typically spanning about 5 mm in length which corresponds to about 5 nH (assuming 1 nH/mm typical for metal wires). This coupled with the device capacitances may have caused the ringing. However the ringing behavior was present even when the –2 V peak-to-peak drain-bias supply was disabled, which implied that the ringing was inherent to the setup rather than the device. I speculated that the device characteristics may be contained in the ringing data, hence performed an arithmetic subtraction between the data obtained with the drain-bias enabled and those obtained with the drain-bias disabled. These extrapolated results are shown in Fig. 2.7a for 300 K and Fig. 2.7b for 4.2 K, which show in the insets that the rise-time of the device is quite close to that expected from 300 K data and foundry data.

All device switching tests involving both PFET and NFET devices, showed a characteristic drooping time-constant as seen in the settling region of the curves in Fig. 2.7. Although not obvious at the time, after having completed tests on the first and second generation ICs, it is now clearly apparent that this time- constant was caused by a combination of the ON-resistance of the PFET, the line (cable) resistance and capacitance, highlighting the importance and significant of proper power-supply decoupling when there are fast switching elements involved, even if these elements are individual devices. The interested reader is referred to section 4.3.5 for evidence of this in action when the second generation control-pulse generator was being demonstrated at sub-K.

2.6 I(V) characteristics of n+-diffusion resistor

I also measured a 50/10 n+-diffusion resistor from the 500 nm process at 300 K and 4.2 K to verify the linearity characteristics of the n+-diffusion region and ohmic contacts between the metal electrodes and the diffusion region. As shown in Fig. 2.8, the conductance curve of the resistor was linear from 0–2 V at 4.2 K suggesting that the ohmic regions and n+-diffusion regions are sufficiently heavily-doped that at low temperatures they retain their ohmic

30 2 – Characterization Experiments

characteristics. This was an important finding as n+-diffusion resistors were very useful in serving several functions throughout the control-pulse generator designs such as introducing resistances (dampers) on the power-supply lines together with decoupling capacitors. They were further useful again as dampers in the input and output pad cells, as well as in ESD clamp cells associated with the pads, and especially in the ESD shunt cells. So the experimental confirmation in Fig. 2.8, of their ohmic operating range was very useful indeed.

0.8

0.6

4.2 K 0.4 (mA) I 300 K 0.2

−0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 V (V)

Fig. 2.8 DC response of 50/10 n+-diffusion resistor from 500 nm process at 300 K and 4.2 K. This reveals that the resistor retains its Ohmic characteristics thus is useful for low-temperature circuit design.

2.7 Transfer characteristics of a differential amplifier

This experiment with a differential amplifier (DA) was performed to test local device matching consistency in local FETs on the SOS substrate, and to show a large analog circuit in operation at cryogenic temperatures. This furthered my

31 2 – Characterization Experiments

understanding of the limitations of these devices for the purposes of this work as, at low temperatures, changes to output FET characteristics such as increased threshold voltage can produce vastly different response from device to device such as vastly different switching times that can result in jitter. This involved a voltage amplification test on a differential-pair, shown in Fig. 2.9, at 300 K and 4.2 K with a 2 V power-supply and a bias-current of 20±5% µA with the measurements shown in Fig. 2.10. This bias current was maintained throughout temperature cycling of this experiment from 300 K to 4.2 K and back to 300 K by setting VSET to 0.587 V for 300 K measurements, then adjusting VSET to 0.832 V in situ for 4.2 K measurements. The non-inverting terminal was kept constant at 1 V, while sweeping the inverting terminal about 1 V revealed the This showed that at low-temperatures device matching deteriorates significantly, as evident from the ~8% deviation of the 300 K transfer characteristics to those at 4.2 K in Fig. 2.10(inset). This test showed that device mismatch may be prevalent enough at low-temperatures to causes of pulse jitter in the mixed-mode first generation design, discussed in Chapter 3. On an unrelated note, this experiment also demonstrated the operation of a large analog circuit (a DA) in operation at low-temperatures which was an interesting proof-of-principle experiment in support of further experiments on cryogenic analog electronics.

2 V

50/0.5 50/0.5

Output Voltage

1 V 50/0.5 50/0.5 Input Voltage 10 uA 10 uA 20 uA VSET 100/0.5

GND

Fig. 2.9 Differential-amplifier (DA) fabricate in the PSC 500 nm process during the second MPR.

32 2 – Characterization Experiments

2.2 300 K 2 4.2 K

1.8

1.6

1.4

1.2 2 1 1.5 Output voltage (V) 0.8

1 0.6

0.5 0.4 0.9 0.95 1 1.05 1.1 1.15

0.2 0 0.5 1 1.5 2 Input voltage (V)

Fig. 2.10 Differential-pair test showing shift in I(V) characteristics as the chip is cooled from 300 K to 4.2 K. This is suggestive of mismatches in the transistors that may affect switching behavior at low-temperatures. This differential-pair was fabricated in the PSC 500 nm process.

2.8 Lightly-doped drains and contacts at low temperatures

The lightly-doped drain (LDD) structure is prevalent in most modern commercial MOSFET fabrication processes for technology nodes below 500 nm, inclusive. The LDD was originally designed to reduce hot-carrier effects (HCEs) [80]. Hot- carrier effects cause premature device degeneration, and occur when hot- carriers are generated at the overlap region between the gate and drain (or source) due to the intense electric field if the (n+-type or p+-type) contacts are metallically doped. The former causes physical damage to the gate oxide, and the latter causes hot-carrier induced punch-through (HCIP) [80]. A method to circumvent this issue in device scaling is to use LDD structures, which allow the applied electric field between the gate and drain (or source) to drop more

33 2 – Characterization Experiments

gradually reducing the probability of hot-carrier generation. This allows relatively higher applied drain (or source) voltages to be used thus enabling the MOSFET to operate at higher speeds as well as improving device lifetimes. Figure 2.12 shows a MOSFET without, and with LDD structures.

n+ n+ SiO2 SiO2 n+ n+ n+ nn++ p p

n+ n+

SiO2 SiO2 + – + p n n n p

(a) (b)

Fig. 2.11 The electric field in a (a) MOSFET without LDD structures may be high enough to generate hot-carriers that can cause impact ionization and avalanche breakdown in the oxide or hot-carrier induced punch-through (HCIP) in the substrate. The same MOSFET (b) with LDD structures increases the distance over which the electric field can distribute thus reducing the probability of hot-carrier generation. Note, in the figures, the size of the arrowheads represents the electric field strength, while the arrowhead density (electric field intensity) is constant, as should be.

There have been studies on the effects of LDD structures on MOSFET operation at 4.2 K [64], [79]. This investigates whether the LDD structures, which are now commonly added to MOSFETs with feature sizes ≤ 500 nm, would cause carrier freeze-out at 4.2 K. However there is contradictory accounts from previous investigations [64], [79], [80], that it is possible that the LDDs will not completely freeze-out. In fact, these reports seem to suggest that LDD structures can assist in reducing anomalies such as kink-effects in the drain-current of MOSFETs operated at 4.2 K [64], [79], while reducing HCEs thus dramatically improving device life times [80].

34 2 – Characterization Experiments

Another concern is the ohmic contacts – the interface between the metal electrode and the n+ (or p+) semiconductor junctions. It is possible that at low temperatures due to changes in the electrochemical potential of the materials the tunnel barrier formed between the electrode and semiconductor increases in potential. This along with the reduced electron temperature at low temperatures can cause non-linear effects to come into play at low drain-source voltages as at such voltages the electrons at the electrodes may not have enough energy to cross the barriers to get into the channel. These non-linear effects can be seen as a drain-current kink in the triode region of these MOSFETs.

2.9 Decision on the technology feasibility

The experiments in this chapter were performed to ascertain the feasibility of either of the PSC 500 nm and 250 nm nodes, for control-pulse generator design and implementation. The 250 nm devices showed better DC I(V) characteristics at low-temperature with less triode region non-linearity than the 500 nm devices. The 250 nm devices also were estimated by the foundry to exhibit rise- times as low as 20 ps. However the final deciding factor was the financial cost of taping out in the faster process. So a compromise had to be made by relaxing the rise-time constraints setout in [15]. Essentially, the 250 nm node with devices approaching 20 ps rise-times and better sub-K DC characteristics than those from 500 nm with 100 ps rise-time cost twice as much to fabricate with no other significant differences to offset against the expense. Hence it was clear that the 500 nm process sufficed for proof-of-principle designs.

Now, particularly on the 500 nm process, it was obvious the devices form this technology node had concerning characteristics at low-temperatures such as the triode-region non-linearity which had the potential to significantly reduce the settling-time of a switching circuit thus affecting its switching speed. The transient characteristics revealed that devices from this process were sufficiently fast at 100 ps rise-time for qubit control requirements. The increase in gain was not significant to affect current however this was factor that had to be considered during design as the resulting increase in current through each

35 2 – Characterization Experiments

device at low-temperatures directly project to increase in power dissipation for a chip made of hundred of these devices. The differential amplifier experiment showed that device matching deteriorated at low-temperatures possibly causing a contributing factor to jitter in mixed-mode and some digital circuits. The low- temperature mismatch was significant at an 8% deviation from 300 K transfer characteristics. However the DC and transient response characteristics were sufficiently favorable to consider proceeding with the technology. The transient response characteristics were especially critical in my decision process, as that experiment showed that a PFET (thus a NFET) would operate without significant deviation from its 300 K switching performance and characteristics which was extremely desirable, in contrast to what was commonly published in the literature about CMOS devices at low-temperatures. Hence the decision was finally made that it would be cost effective and feasible to fabricate the control-pulse generators in the PCS 500 nm UTSi process.

36 3 – First Generation Design

3 First Generation Design

3.1 Introduction

This chapter discusses the details of the first generation mixed-mode SOS- CMOS control circuit design. It elaborates on the details of the schematic and layout design, and offer justifications to the design decisions that were made. All FET aspect ratios (W/L) are in (µm/µm) unless stated otherwise, where W is the channel width and L is the channel length which is 0.5 for the 500 nm process.

3.2 Schematic and layout designs

3.2.1 Control-pulse generation concept

The control-pulse generator is fundamentally a digital circuit formed by a NAND- gate with an NOT-gate (inverter) connected to one of its input terminals and another NOT-gate to its output [78]. However its application in this thesis requires an output that is pulse-width controllable manually. This was achieved by replacing the inverters in the standard circuit with a current-starved inverter either single stage, as shown in Fig. 3.1, or cascaded multi-stage.

The standard design exploits the physical gate-delay of logic circuits to produce timed pulses [78]. The design in Fig. 3.1 provides an external control line to current-control the inverter(s) thereby slowing them down further, thus allowing a certain degree of duty-cycle controllability of the pulse. The timing diagram in

37 3 – First Generation Design

Fig. 3.1 Conceptual schematic diagram of first generation mixed-mode control-pulse generator.

Fig. 3.2 shows the timing flow. The Schmitt trigger produces a cleaned waveform which is fed into the NOT-gate. This NOT-gate has an inherent gate delay which can be used to generate a pulse when combined with the AND- gate as shown in Fig. 3.2. These schematics show how a pulse-width controlled pulse can be generated using standard cascaded logic, while the schematic capture in Fig. 3.3 is the gate-level implementation of these concepts.

The first approach was to develop a simple controller to minimize device count, which can contribute to reduction in power-dissipation. Low-power design is an important requirement for a qubit controller as dilution refrigerators in which sub-K temperatures necessary for qubits can be achieved, have limited cooling power. The refrigerators in our laboratory (Kelvinox K-100) can typically sustain 100 mK while maintaining a cooling power level of 100 µW. This sets the maximum power dissipation limit of the controller, while in operation in the dilution refrigerator. There is also a need to minimize power dissipation and coupling to the adjoining qubit chip which may deteriorate its performance due to thermal effects. Hence the first generation controller was based on an analog pulse-width control method, as explained above, although the pulse generation is performed using digital logic.

38 3 – First Generation Design

3.2.2 Control-pulse generator implementation

The first-generation control circuit was a full-custom mixed-mode voltage-pulse generator, the schematic diagram of which is shown in Fig. 3.3. The photomicrograph is shown in Fig. 3.4. In this design the delay element was a pair of cascaded current-starved inverters that act as delay elements. Essentially, there are two ways to control the delay of these inverters: a) increase their capacitance, b) reduce current through them. Cascading the inverters increases their capacitance while current-starving them increasing the delay through them at the expense of increased jitter. This also reduces their power dissipation however if the inverters are small in channel area, this reduction will not be significant relatively larger driver elsewhere in the circuit.

39 3 – First Generation Design

An analog input port allowed external control of current through the current- starved inverter structures using a controlled current source, which was a PFET device. Using this technique we have been able to demonstrate sub-10 ns pulse-widths and 100 ps rise times at 4.2 K [9], as shown in Fig. 3.9a. It is a relatively simple LSI circuit to reduce power dissipation to a practical minimum while maintaining gate-drive strength and low-temperature operation. However it enabled us to demonstrate that relatively sophisticated LSI circuits can be operated at sub-K temperatures. We also found that the pulse characteristics remain relatively unchanged during and after cool-down to sub-K temperatures, and that thermal cycling between 300 K and sub-K does not affect these characteristics.

This design dissipates ~16 µW at a repetition rate of 100 MHz, which is an encouraging result. Whilst low in power dissipation, it exhibited pulse jitter far higher than the order of the rise time, especially for longer dwell times. This was most likely due to noise on the analog input perturbing the output of the current- source based on its control characteristics producing an uncertainty in the current which strongly-couples to the switching times of the current-starved inverters. There is much literature about jitter-minimizing circuits such as jitter measurement circuits [81], anti-jitter circuits (AJCs) such as PLL and delay- locked loop (DLL), and studies on phase-noise and jitter in CMOS ring oscillator circuits [54]. However these have bias currents involved and at such early developmental stages the main focus of my effort was to demonstrate a fully- functional control-pulse generator operating at cryogenic temperatures. So AJCs have not been explored here, however they may offer good ideas to explore for future extensions of my work.

In this generation we intended to minimize on-chip capacitive loads on the output transistors by not including any ESD protection for the output pads and including weak-ESD protection for the input pads. This was due to uncertainty in operability of such an LSI circuit at the temperatures of interest to us. However as expected this made chips in this generation prone to ESD damage that compromised chip yield and reliability.

40 3 – First Generation Design

e VSS Vpuls VSS VSS 20/0.5 20/0.5 Vm2 Vm1 C2,m1 C3,m1 C2,m2 C3,m2 VDD VSS VDD VSS 10/0.5 C1,m1 C1,m2 1.4/0.5 2.0/0.5 4.5/0.5 10/0.5 2.0/0.5 4.5/0.5 1.4/0.5 1.4/0.5 1.4/0.5 2.0/0.5 1.4/0.5 1.4/0.5 1.4/0.5 1.4/0.5 2.0/0.5 2.0/0.5 1.4/0.5 VDD VSS 2.0/0.5 2.0/0.5 1.4/0.5 VDD VSS 1.4/0.5 1.4/0.5 Vm2 Vm1 VDD VSS ESDP ESDP ESDP 100R 100R 100R Vm1 VSS VDD Vm2 trigger Ddwell Vdwell

Fig. 3.3 The schematic design capture for layout generation. The ESD pad protection (ESDP) cells are also shown in the schematic. These are ESD-clamps with minimal protection. 41 3 – First Generation Design

Fig. 3.4 Photomicrograph of first generation control-pulse generator. Die area is 3 mm x 3 mm. The large fin-like structures are the decoupling capacitors (a Vm2 and Vm1 combined equivalent capacitance of 121.87 pF). Four versions of the same circuit were included and connected to the pad on the right: version 1 (connected to pad 2) has a 20 µm output NFET switch with a 50 Ω triple-microstrip transmission line, version 2 (connected to pad 5) is the same circuit without a transmission line, version 3 (connected to 7) has a 200 µm output NFET switch without a transmission line, version 4 (connected to 10) is the same circuit with a 50 Ω triple- microstrip transmission line. As visible, only ESD-clamps are present at the input and no ESD structures are present at the output. The structure at the top–center is a ring oscillator test structure with 501 stages. The test structures at the bottom-center looking clockwise from top- left are an inverter, the differential-pair in Fig. 2.9, the current-starved inverter structures for individual testing, and individual NFET and PFET devices.

42 3 – First Generation Design

30 25 20 Vtrigger 15 time (ns) Vpulse 10 IDD(VDD=2V) 5.0 Im2(Vm2=0.2V) 0 0 0 0

2.5 2.0 1.5 1.0 0.0 V (V) V

300 200 100 (V) V

10.0

−100 −200 −300

V (mV) V 1000 (mV) V

−10.0 I (mA) I 750.0 500.0 250.0 (mA) I

−250.0 −500.0 −750.0 I (uA) I Im1(Vm1=−0.2V) (uA) I

Fig. 3.5 Simulation results of the first generation control-pulse generator. The dwell-time setting voltage Vtdwell = 1.1 V in this simulation.

43 3 – First Generation Design

3.2.3 On-chip power-supply decoupling capacitors

It is apparent from the device experiments in Chapter 2 that lines (cables and wires) required to measure devices at 4.2 K and sub-K span longer than 4 m each way for inputs and output (when pulse must be measured with a DSO). If the lines are longer than a few millimeters any monolithic integrated circuit having fast switching devices such as digital gates requires at least internal (on- chip) power-supply decoupling capacitors simply because quite often the main power-supply has a time-constant that is too slow compared to those of the devices in these circuits. So in effect what the decoupling capacitors do is provide storage banks for “on-demand” charge to fast on-chip circuitry at a rate the main power-supply is too slow to provide. This requires both internal (on- chip) and external (off-chip) decoupling for proper wide-bandwidth decoupling. The circuit in Fig. 3.6a is a model of the experimental setup illustrating the distance and some approximations on the parasitic elements thus introduced. The introduced inductances due the combined D-connector wire and single- core wire (Lline) and the bond-wire (Lbond) can be estimated, from 1 nH/mm for metal wires, to be about 300 nH and 5 nH, respectively.

The impedance of the lines, from the above inductances, during the 100 ps rise- times of the control-pulse can be estimated to be

−9 2π 300⋅ 10  2πL ( )  ZLlinen(),2== jπ fL−12 18.85k t  tr 100⋅ 10  n = 1, 2 (3.1) −9  2πL 2510π ()⋅  Z() Lbond, n== j 2π ft L −12 0.314k  tr 100⋅ 10 

44 3 – First Generation Design

300 K 4.2 K 1.0 K sub−K setup wire 0.3 m bond wire 0.005 m coaxial cable 4 m

Control−Pulse Generator chip Qubit chip Rline2 Lline2 Lbond2

Vm2 Vpulse M2 Rterm2 50R Ced2 Cid2

Rterm1 Ced1 Cid1 Lbond3 50R M1 CL Vm1

Rline1 Lline1 Lbond1 4 m 0.3 m 0.005 m 0.003 m 0.005 m bond wire bond wire setup wire chip length coaxial cable (a)

Control−Pulse Generator chip Qubit chip

Vm2 t = 0 M2 Cid2 Vpulse

Cid1 Lbond3 M1 CL t = 0 Vm1

(b)

Fig. 3.6 (a) A model of the measurement setup for triggering and observing the control-pulse on a DSO/WBO with long coaxial cables (transmission lines), D-connectors, line wires, and bond wires manifesting significant delays for charge to be supplied on-demand at the controller chip solely by external power-supplies. This shows the significance of and undisputed need for internal and external decoupling capacitors positioned as close as possible to any IC with fast switching elements, but with a Faraday radius as in (3.10) below. Hence decoupling capacitors are needed for on-demand charge storage for ICs that reside beyond a Faraday radius from the power-supplies. The decoupling capacitors therefore play a critical for supplying the necessary charge on-demand.

which implies that at these speeds the charge supplied by the external voltage sources at 300 K is negligible. In other words, the control-pulse chip and any associated qubit-gate load chip can be assumed to be completely isolated from the voltage sources Vm2 and Vm1 as shown in the equivalent circuit in Fig. 3.6b, because the charge needed to drive the load capacitance has a lapse of time in arriving at the output FETS due to the finiteness of the speed of light: “the speed of light is just not fast enough”! At steady-state, before t = 0 the internal decoupling capacitors Cid2 and Cid1 will have charged to approximately Vm2 and Vm1 respectively, allowing some tolerance for error 45 3 – First Generation Design

due to the voltage drops in line resistances Rline2 and Rline1. The inductances would appear as short-circuits at this point in time. Therefore we can use the law of conservation of charge to calculate the required decoupling capacitance for a load capacitance of a qubit gate of 100 fF or thereof. Now with the above assumption of the voltages of Cid2 and Cid1

− Qt( ==0 ) Vmid22 C = Q id 2 (3.2) + Qt()==0 Vpulse() C id2 + C L and from charge conservation we know that

Qt==00+ V( C += C) Q + Q − ()pulse id22 L id L ( ) (3.3)

=+VCmidmL22 VC 1 thus the voltage at the Vpulse node is

VC+ VC VV==midmL22 1 ξ . (3.4) pulse CC+ m2 id2 L ξ =−()1 0.01 = 0.99

This, when rearranged, gives

VCmidmL22+= VC 1ξ V m 2( C idL 2 + C)

()1−=−ξξVCmid22 C L ( V m2 V m 1 )

CVLm()ξ 21− V m Cid 2 = (3.5) ()1− ξ Vm2 1 CVLm()21− 0.99 V m CVid 21= 99 ,m ~ 0 Vm2

CCid 2 = 99 L which is the minimum requirement. Thus the criterion for decoupling becomes

CCid 2 ≥ 99 L (3.6)

46 3 – First Generation Design

in order to provide sufficient decoupling to the load.

This indicates that the decoupling capacitors should be larger than or equal to say 100 times the designed load capacitance. As per the specification guidelines setout above, the typical load capacitance of a qubit gate could be about 0.1 pF allowing for an upper limit of 1 pF. Using the typical value we can design the decoupling capacitance to be about 10 pF, and using the upper limit it can be designed to be about 100 pF. So any on-chip decoupling capacitance larger than 100 pF will be sufficient for proper on-chip decoupling. In the design in Figs. 3.3 and 3.4, the on-chip equivalent capacitance seen at either Vm2 or Vm1 nodes was 121.87 pF which satisfied the 100 pF minimum limit. This was implemented by designing the Vm2 and Vm1 decoupling capacitors to be a combination of both MOS capacitors and MIM capacitors where C1,m2 = C2,m2 = 120 pF and C1,m1 = C2,m1 = 120 pF were MOS capacitors, and C3,m2 = 38.85 pF and C3,m1 = 38.85 pF were MIM capacitors. The stacking of C3 atop C2 in the process layers allows optimizing on area usage.

3.2.4 Output ringing due to fast pulse input feed-through

If a fast pulse arrives at the trigger input, such as a 30 ps sourced from the Anritsu, it produces feed-through ringing at the output. To analyze this we must consider the line resistance and switch capacitance.

As evident from Fig. 3.6a, if the capacitance seen by such a trigger pulse is that of the Schmitt trigger (Cst) and the input pad (Cpad) then the equivalent capacitance can be estimated. The Schmitt trigger has two NFET and two PFET devices at its input. Then its gate capacitance can be estimated as

CCWLWLst=+2 ox( nmos nmos pmos pmos ) =⋅2 3.63fF µm−2 () 1.4()() 0.5 + 2 0.5 () (3.7) =⋅3.4() 3.63fF µm−2 = 12fF 47 3 – First Generation Design

Now the pad capacitance Cpad can be assumed to be typically about 1 pF or higher, and the bond-wide inductance Lbond = Lbond1,2 = 5 nH for a typical bond-wire length of 5 mm (1 nH/mm for metal wires). Therefore it is obvious that the pad capacitance dominates thus determines the bandwidth of the input circuit. Thus the time constant of the dominant pole of that system can be estimated to be about

1 f0 = 2π LCbond() pad+ C ST 1 = . (3.8) 25n1012fFπ ()( ) = 2.24GHz

This indicates that the bandwidth of the input circuit is close to the gain- bandwidth product of this technology of 10 GHz, which implies that a 30 ps pulse (with a base-band of 33 GHz), which is of the same order of magnitude as the bandwidth in (3.8), will be partially attenuated and partially fed-through the chip system thus appearing in the output control-pulse signal.

Now there is no remedy for this effect other than to trigger the control-pulse generator with a slower Vtrigger (e.g. sinusoids, triangle waves, low rise-time square waves). This is in fact exactly the purpose of the control-pulse generator: use a relatively cheap slow rise-time trigger pulse to generate a qubit control-pulse in the picosecond rise-time scale at cryogenic temperatures.

3.3 ESD protection

This was the first attempt in the CQCT lab, where a complex integrated circuit was being designed, fabricated (in the PSA foundry), and tested at 4.2 K and sub-K for its characteristics and pulse performance. The lab specializes in single (stand-alone) device fabrication and characterization rather than complex circuits. There was no one having had done such a feat nor experienced

48 3 – First Generation Design

enough in both IC design, cryogenic measurement of such systems, and test bench preparation for experiments. Hence these were few of many related uncertainties dominating the first generation design including the ultimate operation of such a complex LSI system at cryogenic temperatures, relatively speaking, as there was no guarantee that a single device FET operation demonstrated in the previous chapter implied an LSI chip would operate at such low temperatures too. In anticipation of these uncertainties and limitations, and to maximize the chances of operation of the chip, my design approach had to ensure that the design was as simple with only bare necessities included. Although such scenarios can be simulated in Cadence®, there was no certainty that the IC would work in practice in the conditions it was required to work. This meant compromising on ESD protection circuitry as we had no indication of how the circuit would behave at low temperatures, with extra loads from the ESD circuits on the input and output pads. The focus, especially, was to avoid extra loads on the control-pulse output pad to maximize the chances of the pulses being produced with fast rise-time characteristics. Also power dissipation, although was reasonably estimated from simulations, was an uncertain factor as the circuit could behave unpredictably dissipating more power in certain regions of operation and at certain temperatures that could lead to exceeding the dilution refrigerator’s cooling power limit. Therefore only ESD FET-diode clamp circuits (explained in full detail in Chapter 4) were included at the input pads and no protection at all was included at the output pads, as shown in Fig. 3.7. Refer Chapter 4 for more information on ESD protection, as proper protection circuits were used in the second generation. After fabrication, it was found that this was a significant reason for low chip yield and chip deterioration during operation. There were several chips that had to be tested and changed during experiments. Rigorous repeated tests revealed the possibility of ESD occurring anywhere in the handling processes from the foundry (fabrication, handling, scribing, or transport), to in-house general handling during testing, could have caused damage to the now highly ESD-susceptible chips. Following experimental verification of the behavior of the first chips that were tested, this early hypothesis developed in to a definite confirmation. An immediate decision was made to rectify this in the second design.

49 3 – First Generation Design

VDD

ESD Current 360/0.5

100R To Internal Circuitry To Internal Circuitry Input Pad Output Pad

200/0.5

VSS

Fig. 3.7 The input clamp cell included at each input pad, with no output protection at each output pad. A decision that had to be made due to many uncertainties, leading to risking the ESD-susceptibility of the chip to maximize chances of observing a fast rise-time pulse output.

3.4 Transmission-line design

The output FETs of this pulse generator produce signals up to 10 GHz in bandwidth, based on the experimental estimation of the unity-gain bandwidth

(ft ~ 1/tr) of these devices from Chapter 2. This obviously poses RF issues during design. Typically the fast pulses travel along metal interconnects on-chip and connect to a pad, from which it is carried along a metal wire-bond to a pad and another metal interconnect to a qubit gate or measuring instrument.

This requires some RF analysis to determine antenna effects. The most likely method to increase impedance matching in a discontinuous signal path is to design transmission lines tuned to the source resistance (ON-resistance) of the FETs that produce the signals. In this thesis a switch in the generator drives a qubit-gate load via a chip-to-chip bond wire. This signal has several impedance discontinuities which may cause reflections. These can be avoided if the signal path can be kept within a distance called the “Faraday shield radius”. If the distance from pulse output to qubit is longer than this length, matched- transmission lines have to be used to avoid reflections.

The Faraday shield radius can be derived from the relativistic equation

50 3 – First Generation Design

1 v =

εµ 27− ,,εεεε==r 00c µ 0 ,410 µ 0 =⋅ π v ∴λreflection==tv r (3.9) ft λ ∴L ≤ reflection termination 4 where Ltermination is the minimum signal propagation length before reflections occur [82], [83]. This gives a length limit to which normal metal interconnects can be used beyond which transmission lines have to be used.

Making the assumption that the silicon dioxide (SiO2) layer of the SOI wafer appears to signals as the dominant base of the microstrips, εr = 3.9 and µr = 1. Therefore, using the pulse bandwidth of the FETs of this process measured in Chapter 2, we can estimate the length

1 v ==⋅151.8 1061 ms− 3.9εµ00

∴λreflection==tv r ()100ps v = 15.18mm (3.10)

∴Ltermination ≤ 3.8mm as the termination limit beyond which this design requires transmission lines.

The type of transmission line investigated was the simple triple-microstrip coplanar transmission line which has two ground strips adjacent to a central signal strip. This triple-microstrip transmission line was designed using a set of trigonometric equations [82], [83] for the characteristic impedance

  η 1 Z = 0  (3.11a) 0 4 ε 1 t eff + fk k, k ' ba− ()11

cb22− a k = (3.11b) 1 bac22−

51 3 – First Generation Design

πππcba22   sinh sinh − sinh  444hhh   k2 = (3.11c) πππbca22   sinh sinh − sinh  444hhh  

'2 kknnn=−1,1,2 = (3.11d)

1 ' ()ε −1 fkkk ()22, ε =+1 r  (3.11e) eff 2 1 t + fkk, ' ba− k ()22

µ0 η0 = (3.11f) ε r ε0

and the elliptic function fk(k, k’) in the above equations defined as [82]

 114++kk4  ln 2 ,ifffk=∞ 0, , = 1 ,1 4 k []  2  Kk() 2π 14+−kk ∀∈()kk,', fkk : f () kk ,' =≅ Kk()'  114++kk4 ln 2 ,ifffk== 0,1 , 0, 1   4 k []  2   2π 14+−kk (3.11g) where a, b, c, and h are dimensions shown in Fig. 3.8.

The matching conditions were a characteristic impedance Z0 = 50 Ω at a strip height h = 0.5 µm to encourage matching to source impedance. However reflections are inevitable depending on the type of measurement on the control- pulse output through the transmission lines. For instance, waveform measurement equipment such as digital storage oscilloscopes typically have input impedance of 50 Ω, while when bonded directly to the qubit fast-line gate pad the driven gate poses an open-circuit load. However the intension in designing the transmission line about the 50 Ω characteristic impedance region was to minimize the possibility of reflections when the control-pulse was being measured and characterized inevitably with measurement equipment, as above.

52 3 – First Generation Design

t a b h c

Fig. 3.8 The triple-microstrip transmission line model used in equation set in (3.11).

3.5 Experimental results at 300 K, 4.2 K, and sub-K

The operation of the controller at 4.2 K is shown in Fig. 3.9, clearly indicating the 100 ps rise time and pulse-width. The results are very similar at 300 K and sub-K. The low peak-to-peak voltage results from the measurement-dependent voltage division that occurs between the on-resistance of the output FETs and the input impedance of the wide-band digital storage oscilloscope (WBO). A WBO was necessary to minimize band-limiting the fast control-pulse during measurement. This first generation controller fabricated with ~100 individual transistors, shows that it operates with desirable results at 4.2 K and sub-K temperatures as shown in Fig. 3.9 and Fig. 3.10, regardless of its relative complexity and high device count.

Fig. 3.10 shows power-to-frequency measurements performed at 300 K (top), 4.2 K (top), and sub-K (bottom) temperatures to ascertain the degree of heating caused by the power dissipated by the controller in the cold-stage of the dilution refrigerator where the qubit sample would most likely be positioned. The power- to-frequency curve of the controller shows a linear relationship, as expected for switching circuits with no bias currents.

53 3 – First Generation Design

−2

Voltage (mV) −4

−6

4.2 K −8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ns)

(a)

−2 Voltage (mV) −4

−6 4.2 K −8 0 1 2 3 4 5 6 7 8 9 10 Time (ns)

(b)

Fig. 3.9 (a) The first control-pulse generator rise-time of 100 ps at 4.2 K, and (b) the pulse-width when Vdwell = 1.2 V showing the jitter on the falling-edge.

54 3 – First Generation Design

The sub-K results also have included measurements made using a ruthenium oxide (RuO2) thermometer positioned close to the controller (sample) and compared to the mixing chamber (MC) temperature of the dilution refrigerator.

There is additional heat-load from the many signal and control lines supplied to the chip. The effect of this heat-load on the base temperature of the refrigerator is visible in the sub-K temperature-to-frequency curve in Fig. 3.10, where the base temperature is at ~160 mK. These results show correlation of temperature rise to switching frequency (repetition rate) of the control-pulse measured. The sample is warmer than the MC due to the inability to perfectly heat-sink the controller chip to the MC. This is due to limitation in the amount of thermal- coupling possible from the chip to the RF-PCB enclosure system. If the chip is not adequately thermally anchored to the cold-stage, the heat will not be extracted from the chip at the cooling power of the refrigerator, hence the base temperature will be higher than usual (~30-70 mK). These low temperature experiments and measurements provided us with the means to identify design issues in the first generation that were insightful in designing the second generation controller.

The critical issue we identified was the analog pulse-width control mechanism using current-controlled inverters was noisy, affecting the temporal stability of the falling-edge of the pulse producing significant jitter (phase noise) that is well-known to be undesirable for qubit control. This is visible in the control-pulse in Fig. 3.9b produced when the analog input Vdwell = 1.2 V. From observation of the control-pulse in Fig. 3.9b, the measured pulse-width is approximately between 4.25 ns and 5.75 ns while the mean pulse-width is ~4.75 ns. Thus the pulse-width spread, or jitter, is approximately 1.5 ns or ~30%. Assuming this jitter is Gaussian-distributed with a six-sigma (6σ) spread, its standard deviation (σ) would be in the order of 1.5 ns/6 = 250 ps for the particular pulse in Fig. 3.9b. However the falling-edge showed significantly reduced jitter when the analog pulse-width control circuit was not in use. So it is reasonable to deduce that the FETs in the current-starved inverter circuit were the cause of the jitter.

55 3 – First Generation Design

15 W)

µ 10

5 Power ( 0 0 20 40 60 80 100

400 Sample Mixing Chamber

200

Temperature (mK) 0 0 20 40 60 80 100 Frequency (MHz)

Fig. 3.10 Power-to-frequency curves at 300 K, 4.2 K (top), sub-K (middle), showing linear behavior for varying pulse frequency (repetition rates), and the related temperature rise (bottom) at the sample and in the mixing chamber, for sub-K measurements in the dilution refrigerator.

Based on this and the well-known fact about manufacturing process accuracies, we concluded that the analog components were the cause of this jitter. Further, the higher pulse-widths (≥ 500 ps), as shown in Fig. 3.9b, suffer from higher 56 3 – First Generation Design

jitter additionally due to the intrinsically non-linear characteristics of the FETs during current-controlling as they move through their non-linear regions during from cut-off through saturation to triode regions and vice versa. We also believe from 300 K and cryogenic experiments that although the lower power dissipation in the analog design allowed for higher switching frequencies within the cooling power limit of the dilution refrigerator, it was too susceptible to voltage-pulse jitter most likely further accentuated by noise coupling from the analog input. However we decided that that the jitter was too significant an issue to solve within the same circuit topology. Hence we decided that the only way we could solve the jitter issue was to use an external and/or internal timing reference for controlling the pulse-width. This resulted in a shift in design paradigm of pulse-width control from analog to digital. Hence our second generation controller was based completely on digital logic and registers for pulse-width control. This meant that the pulse-width would be limited to the resolution set by the word length of the registers with simulations showing the minimum possible pulse-width, for a 16-bit word length, being about 2 ns before this particular process technology reaches its switching frequency limit. We have countered this limitation by facilitating for an external clock input that can be fed from a local quartz crystal or other source. We have yet to investigate whether quartz crystals can operate with sufficiently high oscillations for RF- CMOS clocking at cryogenic and lower temperatures.

Transmission of the 100 ps control-pulse was not affected by measurement setup. However we designed variants of the first generation controller with on- chip metal-strip transmission lines for pulses traveling beyond the Faraday shield radius for Si of ~2.2 mm: this was calculated for the above rise time. Any pulse signals traveling beyond this radius were transmitted through coaxial cables or metal-strip transmission lines.

Intentionally left void

58 4 – Second Generation Design

4 Second Generation Design

4.1 Introduction

This chapter discusses the details of the second generation full-digital SOS- CMOS control circuit design. It elaborates on the details of the schematic and layout design, and offer justifications to the design decisions that were made.

4.2 Schematic and Layout designs

4.2.1 Control-pulse generation concept

The second generation schematic design process involved addressing the issues of the first generation design that were learnt from experiments on it, namely jitter and ESD protection. I commenced by conjuring different circuits that can be used to generate rapid pulses but with precise control over the pulse-width (dwell time). The most practical method given the limited time to send the Cadence® GDS-II files to the foundry was to use a clocked counter for precise timing.

The conceptual schematic diagram in Fig. 4.1 describes the second generation control-pulse circuit design at an abstract level. Initially, the trigger is set to “LO” which closes the data path to the counter. The data is, then, sequentially fed-in to the counter. Once the counter is loaded the data stream is stopped, and the trigger is set to “HI” which simultaneously isolates the data path from the counter register allowing the counter to count. At the moment the trigger is set

59 4 – Second Generation Design

“HI” the NAND-gate produces a logic “HI” output and the counter commences counting until it reaches “zero”. This “zero” output from the counter acts as a flag to trigger the NAND-gate to produce a logic “LO” at its output. The control- pulse is the output of the NAND-gate. The subsequent inverters are cascaded in increasing driving strengths to act as a “super-buffer” to boost the control- pulse output from the NAND-gate so that it can be interfaced to larger external (off-chip) loads such as a qubit gate, being capable of driving typical loads of around 100 fF to 1 pF.

VDD Vm2

Vtrigger Vpulse

COUNTER DATA

VSS Vm1

Fig. 4.1 Conceptual schematic diagram of second generation full-digital control-pulse generator.

4.2.2 Control-pulse generator implementation

The complete gate-level schematic of the full-custom full-digital control-pulse generator is captured in Fig. 4.2, which is an instantiation of the concept in Fig. 4.1. The photomicrograph is shown in Fig. 4.3. Starting from transistor-gate level cell-blocks were implemented by composing individual devices to make logic-gates and other functional blocks [84], [85]. These were individually tested through simulations before integrating into the higher level blocks and finally the final chip level cell-blocks. This second generation design has several improvements made to address issues identified in the first generation. This design was based on the same standard-logic pulse-delay principle as in the first generation with the delay element replaced with a clocked ripple-counter 60 4 – Second Generation Design

that flags when to stop the pulse. The entire structure is based on a logic enabled load-count mechanism based on the logic level of a trigger pulse as follows:

1. the Vtrigger signal is set LO and RESET and SET lines are set HI to put the shift register and ripple counter into load-mode, 2. the dwell-time of the control-pulse is set by a control-word between 0×0000 and 0×FFFF streamed into the 16-bit shift register via a two-wire synchronous serial port, 3. the sequentially sent control-word gets loaded onto the counter in situ from the register via loading logic, 4. if the register/counter contents is non-zero the AND-gate output flags HI, the counter clock enters ready-mode, 5. once the register is loaded the serial lines are set LO, 6. the Vtrigger is set HI selecting count-mode, 7. the control-pulse is set output HI, the clock is enabled, and the counter starts processing: counting from the control-word down to zero, 8. once the counter reaches zero or the Vtrigger is set LO whichever occurs first, the control-pulse is set output LO and clock is disabled, 9. the same control-pulse can be regenerated periodically, by setting the Vtrigger frequency to a desired repetition rate, 10. the dwell-time of the control-pulse can be set to another value by repeating the process from step 1).

I designed two versions: one with a dedicated internal ring oscillator, and one with provision for an external clock feed-in (perhaps from a crystal resonator). The latter allows testing this circuit at faster clocking speeds up to dwell-times that span few rise-times. This frequency is ultimately limited by physical characteristics of the silicon process. Most importantly, jitter is now process- limited to the order of the rise time, a significant improvement from the first generation. In addition, increased ESD protection to all pads of the wafer dramatically improved chip yield and reliability. The shortest dwell time for this design was limited to 8.15 ns, corresponding to 2 clock periods (control-word of

61 4 – Second Generation Design

0×0002) as the least-significant bit (LSB) is ignored during the counter output processing. This avoids counter-wrapping from delays in the logic stages. Therefore setting the control-word to 0×0000 or 0×0001 has the same effect as setting it to 0×FFFF as this will cause counter wrap-around to produce the longest pulse possible. Additionally, a D-flip-flop was used to latch its state once it reached zero in order to force the clock into disabled-mode, in case the propagation delay of the entire circuit lets the clock wrap the counter around. This was an important consideration to avoid the control-pulse restarting while Vtrigger was HI. Finally, a combinational-logic circuit (15-bit OR-gate) determines whether the counter has reached it zero-state. The output from this OR-gate forms the inputs to both the clock-enable and the pulse-generating AND-gate, as shown in Fig. 4.2. Measurement results are discussed in section 4.3.2.

The ESD protection circuits improved the chip yield of this generation dramatically relative to the previous generation. The main ESD protection circuit was a large FET-clamp on the main power supply metal (i.e. VDD, and VSS), which was designed using the standard 3 kV–2 A human-body model corresponding to a 1.5 kΩ source resistance. The purpose of this large FET- clamp was to act as a low-resistance current path through which an ESD- current can flow and dissipate its energy during an ESD event. Inclusion of diode-connected FET-clamps on all inputs and outputs, and the inclusion of this FET-clamp on the power–supply rails dramatically increased the chip yield. This will be covered in more detail in section 4.2.7 below.

All power-supply metal in METAL1, METAL2, and METAL_THICK (METAL3) were redesigned to 50 µm width, as opposed to 20 µm in the first design. This was with allowance for larger operating currents and ESD currents to flow through the metal. All signal lines were made 2 µm, as opposed to 1 µm in the first design. The increased surface area was advantageous in the power-supply metal layers as the stray capacitance would add to decoupling capacitance, while routing widths had to be kept under strict control in the signal lines to minimize stray capacitance as these would add to signal propagation delay.

62 4 – Second Generation Design

e VSS VSS Vpuls ESDPO 20/0.5 20/0.5 Vm2 Vm1 C2,m1 C3,m1 C2,m2 C3,m2 VDD VDD VSS VSS C1,m1 C1,m2 4.5/0.5 10/0.5 VDD VSS 2.0/0.5 4.5/0.5 10/0.5 1.4/0.5 1.4/0.5 1.4/0.5 R VDD S DQ VSS C0 C9 C8 C7 C6 C5 C4 C3 C2 C1 C15 C14 C13 C12 C11 C10 Q15: Q0 Ripple− Counter CLK LD/CNT Q15: Q0 CLK Q15: Q0 Q15: Q0 Ring− Oscillator EN Shift− Register S SRDATA R SRCLK 1.4/0.5 1.4/0.5 1.4/0.5 1.4/0.5 1.4/0.5 Vm2 Vm1 VDD VSS ESDPI ESDPI ESDPI ESDPI ESDPI 100R 100R 100R SET VDD Vm2 Vm1 VSS RESET Vtrigger REG_CLK EG_DATA

Fig. 4.2 The schematic design capture for layout generation. The ESD pad protection (ESDPI for input and ESDPO output) cells are also shown in the schematic. 63 4 – Second Generation Design

Fig. 4.3 Photomicrograph of second generation control-pulse generator. Die area is 3 mm x 3 mm. The internally clocked version is the large structure on the top, and the externally clocked version at the bottom. The first generation block was also included as visible in the middle of the chip for further testing and investigation. That circuit now has ESD-shunt protection on its power-supply lines. The ESD-shunt structures are present where there are two visible METAL_THICK top-caps of the corresponding MIM-capacitors. In the structure at the top these top-caps are visible just under the power-supply pads at the center-top region of the chip. The structure at the left-bottom is a ring-oscillator (RO) identical to that included in the first generation design, however now with the ESD-shunt protection visible just above the two power-supply pads of the RO. The structure at the left-top is a collection of NFETs and PFETs for individual device characterization. The structure at the left-middle just adjacent to the RO power-supply pads is a large inverter (NOT-gate).

64 4 – Second Generation Design

100 RO:CLK 75.0 Vtrigger REG_DATA 50.0 46.9ns 46.9ns 46.9ns 46.9ns46.9ns time (ns) REG_CLK 42.1ns 42.1ns 42.1ns 42.1ns42.1ns 25.0 Im1(Vm1=−0.2V) Im2(Vm2=0.2V) 0

2 1 0 0 0

−1 −2 −3 −4 I (mA) I

I (mA) I −.5 2.5 2.0 1.5 1.0 V (V) V

125 (V) V 300 200 100

25.0

−100 −200 −300 V (mV) V

−75.0 (mV) V I (uA) I IDD(VDD=2V) Vpulse (uA) I

Fig. 4.4 Simulation results of the second generation control-pulse generator. The control-word is 0×0002 to produce the shortest pulse-width possible with this design.

65 4 – Second Generation Design

4.2.3 Shift-register (16-bit) design

The simulated clocking frequency possible for the on-chip oscillator, discussed below, showed that the duration of a pulse would be limited to about 2.0 ns. This is not in direct agreement with the measured value of 8.15 ns as mentioned above; however it is in the same order of magnitude and significantly distant from the measurement value. The clocking frequency however could be sped-up using the external oscillator feed-in pad, limited by the gain-bandwidth product of the process, of course. So the period of any pulse can be varied depending on the oscillator frequency used. This urged me to develop the register to allow sufficient resolution to produce short pulses as well as long pulses. Hence I decided that a 16-bit sequential synchronous edge-triggered flip-flop based register is sufficient for practical considerations and has a low enough device count for inclusion in this control-pulse generator. Once the register is loaded the control-word is retained throughout the experiment for any repetition rate set using the Vtrigger of the chip, until it is either over-written by a newly sent control-word, or set/reset by pulling the set/reset pads LO.

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

CLK

D Q D Q D Q D Q D Q D Q D Q D Q

S S S S S S S S R Q R Q R Q R Q R Q R Q R Q R Q

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Fig. 4.5 The schematic of the positive-edge triggered 8-bit sequential synchronous flip-flop based shift register cell for control-word load and store with logic-LO set and logic-LO reset. The 16-bit register was designed by cascading two of these 8-bit register cells. Once the register is loaded the control-word is retained throughout the experiment for any repetition rate of the Vtrigger signal.

66 4 – Second Generation Design

4.2.4 Ring oscillator design

A ring oscillator (RO) is a simple high-Q circuit that would allow low-power dissipation while generating a fast internal clock signal. As it is critical to keep the power dissipation to a practical minimum, I decided to use a buffered-RO structure the schematic of which is shown in Fig. 4.6. The RO is constructed of an odd number of cascading base inverters with a super-buffer stage buffering the output from the feedback node. If not designed properly, the RO could be the most power consuming element designed to typically operate at about 368 MHz. Hence it was paramount that the RO be designed with the lowest FET widths allowable by PSC design rules (1.4/0.5), and maintaining interconnect lengths between devices and adjoining cells as thin and short as possible in the layout to keep parasitic line-capacitances to the physical minimum. This helps to reduce stray power dissipation in the clocking circuit.

1.4/0.5 1.4/0.5 1.4/0.5 1.4/0.5 1.4/0.5 2.0/0.5

CLK EN

Fig. 4.6 The buffered ring oscillator schematic design.

4.2.5 Ripple-counter design

Initially, I considered several counter designs so that a suitable design could be selected after consideration and analysis. Amongst the selection were a ripple counter, gray-code counter, and binary-coded-decimal (BCD) counter [78]. The reason the gray-code counter design was considered was because in such a design only one bit flip occurs at any given timing event (clock-edge). The counter would be the second most power consuming element after the RO as it will inevitably have memory elements, namely flip-flops, switching for each bit- flip at each rising (or falling) clock-edge. Hence after much analysis and simulations of few-bit gray-code and BCD designs, I deduced that the ripple counter sufficed with a power consumption somewhat similar to that of a gray- code counter and simplicity of design, although it would reach its maximum 67 4 – Second Generation Design

power consumption at carry-bit flip events such as for example during switching from 0×0007 (0111b) to 0×0008 (1000b).

C0 C1 C2 C3 C4 C5 C6 C7

D Q D Q D Q D Q D Q D Q D Q D Q CLK

S S S S S S S S R Q R Q R Q R Q R Q R Q R Q R Q

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LD/CNT

Fig. 4.7 The ripple counter schematic design.

I also had to deduce on the resolution of the counter which would define how accurately the pulse widths can be controlled. After much analysis and iteration, I decided that to achieve sufficient resolution at least a 14- to 16-bit counter would be necessary, and adding more than necessary bits may cause too much power dissipation at carry-bit flip events. Hence the resolution of the counter was set to 16-bits. The schematic of this 16-bit ripple counter is shown in Fig. 4.7.

4.2.6 Positive-edge triggered D-type flip-flop

The fundamental operational cell of the register and counter is the positive-edge triggered D-type flip-flip. It is the essential component throughout the second generation chip including the latch that remembers the state of the counter when it counts down to two (“2”), thus stopping the clock before the counter reaches zero (“0”) preventing wrap-around due to propagation delay in the relatively large clocking circuit.

68 4 – Second Generation Design

1.4/0.5 1.4/0.5 CLK 1.4/0.5 1.4/0.5 Q D

S CLK 1.4/0.5 1.4/0.5 Q R

1.4/0.5 1.4/0.5 1.4/0.5

(a)

(b)

Fig. 4.8 The (a) schematic and (b) layout designs of the positive-edge triggered D-type flip-flop register. 69 4 – Second Generation Design

The memory element used for each bit is an edge-triggered D-type flip-flop as shown in Fig. 4.8 with set and reset inputs to allow for semi-asynchronous set/reset functionality. This is necessary as in order for the counter to successively propagate (ripple) its bits, it should be edge-triggered by the clock input.

R CLK D Q Q D CLK Q CLK S CLK

CLK CLK CLK S Q

Fig. 4.9 The level-triggered D-type flip-flop schematic.

Hence edge-triggering was implemented by two cascaded level-triggered D- type flip-flops shown in Fig. 4.9. The resulting edge-triggered D-type flip-flop design is semi-asynchronous design as the first-stage level-triggered D-type flip-flop sets/resets when the set or reset inputs are pulled-LO, mutually exclusively, the second-stage D-type flip-flop requires a clock-edge to arrive before setting or resetting its output. However simulations showed that this method sufficed and these have been verified by post-fabrication experiments.

4.2.7 Super-Buffer design

The pulse output of the NAND-gate, in Fig. 4.2, is the duty-cycle (dwell time) controlled pulse that is can be used to drive a qubit. However qubit gate loads can range from 100 fF to 1 pF. The control circuit must also drive larger loads such as coaxial cables during characterization and testing. This requires the integration of a super-buffer [78], [86], [87] as in Fig. 4.2, to the output node of the NAND-gate that acts as a large-load driver between the "control-pulse" producing NAND-gate and the output FETs. This super-buffer is a series of cascaded inverters with increasing load-drive capability with each successive 70 4 – Second Generation Design

stage with the last stage driving a NFET-gate of width WN and length LN. Thus the succession-multiplier ψ of a N-stage super-buffer can be evaluated as

1 N ψ = ()WN (4.1)

WWnNnn+1 =ψ ,0,=∈[ ] (4.2)

where W0 = 1.4 µm and Ln = 0.5 µm for the 500 nm ultra-thin Si process [7] used to implement this design. So for instance a three-stage super-buffer with three stages consisting of an output FET that is a 20.0/0.5 NFET will have M = 2.68. Thus using the lowest practical sizes for the NAND-gate we can start from a 1.4/0.5 NFET for the NAND-gate, then the first super-buffer inverter can have a 2.0/0.5 NFET, the next inverter can have a 3.6/0.5 NFET, the next inverter can have a 10.0/0.5 NFET, and the output FET can be a 20.0/0.5 NFET. In the first-stage of the super-buffer, I have placed a 1.4/0.5 transmission gate connected to the power rails VDD and VSS (permanently turned-ON) to induce sufficient propagation delay to compensate for the propagation delay in the inverter below it. This formula has been known to produce the fastest rise times for the least power consumption.

4.2.8 ESD protection design

The second generation chip was designed with proper ESD protection circuitry capable of withstanding ESD from the 3 kV-2 A standard human-body model [88].

1.5k

150pF 3kV 2A ESD Current Control−Pulse Generator 225ns time constant

Fig. 4.10 An electrostatic discharge (ESD) event from the 3 kV-2 A standard human-body model [88] to the chip.

71 4 – Second Generation Design

An ESD event can occur from the standard model as shown in Fig. 4.10, where a user charged up to 3 kV discharges through a 1.5 k body resistance producing a 2 A ESD current.

I designed standard FET-based diode-clamps for each input pad (that drives a gate in an internal cell) and similar but weaker diode-clamps for all output pads to ensure all input/output pads on the chip were protected. The weaker clamp was designed to reduce the capacitive loading on the output transistors of the pulse generator circuit, yet maintain sufficient ESD-protection on its output pad.

This ESD-protection was implemented for the entire chip by including instances of the input clamp cell as shown in Fig. 4.11 at each input pad, instances of the output clamp cell at each output pad, and the bidirectional ESD shunt circuit [89] (also known as ESD craw-bar circuit or ESD power-clamp) between the power-supply metal/nodes (VDD and VSS). The position of the ESD shunt is not critical, so it was physically laid out closer to the power-supply pads.

VDD

30/0.5 ESD Current 40/0.5 ESD CLAMP ESD CLAMP ESD SHUNT 100R To Internal Circuitry To Internal Circuitry Input Pad Output Pad

ESD CLAMP ESD CLAMP

ESD Current 40/0.5 30/0.5

VSS

Fig. 4.11 The input clamp cell included at each input pad (ESDPI), output clamp cell included at each output pad (ESDPO), and the bidirectional ESD shunt [89] cell included between the power-supply nodes closer to the power-supply (VDD and VSS) pads.

The ESD shunt in Fig. 4.11 schematically is implemented as shown in Fig. 4.12, in which the primary protecting device is a large NFET acting as a low- resistance current path (shunt switch) through which any ESD current can flow and dissipate its energy. In an ESD event as illustrated in Fig. 4.10, the ESD

72 4 – Second Generation Design

current flows from the human-body source through to the 200 kΩ-1.5 pF RC- network pulling the VDD line high or the VSS line low. As the standard human- body model time constant, of 225 ns, is shorter than the charging time constant of the 1.5 pF MIM-capacitor the shunt FET stays on for long enough to allow the ESD current to flow, producing an impulse response shown in Fig. 4.16. However the time-constant of the shunt cell must be designed to last longer than that of the human-body model, so that the shunt circuit remains on for longer than the ESD source time-constant allowing the dissipation of all the ESD energy through the shunting NFET. The inverter is used to buffer the NFET from the RC-network. This RC time-constant was designed by assuming a 2 A ESD pulse from the human-body standard model with say a 200 mArms effective value. Allowing a long charging-discharging time of the MIM-capacitor, I estimated that τ = 300 ns is sufficiently large enough to satisfy the τ ≥ 225 ns time-constant requirement and to accommodate for the practical size limitations of the MIM-capacitor on-chip. Picking the above mentioned 1.5 pF capacitance for the MIM-capacitor we can arrive at the 200 kΩ resistance for the n+-diffusion –2 resistor. Using the MOSFET equations, and given that µCox ~ 100 mA·V from the PSC PDK, VDD = 2 V, we have

WmII200 ≥===DD 500 . (4.3) LC2 µµV22100⋅ 2 µCVox() GS− V t ox DS

Hence arbitrarily letting W/L = 800 to allow enough tolerance for the chip to sustain such a current, and noting that the 500 nm process sets L = 0.5 µm, we get W = 400 µm. This was also a good approximation to allow for the size limitations of the routing real-estate available on-chip. This was shown in simulations (Fig. 4.16) to perform sufficiently well, and subsequent experiments after the chip was fabricated and delivered showed it was significantly effective in protecting the chip from ESD damage. Throughout all experiments only a single chip was needed from a MPR supply of 130 chips: although expected a significant result in itself relative to what was seen in the first generation.

73 4 – Second Generation Design

The schematic in Fig. 4.12 was implemented in Cadence® as shown in Fig. 4.13(a) below. Figs. 4.14 and 4.15 show the input-pad cell ESD protection circuit (shown as ESDPI in Fig. 4.2) and the output-pad cell ESD protection circuit (shown as ESDPO in Fig. 4.2).

VDD

50/0.5 200k

V ESD SHUNT

400/0.5

1.5pF 50/0.5

VSS

Fig. 4.12 The schematic design of the ESD shunt circuit.

(a)

(b)

Fig. 4.13 The MOS-diode based power-supply ESD shunt for dissipation of ESD currents and voltages, (a) schematic, (b) layout designs. Design based on a 3 kV–2 A human-body model.

74 4 – Second Generation Design

(a)

(b)

Fig. 4.14 The MOS-diode based input pad ESD clamp, (a) schematic, (b) layout designs for steering ESD current and voltages to the ESD shunt in Fig. 4.12.

(a)

’ (b)

75 4 – Second Generation Design

Fig. 4.15 The MOS-diode based output pad ESD clamp, (a) schematic, (b) layout designs for steering ESD current and voltages to the ESD shunt in Fig. 4.12.

(a)

76 4 – Second Generation Design

10.0 7.5 5.0 time (us) 2.5 IESD VDD Vtrigger 0 6 5 4 3 2 1

60 50 40 30 20 10

0.0 0.0 0.0 V (V) (V) V V V (V) V

600 500 400 300 200 100 (V) V V (V) V

V (V) V 50.0 VESD −150 −350 I (mA) I

I (mA) I (b)

Fig. 4.16 (a) An ESD simulation setup and (b) simulation results with a 500 V ESD spike entering the Vtrigger pad, through a 100 pF-1.5 kΩ standard human-body model.

77 4 – Second Generation Design

As evident from the simulation results in Fig. 4.16, the ESD protection circuits limit the currents and voltages to safer levels that can be sustained for short periods of time by the gates of input and source-drains of output transistors.

4.2.9 Chip-level integration of cells

The above circuits and their sub-circuits were designed into cell-level full- custom blocks for reusability and object-based testing, robustness, and reliability. They were integrated into the chip-level implementation of the full- digital control-pulse generator and it’s externally clocked variant, after each cell- block was tested individually using the Cadence® Virtuoso Analog Design Environment (ADE) simulation tool. This approach made it possible to reduce system level errors in functionality as each cell-block had to pass its stand- alone functionality tests, as they were only used at the system level once all internal issues were identified and resolved. Given the short time frame from concept to fabrication MPR run, I found this approach to be very time efficient.

The object based schematic design also allowed straight-forward test-bench implementation in the ADE. The chip level test-bench schematic screen-capture is shown in Fig. 4.17 for both the internally and externally clocked versions.

78 4 – Second Generation Design

(a)

Fig. 4.17 The chip-level full-custom digital control-pulse generator schematic in Cadence®.

79 4 – Second Generation Design

4.3 Experimental results

4.3.1 The RF-PCB

The second generation control-pulse generator design was tested in a similar setup to that of the first. The pulse generator chip was mounted onto a FR-4 type RF-PCB that was designed specifically in Microwave OfficeTM to fit the needs of the power-supply, inputs and fast (RF) output of the chip. This RF- PCB was in-turn mounted onto the enclosure shown in Fig. 4.18. The lines are tapered towards the chip to allow gradual impedance change on each line as they get closer towards the chip. This helps eliminate possible reflections of signals due to routing on the PCB, now leaving the possibility of reflection to the limitations on external wiring imposed by the measurement setup.

Fig. 4.18 The second generation RF-PCB enclosure made for the second generation control- pulse generator chip lying on its mounting-face with its power-supply, input, and output ports labeled.

80 4 – Second Generation Design

Proper mounting was possible using vacuum-grease and a flat surface of unetched-copper plating on the PCB as shown in Fig. 4.18. This RF-PCB was also designed with provisions to mount a separate Al-SET chip next to the control-pulse generator for localized temperature measurements. The Al-SET chip site has three tapered lines; one for the SET gate, and two for the SET source (DC-bias and RF-carrier). The entire enclosure was a common to both the control-pulse chip ground (VSS) and the SET chip grounded-dain (VD_SET; not shown in figure). This provides a degree of shielding from external interference to the sample within the enclosure, provided proper precautions are taken to shield all external cabling as well.

It is well known that decoupling is very important for microelectronics. The control-pulse generator chip is no exception. Hence each of it’s the lines VDD,

Vm2, Vm1, V2RuO2, and V1RuO2 have 4.7 nF ceramic feed-through decoupling capacitors as shown in Fig. 4.19. Although not obvious at first, ceramics capacitors are the only type that can be cooled to sub-K temperatures. The materials used in all other types of capacitors freeze-out thus cannot be used in dilution refrigerators. This places a top-limit for local external decoupling capacitance of the control-pulse generator chip as the highest capacitance in ceramic material that can be fitted to the chip enclosure is 4.7 nF. However, as shown from experimental verification in section 4.3.5, the value of the decoupling capacitor determines the steady-state droop time-constant thus the stability of the power-supply voltages on the Vm2 (HI) and Vm1 (LO) levels of the pulse. The larger the decoupling capacitance the longer this time-constant is and if the decoupling capacitances reaches large enough values, the time- constant is long enough to produce virtually steady power-supply voltages on VDD, Vm2, and Vm1. The results in Fig. 4.32 section 4.3.5 reveal a demonstration of this importance of proper decoupling in action, where Fig. 4.32a shows Vm2 decoupled with three parallel-connected 4.7 nF capacitors (equivalent capacitance of 14.1 nF), while Vm1 is only decoupled with a single 4.7 nF capacitor. Fig. 4.32b shows the same effect on Vm1 when the decoupling capacitors are interchanged between Vm2 and Vm1. Power- supply decoupling clearly is a significantly important issue in IC design and operation! 81 4 – Second Generation Design

VS_DCSET SET-chip site VG_SET 5 mm

VS_RFSET Vpulse 4.7 nF feed-through capacitor

Vm1 V2RuO2

Vm2

VDD V1RuO2

VSS RuO2 resistor

Vtrigger VREG_CLK Control-Pulse VREG_DATA S R Generator

Fig. 4.19 The enclosure with its mounting-face removed to show the second generation RF- PCB layout with the control-pulse chip bonded in the middle. and provisions for an RF-SET. The

1206 SMD packaged RuO2 resistor is soldered exactly 5 mm away from the chip. This is the closest to the chip a 1206 SMD package can be placed on this enclosure.

4.3.2 Experimental measurements at 300 K

Simulations in Cadence (refer Fig. 4.4) showed that the RO clock frequency was ((46.9-42.1)/3 ns)–1 = 625 MHz, based on the three clock edges that produced the shortest control-pulse. Experimentally at 300 K, the shortest control-pulse period was measured to be 8.15 ns implying a clock frequency of (8.15/3 ns)–1 = 368 MHz given that the counter requires three clock cycles to count down from 0×0002.

The measured rise-times at 4.2 K was 212 ps (refer Fig. 4.24), somewhat longer than that of the previous design, owing to the extra loads on-chip from ESD protection circuits. However this will not significantly affect qubit control 82 4 – Second Generation Design

functionality as non-adiabatic drive times are still in the hundreds-of- picoseconds time-scale.

The slight increase in rise-time was expected both in post-extraction simulations and experimental results, as this was based on the design decision to trade-off rise-time for yield. However the loading effects of measurement equipment on the output of the circuit were not performed as this control-pulse generator was designed to drive a qubit gate and not measurement equipment loads. Such simulations should have been performed during the post-layout process, after all the main design requirements were satisfied. However we were not overly concerned about achieving good agreement between simulation and measurements as the 300 K models used from the PDK were quite inaccurate for the lower temperatures of interest to this work. These 300 K PDK models were only used for validating the general operation of the chip. Although device modelling is important, in this work the primary thrust was to design the chip and demonstrate experimental evidence that it works at 4.2 K and sub-K. Hence given the limited time to deliver the two generations, I focused on the designs and demonstrations while noting that modelling should be done in future work.

The rise-time measurements in both Figs. 4.21–4.25, 4.30, and 4.31 were performed using an Agilent 86100B DCA wide-band oscilloscope (WBO) with a 13 pF 50 Ω input impedance. The control-pulse generator was designed to drive up to a 0.1 pF high impedance load: a typical qubit gate fabricated in-house in the laboratory. It was not designed for a 50 Ω load. However this is necessary for fast rise-time measurements and pulse characterization. Hence in these figures, the measured voltage levels are very-low due to the voltage-division between the on-resistance (~300 Ω of the output switches and the 50 Ω load impedance of the WBO input). Fig. 4.22 shows a pulse as measured by an Agilent DSO8104A lower bandwidth digital-storage oscilloscope (DSO) with a 13 pF 1 M Ω input that shows that the pulse is in fact switching between the intended externally set voltage levels. The two comparisons also showed that the rise-time is not affected during thermal cycling from 300 K to sub-K (Fig. 4.22 and 4.29). In addition, the cables that carry the measured signal span

83 4 – Second Generation Design

~4 m from the chip along the dilution refrigerator to the measurement instruments present further parasitic loads. However the rise-time remained reproducible. The individual components of this implementation will be further described in the subsequent sections.

The power dissipation was based on IDD ~ 80 to 120 µA at VDD = 2 V at 4.2 K at repetition rates of from 100 Hz up to 1 MHz. This is an order of magnitude greater than the dissipation of the first generation circuit, which was consistent with simulation results. However the dissipation appeared somewhat within the above range for increasing repetition rates. This is still acceptable as, after these demonstrations, the hot CMOS circuits were planned to be positioned at the 1 K stage of the dilution refrigerator where on the order of Watts of power dissipation is possible; only multiplexing and demultiplexing circuits may remain at the sub-K stage with the qubit-chip or the tentative quantum processor. This release of the power constraints on the design can be exploited to explore more sophisticated, but not necessarily higher power, techniques of pulse generation on continuation of this work into future designs.

Fig. 4.20 The input trigger waveform (Vtrigger) showing non-ideal edge-transition due to reflections from the high-impedance gate input of the chip. However the significance of the Schmitt-triggers on-board the chip is evident as the chip is still triggered as if the Vtrigger edge transition did not have these anomalies. 84 4 – Second Generation Design

Fig. 4.21 Control-pulse output with 50 Ω terminated load showing signal attenuation due to higher loads and voltage division between the switch and the DSO input terminator.

Fig. 4.22 Pulse with high-impedance load showing pulse swing between set-points of ±0.2 V.

85 4 – Second Generation Design

Fig. 4.23 The control-pulse output from the second generation circuit as measured using (a) an Agilent DSO8104A DSO with a 13 pF 1 MΩ input impedance, (b) an Agilent 86100B DCA WBO with a 13 pF 50 Ω input impedance; the low levels are due to voltage-division between the 50 Ω load and the output switches. The rise-time (212 ps) was measured at 300 K. What appears to be a second time constant towards the settling time of the pulse is an artifact of the measurement setup as discussed in the following section.

4.3.3 Experimental measurements at 4.2 K

The chip enclosure was mounted onto a 4.2 K immersion column similar to that of the dilution refrigerator, and immersed into liquid-He as was done in the first generation tests.

15 15

10 10

5 5

0 0

−5 −5 Voltage (mV) Voltage (mV) −10 −10

−15 −15 4.2 K 4.2 K −20 −20 0 0.1 0.2 0.3 0.4 0.5 0 0.2 0.4 0.6 0.8 Time (ns) Time (ns) (a) (b) 86 4 – Second Generation Design

15 15

10 10

5 5

0 0

−5 −5 Voltage (mV) Voltage (mV) −10 −10

−15 −15 4.2 K 4.2 K −20 −20 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 Time (ns) Time (ns) (c) (d)

Fig. 4.24 The 4.2 K rise-time and rising-edge-shape measurements of the second generation digital control-pulse generator showing (a) 212 ps rise-time in a 1 ns window, and rising-edge pulse shape in (b) 2 ns, (c) 5 ns and (d) 10 ns windows.

4.3.4 Experimental measurements at sub-K

The chip was bonded onto the RF-PCB which was in-turn loaded onto an enclosure that was specifically designed for the chip, as was done before, in the first generation measurements. A RuO2 resistor was used as a calibrated thermometer to obtain local temperature measurements of the chip. The RuO2 thermometer was soldered onto the RF-PCB, close to the controller chip as in Fig. 4.19, and the enclosure mounted on the refrigerator as shown in Figs. 4.25 and 4.26. The thermometer was then biased with a constant current source of about 10 nA at 1.0 V (Isouce in Fig. 4.28) supplied by the SR830 Lock-In amplifier. The temperature is measured by measuring the resistance change of the RuO2 thermometer as the dilution refrigerator cools the sample. These resistors exhibit higher sensitivity to temperature changes as they cool below 1 K, and do not exhibit much change in their resistance when hotter than 4.2 K.

87 4 – Second Generation Design

Fridge Control Unit He Dewar

Dilution Refrigerator

Fig. 4.26

Fig. 4.25 The dilution refrigerator in which the sub-K measurements for the second generation were performed. The helium Dewar (He Dewar) and fridge control unit are also shown.

Now as evident from the current source and voltage thus produced across the

RuO2 resistor, this type of measurement does not introduce additional (or significant) heating relative to self-heating of a sample. In fact, this is exactly how the mixing chamber temperature is measured by the Fridge Control Unit.

88 4 – Second Generation Design

Mixing Chamber

Copper-Powder Filter

Sample

Fig. 4.26 The sample and its wiring showing the potential heat load on the fridge from the many necessary cables (SMAs for singals, semi-rigid for fast signals, single-core for power-supply). It also shows the copper-powder filter used to filter high-frequency noise from the signals lines.

Fig. 4.27 shows the resistance-to-temperature curve of a 1580 Ω RuO2 thermometer. Such resistors are calibrated at manufacture against a Pt(100)3

3 The RuO2 and Pt(100) resistors are quantum devices; Pt(100) is the best crystal available being made of a metallic lattice, measuring exactly 100 Ω at 300 K. In an ideal (homogeneous) 89 4 – Second Generation Design

platinum resistance thermometer. The curve can then be used to measure temperature using the RuO2 as the transducer.

5 10 100 K to sub−K

4 10

3 10

2 10

1 10 Temperature (mK)

0 10 Ω

−1 1580 10 3 4 5 6 10 10 10 10 Resistance (Ω)

Fig. 4.27 The temperature-resistance characteristics of a 1580 Ω RuO2 1206 surface-mount device (SMD) resistor.

100M SR830 SR830 SOURCE MEASURE

1580R Vsource Isource RuO2 1206 SMD

300 Ksub−K 300 K

Fig. 4.28 The standard 4-terminal RuO2 bias and measurement circuit.

crystal an electron travels as a Bloch-wave (i.e. unscattered); resistance occurs due to scattering. The electron waves scatter in a Pt(100) only due to impurities in the crystal making it non-ideal (inhomogeneous). However their waves scatter lesser as the temperature reduces because the entropy of the electron reduces with temperature. That is, the uncertainty in the electron’s energy (reduces limited by Heisenberg’s principle) which reduces scattering. 90 4 – Second Generation Design

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 0×0002 6.23 ns ± 50.2 ps 0×0003 7.57 ns ± 29.8 ps

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 0×0004 11.67 ns ± 40.5 ps 0×0005 12.99 ns ± 16.5 ps

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 0×0006 14.41 ns ± 32.0 ps 0×0007 16.17 ns ± 558.0 ps

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 91 4 – Second Generation Design

0×0008 19.76 ns ± 69.9 ps 0×0009 22.71 ns ± 539.0 ps

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 0×000A 22.48 ns ± 160.0 ps 0×000B 26.35 ns ± 448.0 ps

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 0×000C 27.65 ns ± 470.0 ps 0×000D 31.60 ns ± 745.0 ps

25 25 sub−K sub−K 20 20 15 15 10 10 5 5 0 0 −5 −5 Voltage (mV) Voltage (mV) −10 −10 −15 −15 −20 −20 −25 −25 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Time (ns) Time (ns) 0×000E 30.45 ns ± 18.0 ps 0×000F 33.85 ns ± 1350.0 ps

Fig. 4.29 Demonstration of the pulse-width and standard deviation (due to sporadic jitter sources) as the control-word is set from 0×0002 to 0×000F. The waveforms and time measurements were obtained using the Agilent DSO8104A low-bandwidth DSO. These sporadic jitter sources are most likely self-heating effects of parts of the counter, or clock, and that heat not flowing evenly through the circuit surface. It was not possible to identify these issues in this generation as there was not enough time to make provisions for such diagnostics.

92 4 – Second Generation Design

The results in Fig. 4.29 above is a demonstration, at sub-K, of the relatively more accurate pulse-width control offered by using the counter in the second generation controller, plotted for control words from 0×0002 to 0×000F. Hence Fig. 4.29 is a tabulation of the control-pulse dwell-times versus control-words. As mentioned before, 0×0000 and 0×0001 are not used unless wrap-around is intended, as at these control-words the counter reaches zero before the propagation delay of the feedback circuit allows the zero-flag signal to stops the clock. Figs. 4.30 and 4.31 show the rise-time of the control-pulse at sub-K which shows that it is consistent with 212 ps as measured at 300 K, and 4.2 K. Fig. 4.31a shows the rising edge, and Fig. 4.31b shows the falling edge. All measurements in Figs. 4.29–4.31 were obtained using the 86100B DCA WBO. However, in contrast to the first generation, here the jitter was significantly lower as the falling-edge was now controlled by a clocked circuit therefore reducing the jitter to a fraction of the clock-pulse. These measurements confirmed my justification for designing the full-digital second generation. There were occasions of sporadic jitter from unknown sources that are recorded as a spread rather than root-mean-square (RMS) jitter in Fig. 4.29 for control-words of 0×0007, 0×0009, 0×000B, 0×000C, 0×000D, and 0×000F. These sporadic jitter sources are most likely self-heating effects of parts of the counter, or clock, and that heat not flowing evenly through the circuit surface. It was not possible to identify these issues in this generation as there was not enough time to make provisions for such diagnostics. However these sporadic occurrences warrant further investigated in future work.

−5 Voltage (mV) −10

−15 sub−K −20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Time (ns)

Fig. 4.30 A pulse for control word of 0×0002 measured with the Agilent 86100B DCA WBO showing the setup time-constant effects. However the fast-rise time is distinguishable. 93 4 – Second Generation Design

20 20

15 15

10 10

5 5

0 0

−5 −5 Voltage (mV) Voltage (mV)

−10 −10

−15 −15 sub−K sub−K −20 −20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ns) Time (ns) (a) (b)

Fig. 4.31 The same pulse as in Fig. 4.30 for control word of 0×0002 measured with the Agilent 86100B DCA WBO showing the fast-rise time measurable at about 212 ps. This is significant as the chip is producing these rise-times despite the large setup parasitic loads.

4.3.5 Effects on pulse shape due to measurement setup

The measurements in Fig. 4.32 is a 0x8000 pulse with ~5 µm dwell-time used to test the effects of disconnected the pulse-out line from the refrigerator setup and shunting it with a 1.5 m short cable to the Agilent DSO8104A low- bandwidth DSO. These output were also obtained with a set of 3 parallel- connected 4.7 nF ceramic capacitors (14.1 nF) soldered to either Vm2 or Vm1 ports of the enclosure and its other end grounded to the enclosure mount on the refrigerator. This figure captures the significance effects of using higher decoupling capacitance and lower resistance lines.

94 4 – Second Generation Design

15 300 K

Voltage (mV) −5

−10

−15 0 5 10 15 20 25 Time (µs) (a)

15 300 K

Voltage (mV) −5

−10

−15 0 5 10 15 20 25 Time (µs) (b)

Fig. 4.32 The effects of shunting the long 4 m pulse-output line with a shorter 1.5 m cable and (a) Vm2 and (b) Vm1 ports of the enclosure decoupled with 3 parallel-connected 4.7 nF capacitors. The 0x8000 pulse with ~5 µm dwell time was used to test the effects of disconnected the pulse-out line from the refrigerator setup and shunting it with the 1.5 m short cable to the Agilent DSO8104A low-bandwidth DSO.

Intentionally left void

96 5 – Conclusion

5 Conclusion

Microelectronics has shaped the world beyond what was thought possible at the time of its advent. One area of current research in this field is on the solid-state Si:P-based quantum computer (QC). In this machine, each qubit requires an individually addressed fast control-pulse for non-adiabatic drive and measure operations. Additionally, it is increasingly becoming important to be able to interface nanoelectronics with complementary metal-oxide-semiconductor (CMOS) technology. In this work, I have designed and demonstrated mixed- mode and full-digital fast control-pulse generators fabricated in a silicon-on- sapphire (SOS) CMOS commercial foundry process, which is a radio-frequency (RF) CMOS technology.

Initially, after the design specifications were decided upon, I characterized NFET and PFET devices and a n+-diffusion resistor from 500 nm and 250 nm commercial SOS-CMOS processes. Measuring their conductance curves at 300 K, 4.2 K, and sub-K (30 mK base to 1000 mK) showed that they function at 4.2 K and sub-K with some deviations from 300 K measurements. In the NFET and PFET, there was a noticeable triode non-linearity in the ohmic region which was less pronounced in the 250 nm devices than in the 500 nm once. Following this I measured their transient response behaviours at the above temperatures that showed that they switch with no deviation to their rise-times of 100 ps at the above temperatures. This was the main deciding experiment which when combined with the financial aspects made the 500 nm technology feasible for this work.

The mixed-mode first generation control-pulse generator was demonstrated showing that it produced dwell-time adjustable pulses with 100 ps rise-times at 97 5 – Conclusion

300 K, 4.2 K, and sub-K. The design was based on current-starved inverters which would act as delay elements. However this design exhibited jitter that increased with increasing dwell-time in accordance with the conductance characteristics of the current-source used to starve current from the inverters. Jitter is inherent in all CMOS circuits and is limited by characteristics of the materials used in the fabrication processes, but the nature of the design is usually the primary cause. Power dissipation was promising at 12 µW at 100 MHz due to the simple design. This generation did not have electrostatic discharge (ESD) protection due to many uncertainties about loading the inputs, outputs, and power dissipation, which significantly affected chip yield.

The full-digital second generation control-pulse generator was demonstrated showing accurately adjustable dwell-times set via a control-word streamed synchronously to a shift-register. The design was based on ripple-counter with provisions for internal or external clocking, which would act as the delay element. The accurate control offered by this digital circuitry reduced pulse jitter to the process limit of about the order of a rise-time. This was a significant improvement from the previous design. The rise-time now was 212 ps at the above measurement temperatures, which may have been due to ESD protection included on all input and output pads. The ESD protection circuits were based on the standard 3 kV-2 A ESD source model. This increased chip yield and made their operation significantly reliable even after much handling. The slight increase in rise-time was expected both in post-extraction simulations and experimental results, as this was based on the design decision to trade-off rise-time for yield. However the loading effects of measurement equipment on the output of the circuit were not performed as this control-pulse generator was designed to drive a qubit gate and not measurement equipment loads. Such simulations should have been performed during the post-layout process, after all the main design requirements were satisfied. However we were not overly concerned about achieving good agreement between simulation and measurements as the 300 K models used from the PDK were quite inaccurate for the lower temperatures of interest to this work. These 300 K PDK models were only used for validating the general operation of the chip. Although device modelling is important, in this work the primary thrust was to design the chip 98 5 – Conclusion

and demonstrate experimental evidence that it works at 4.2 K and sub-K. Hence given the limited time to deliver the two generations, I focused on the designs and demonstrations while noting that modelling should be done in future work.

Future work will have to look at multiplexing and demultiplexing the control- pulses to and from millions of qubits in the tentative quantum processor, minimizing power dissipation, and most likely positioning the control-pulse generator (or its successors) at 1 K where power on the order of 1 W can be dissipated without affecting the dilution refrigerators sub-K stage. Reducing power-dissipation will inevitably contribute to the overall continuation and progressed maintained in this work. Also better jitter reduction circuits (such as AJCs) may be used to control phase noise and jitter even further. Also relatively more accurate thermometry and in situ indirect signal detection can be performed using an Al-SET instead of the RuO2 thermometer. The second generation RF-PCB has an SET-chip site for this purpose with the required DC- bias and RF-tank circuit components already soldered onto the PCB.

This research has made significant contribution to both microelectronics and quantum computer technology by demonstrating that SOS-CMOS technology is has very-high feasibility for controller fabrication for a Si:P-based QC. I have demonstrated mixed-mode and full-digital control circuits at 300 K, 4.2 K, and sub-K that have shown their operation at cryogenic temperatures and in the latter case favourable pulse characteristics. I believe I have achieved beyond the targets that were set at the beginning of this thesis, and I enjoyed every step of this great journey of learning, discovery, scholarship, and inventorship.

Intentionally left void

100 Appendix A

Appendix A – Acronyms and Abbreviations

ADE Analog Design Environment CB Coulomb Blockade DAC Digital-to-Analog Converter DC Direct Current BCO Bias-Controlled Oscillator (such as VCO and CCO) CCO Current-Controlled Oscillator (refer BCO) CQO Controller-Qubit-Observer DRAM Dynamic RAM DFM Design-For-Manufacturability DLL Delay-Locked Loop DRC Design-Rules Check GDS-II Graphic Data System II ELTRANTM Epitaxial Layer Transfer (A trademark of Canon, Inc.) ESD Electrostatic Discharge FET Field effect transistor GDS-II Graphic Data System II HI Logic-High IC Integrated Circuit IDE Integrated Design Environment LO Logic-Low LSI Large-Scale Integrat[-ed][-ion[ LVS Layout-Versus-Schematic MATLAB® A mathematical simulation application from MathWorks Inc. MIM Metal-Insulator-Metal

101 Appendix A

MOS Metal-Oxide-Semiconductor MOSFET refer MOS and FET MPR Multi-Project Reticle MPW Multi-Project Wafer. Refer MPR. PCB Printed Circuit Board PLD Programmable Logic Device PSA Peregrine Semiconductor Australia PSC Peregrine Semiconductor Corporation PVD Physical vapor deposition PCVD Physo-chemical vapor deposition QD Quantum dot (0DES) QW Quantum wire (1DES), or Quantum-well (2DES) QED Quantum Electrodynamics QM Quantum mechanic[-s][-cal] RAM Random access memory RC Resistor-capacitor RF Radio frequency RF-CMOS Radio-Frequency Complimentary-Metal-Oxide-Semiconductor RO Ring oscillator SET Single-Electron Transistor SIMON Separation by Implantation of Nitrogen SIMOX Separation by Implantation of Oxygen SMU Source-Measure Unit SOI Silicon-On-Insulator SOS Silicon-On-Sapphire SPICE Simulation program with integrated circuit emphasis sub-K sub-Kelvin (1 mK to 1000 mK) UTSi Ultrathin-Silicon (UTSiTM, alternatively, UltraCMOSTM) VCO Voltage-Controlled Oscillator (refer BCO) VLSI Very-Large Scale Integration

102 Appendix B

Appendix B – Symbol Index

ε Relative permittivity of a material (εrε0). 2 –1 –1 ε0 Absolute (electric) permittivity of free space ((c µ0) F·m ).

εr Dielectric constant of a material, which is the ratio of the absolute permittivity of the material to that of free space. –7 –1 µ0 Absolute (magnetic) permeability of free space (4π·10 H·m ). τ Time constant (s). Ced External decoupling capacitance (F/m) Cid Internal decoupling capacitance (F/m) Ddwell Dwell-time short/long range select on logic-LO/HI (V)

ID Drain current (A) L MOSFET channel-length (µm) Lline Line inductance (H/m) Lbond Bond-wire inductance (H/m) – assume 1 nH/mm for metal bond-wire VDD Positive power-supply voltage (V) VDS Drain-source voltage (V) VGS Gate-source voltage (V) VSS Negative power-supply voltage (V) Vtdwell Analog dwell-time setting (V) Vm2 Logic-HI level of control-pulse (V) Vm1 Logic-LO level of control-pulse (V) Vpulse Control-pulse output from generator chip (V) Vtrigger Trigger pulse input (V)

VT Thermal voltage (kBΘ/q = 0.026 V) T Temperature (K) W MOSFET channel-width (µm)

103 Appendix B

c Speed of light in free space (exactly 2.99792458·108 m·s–1). q Elementary charge (–1.6022·10–19 C). –23 –1 –5 –1 kB Boltzmann constant (1.3807·10 J·K or 8.6175·10 eV·K ). tdwell Dwell-time (s), control-pulse duration (s) tr rise-time (s) ft Gain-bandwidth product (Hz) r Radius (m) v Velocity (m·s–1).

104 Appendix C

Appendix C – Patents and Publications

Published in IEEE-NANO 2007

Quantum bit controller and observer circuits in SOS-CMOS technology for gigahertz low-temperature operation

S. Ramesh Ekanayake 1, 2,*, Student Member IEEE, Torsten Lehmann 2, Senior Member IEEE, Andrew S. Dzurak 1, 2, Robert G. Clark 1, 3 1 Australian Research Council Center of Excellence for Quantum Computer Technology, 2 School of Electrical Engineering and Telecommunications, 3 School of Physics, University of New South Wales, Kensington, NSW, 2052, Australia.

Abstract––Quantum bit (qubit) control and readout requires However quantum gate operations on a qubit require ultra- controller-qubit-observer systems for rapid control signal fast pulse signals with typical rise times on picosecond generation and injection to the qubit gates, and observation of timescales [3] to drive the qubit non-adiabatically to undergo their final state projections. Conventionally, for solid-state coherent quantum oscillations. Conventionally, this has been qubits, this is achieved by generating the control signal at 300 K done by sending control pulses along very long coaxial cables and transmitting it along very long coaxial cables that span from from the signal source to the sample, and receiving sensor 300 K to sub-K (typically d 500 mK), then reading out the responses over similar lengths of cable to readout equipment response from charge proximity sensors such as single-electron followed by further processing. The typical experimental setup transistors along similar lengths of cable. Our approach is to is illustrated in Fig. 5a. This approach has many interconnects, fabricate the classical controller and observer circuits using a attenuators, and terminals from the source to the sample and commercial foundry processed silicon-on-sapphire (SOS) RF- vice versa that introduce parasitics from long lines, and CMOS technology for operation at low temperatures (either at 4.2 K, 1 K, or sub-K). We have demonstrated SOS-CMOS NFET possible reflections from impedance mismatches that can cause and PFET device operation at 4.2 K, and sub-K that showed undesirable signal distortions. deviations from their 300 K characteristics, but with further There have been reports of low-temperature control experiments these were shown to have minimal effects on control electronics using superconducting device fabrication circuit function. Using these results, we have fabricated and technology for controlling flux qubits and superconducting demonstrated a low-power proof-of-concept SOS-CMOS devices. Most of these reports are on rapid single-flux quantum controller circuit (monostable 100 ps voltage-pulse generator) (RSFQ) technology for flux qubit control [4-6], and some on that can operate at sub-K temperatures in a dilution refrigerator. We briefly discuss experimental and conceptual schemes with low-temperature RSFQ-based microprocessors [7]. There have which we can develop qubit control systems for cryogenic and also been reports of interfacing nanoelectronic devices with lower temperatures. These low temperature experiments also complementary metal-oxide-semiconductor (CMOS) demonstrate that commercial SOS RF-CMOS technology can be technology as well [8, 9]. However RSFQ technology has its feasible for other low temperature and low power applications. limitations such as low pulse voltages (typically PV–low-mV scale), requirements for an applied magnetic field, high power Index Terms—CMOSFETs, control systems, cryogenic dissipation in relatively simple circuits due to requirement of electronics, quantum effect semiconductor devices. bias currents, and the lack of technology maturity. However the potential for CMOS technology for low temperature control I. INTRODUCTION circuit design has not been investigated. Silicon (Si) quantum computers (QCs) based on charge The motivations for our work on silicon-on-sapphire (SOS) qubits [1] and spin [2] qubits will, once realized, require RF-CMOS controller (monostable voltage-pulse generator) advanced controller-qubit-observer (CQO) circuit systems to design for low-temperature operation were perform quantum gate operations (quops) and qubit readout. We use the terms "controller" and "observer" for the devices a) the requirement of cryogenic or lower temperatures for qubit that semi-classically control and measure the eigenstates of a operations, quantum system analogous to and in the context of classical b) low power design capability with Voltage-scale pulse state-space control and estimation of a linear classical system. heights, c) need for 100 ps or sub-100 ps (GHz band) pulse rise time, Manuscript received February 15, 2007. This work was supported by the d) bond the controller and qubit chip in the same package, thus Australian Research Council (ARC), the Australian Government, and the US e) eliminate long lines to minimize parasitic effects on signals, National Security Agency (NSA), Advanced Research and Development Activity (ARDA), and the Army Research Office (ARO) under contract f) use a technology-mature design-to-fabrication process: number W911NF-04-1-0290. CMOS has extensive commercialized computer-aided- * S. R. Ekanayake is with the ARC Center of Excellence for Quantum design (CAD) and fabrication support. Computer Technology, and the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, NSW, 2052, Australia (email: [email protected]).

105 Appendix C

Additionally, there has been comprehensive theoretical work developed on donor-based QC and architectures by 2.5 Hollenberg and colleagues [1, 10, 11] shown in Fig. 4. Our 2 work contributes to these efforts towards the future of developing a solid-state Si:P-based spin-QC originally inspired 1.5 by the Kane proposal [2]. 1 PMOS W/L = 10/0.4 V = [−2, 0] V This paper discusses NFET and PFET device characterize- 0.5 DS ∆V = (−0.2) V DS ations and the first generation classical controller design and 0 (mA) D

issues identified from 4.2 K and sub-K experiments in the I NMOS W/L = 10/0.4 V = [0, 2] V −0.5 DS laboratory, followed by a summary of improvements that have ∆V = 0.2 V DS lead to a second generation controller. We also propose −1 experimental schemes for the position of controller and observer circuits in more advanced stages of QC development. −1.5 −2 (a) 4.2 K II. EXPERIMENTAL SECTION −2.5 −2 −1.6 −1.2 −0.8 −0.4 0 0.4 0.8 1.2 1.6 2 V (V) A. Device measurements DS We demonstrated NFET and PFET devices from the above 2.2 mentioned commercial SOS RF-CMOS 500 nm technology 300 K 2 4.2 K with measurements at 300 K, 4.2 K, and sub-K [12]. The devices tested showed slight deviations from their 300 K 1.8 characteristics: non-linear behavior in the normally-linear 1.6 triode region, what appear to be short-channel effects (SCEs) in the strong-saturation region, and a slight increase in gain 1.4 possibly due to lower charge scattering rates at low 1.2 temperatures [12]. The devices showed repeatable behavior 2 1 from temperature cycling suggesting they survive the resulting 1.5 thermal shock [12]. Fig. 1a shows the I(V) measurement results Output voltage (V) 0.8 of individual NFET and PFET devices operated at 4.2 K. We 0.6 1 also performed an experiment to test local device matching 0.4 0.5 consistency in local FETs on the SOS substrate. This furthers 0.9 0.95 1 1.05 1.1 1.15 (b) our understanding of the design, as at low temperatures the 0.2 0 0.5 1 1.5 2 output FET characteristics, such as increased threshold Input voltage (V) voltages, can produce vastly different outputs and also cause Fig. 1 (a) The I(V) characterization of NFET and PFET devices at 4.2 K, and vastly different switching times that can introduce jitter. Hence (b) differential-pair output in a voltage amplifier configuration to measure testing for matching was necessary to eliminate the possibility device matching consistency between local FETs on the SOS substrate. The of device matching-related jitter, so that we were able to make voltage difference about the 1 V output bias, between the 300 K and 4.2 K results, is about 75 mV. There are many factors that can cause this shift, informed decisions about improvements to the design. This however as its magnitude is of the order of the bias voltage it indirectly shows involved a voltage amplification test on a differential-pair at that local dopant concentration is consistent at least between the differential- 300 K and 4.2 K with a 2 V power supply and a bias current of pair to ensure device matching. 20±5% A with the measurements shown in Fig. 1b. The P operation in the dilution refrigerator. There is also a need to results suggested that the doping consistency of this process minimize power dissipation and coupling to the adjoining was sufficient for local FET matching. This test was performed to ascertain whether doping consistency was the cause of pulse qubit chip which may deteriorate its performance due to jitter, which will be introduced in section II.B. We were able to thermal effects. Hence the first generation controller was deduce, based on these measurements, that the above SOS based in an analog pulse width control method although the process was suitable for our low temperature qubit controller pulse generation is performed using digital logic. The design requirements. operation of the controller at 4.2 K is shown in Fig. 2, clearly indicating the 100 ps rise time. The low peak-to-peak voltage B. Pulse generator measurements results from the measurement-dependent voltage division that occurs between the on-resistance of the output FETs and the Our first approach was to develop a simple controller to minimize device count, which implies lower power dissipation. input impedance of the wide-band digital storage oscilloscope Low power design is an important requirement for a qubit (WSO) with a sufficiently wide bandwidth that had to be used controller as the dilution refrigerators in which sub-K to measure this pulse without band-limiting it in the temperatures can be achieved have their limitations on cooling measurement equipment. This first generation controller power. The refrigerators in our laboratory can typically fabricated with ~100 individual transistors, shows that it maintain 100 mK at a limit of 100 PW. This sets the maximum operates with desirable results at 4.2 K and sub-K power dissipation limit of the controller, while in temperatures as shown in Fig. 2 and Fig. 3,

106 Appendix C

2 15 W)

µ 10 0 5 Power ( −2

) (mV) 0 t ( 0 20 40 60 80 100 o v

−4 Sample 400 Voltage, Mixing Chamber

−6 200

4.2 K −8 Temperature (mK) 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 20 40 60 80 100 Time, t (ns) Frequency (MHz) Fig. 2 Output voltage-pulse of controller showing rise-time of 100 ps at 4.2 K Fig. 3 Power-to-frequency curve showing linear behavior for varying pulse frequency, and the related temperature rise at the sample and in the mixing regardless of its relative complexity and high device count. Fig. chamber of the dilution refrigerator. 3 shows a power-to-frequency measurement performed at sub- control. This meant that the pulse-width would be limited to K temperatures to ascertain the degree of heating caused by the the resolution set by the word length of the registers with power dissipated by the controller in the cold-stage of the simulations showing the minimum possible pulse-width, for a dilution refrigerator where the qubit sample would most likely 16-bit word length, being about 2 ns before this particular be positioned. The power-to-frequency curve of the controller process technology reaches its switching frequency limit. We shows a linear relationship, as expected for switching circuits have countered this limitation by facilitating for an external with no bias currents. The thermal results show correlation of clock input that can be fed from a local quartz crystal or other temperature rise to switching (cycle) frequency of the voltage- source. We have yet to investigate whether quartz crystals can pulse measured using a ruthenium oxide (RuO2) thermometer operate with sufficiently high oscillations for RF-CMOS positioned close to the controller (sample) and compared to the clocking at cryogenic and lower temperatures. mixing chamber (MC) temperature of the dilution refrigerator. The sample is warmer than the MC due to the inability to The other concerning issue was electrostatic discharge perfectly heat-sink the controller chip to the MC. These low (ESD) protection. We did not include sufficient electrostatic temperature experiments and measurements provided us with protection on all input and output pads to ensure there was no the means to identify design issues in the first generation that capacitive loading on the incoming dynamic signals and the were insightful in designing the second generation controller. outgoing pulse signal which was expected to increase undesired power dissipation from the sample to the cold stage. The critical issue we identified was the analog pulse-width As such an approach has not been attempted prior to this, we control mechanism using current-controlled inverters was had to experiment by reducing the number of power consuming noisy, affecting the temporal stability of the falling-edge of the components to essential minima. However reducing ESD pulse producing significant jitter (phase noise) that is well- protection affected the final yield, which was expected. Hence known to be undesirable for qubit control. We concluded that the second generation controller has been fitted with ESD the analog components were the cause of this jitter, as the protection on all input and output pads with inputs buffered and edges were found to be stable when the analog pulse-width wide output FETs to drive the capacitive loading due to the control circuit was not in use. This was caused when the protection circuits. current-controlling FETs move through their non-linear regions during switching as they move from cut-off through saturation Transmission of the 100 ps voltage-pulse was not affected to triode regions and vice versa. Hence the higher pulse-widths by measurement setup. However we designed variants of the first generation controller with on-chip metal-strip transmission (t ~500 ps) suffer more jitter due to non-linear characteristics of the FETs combined with noise coupling through the gates lines for pulses traveling beyond the Faraday shield radius for and power supplies. We discerned, from 300 K and cryogenic Si of ~2.2 mm: this was calculated for the above rise time. Any experiments, that although the lower power dissipation in the pulse signals traveling beyond this radius were transmitted analog design approach allowed for higher switching through coaxial cables or metal-strip transmission lines. frequencies within the cold-stage cooling power limit it was Having summarized the issues learnt and dealt with from too susceptible to voltage-pulse jitter caused by noise coupling. our investigation of SOS-CMOS at cryogenic and lower This resulted in a shift in design paradigm from analog to temperatures, we intend to address these in more detail in a digital. Hence our second generation controller was based future paper. completely on digital logic and registers for pulse-width

107 Appendix C

classical classical processor processor 300 K controller observer

1–4.2 K A scalability coherent electron spin spin qubit storage J transport A

quantum logic gates qubit sensor d 100 mK power dissipation 50 :

classical Network classical 300 K Fig. 4 The central qubit interaction zone and transport rails for the two- processor processor dimensional (2D) linear-nearest-neighbor (LNN) Si:P spin qubit architecture theoretically investigated by Hollenberg et al.

III. FUTURE SCHEMES n n Although it is too early to predict which QC technology Feedforward platform will be most practicable or whether there would be 1–4.2 K controller observer different platforms suitable for the tasks to be performed, we m nm Superconducting n propose here some conceptual control system schemes for transmission lines positioning the controller and observer circuits, and the qubit system in a dilution refrigerator environment. Fig. 5b shows a nk scheme in which the controller and observer can be placed at 1–4.2 Kor quantum mux processor sensors demux 4.2 K, or 1 K due to higher power dissipation. The controller sub-K and observer would then be connected to the qubit system at the sub-100 mK stage via transmission lines, as this requires the gigahertz signals to travel beyond the aforementioned Faraday shield radius. It is also likely that if these complex Fig. 5 (a) Conventional setup for solid-state qubit control and readout. (b) circuits can be designed to dissipate lesser power, through Conceptual diagram of a scheme for a scalable quantum processor. This further refinements and faster RF-CMOS processes, the scheme is the motivation of our current work in developing controller circuits controller and observer circuits may be placed in the sub-K to operate either at 4.2 K, 1 K, or sub-K. The bus line numbering indicated is stage eliminating the need for transmission lines. Also there is for illustration purposes only. the possibility that yet again due to power dissipation limits in the sub-K stage, that the qubit system may only be interfaced to IV. CONCLUSION a RF-CMOS multiplexer-demultiplexer system positioned at the sub-K stage while the controller and observer may be Our work has demonstrated that commercial RF-CMOS positioned in the 1 K or 4.2 K stages. Based on the LNN technology can be used to fabricate classical controller circuits architecture discussed above and shown in Fig. 4, it is possible for quantum devices and that these circuits can be operated at for the hypothetical quantum processor in Fig. 5b to consist of low temperatures. The device measurements revealed that a qubit-gate array or more, which would require such schemes. commercial SOS-CMOS FETs designed and fabricated for A possible conceptual multiplexing scheme is proposed in Fig. higher temperature (218–348 K) operation can operate at 6 where fine-adjust mechanism is built-in to allow for shifts or cryogenic and dilution temperatures (sub-K) with the resulting drift in individual qubit characteristics that can be adjusted in situ prior to control and readout operations. deviations from their 300 K characteristics having no significant effect on controller design. We have shown that a

108 Appendix C

V V V fine adjust J2 VI. REFERENCE Substrate [1] L. C. L. Hollenberg, et al., "Charge-based quantum computing using single donors in semiconductors," Phys. Rev. B, vol. 69, pp. 113301(4), Multiplexer cell 2004. [2] B. E. Kane, "A silicon-based nuclear spin quantum computer," Nature, V pulse qubit gate qubit vol. 393, pp. 133-137, 1998. [3] Y. Nakamura, Y. A. Pashkin, and J. S. Tsai, "Coherent control of

A0 macroscopic quantum states in a single-Cooper-pair box," Nature, vol. A1 398, pp. 786-788, 1999. [4] D. S. Crankshaw, et al., "An RSFQ variable duty cycle oscillator for V V V V V SS SS SS SS J1 driving a superconductive qubit," IEEE Trans. Appl. Supercond., vol. 13, Fig. 6 A conceptual on-chip multiplexing strategy where the pulse is pp. 966-969, 2003. multiplexed and capacitively coupled to an island and the potential levels fine [5] V. K. Semenov and D. V. Averin, "SFQ control circuits for josephson tuned using a charge injector such as a SET. junction qubits," IEEE Trans. Appl. Supercond., vol. 13, pp. 960-965, 2003. complex RF-CMOS circuit fabricated of hundreds of can [6] T. A. Ohki, M. Wulf, and M. F. Bocko, "Picosecond on-chip qubit operate at such cryogenic and lower temperatures opening control circuitry," IEEE Trans. Appl. Supercond., vol. 15, pp. 837-840, 2005. CMOS technology to a wide range of potential applications in [7] M. Dorojevets, "A 20-GHz FLUX-1 superconductor RSFQ quantum interfacing, controlling, and observing. We have microprocessor," J. Phys. IV (France), vol. 12, pp. 157-160, 2002. discussed the various issues involved with our first generation [8] Y. Feng, et al., "Josephson-CMOS hybrid memory with ultra-high-speed analog controller design and the modifications that lead to a interface circuit," IEEE Trans. Appl. Supercond., vol. 13, pp. 467-470, second generation register-based digital controller. We also 2003. [9] T. van Duzer, Y. Feng, X. Meng, S. R. Whiteley, and N. Yoshikawa, discussed the motivations that lead us to explore RF-CMOS "Hybrid Josephson-CMOS memory: a solution for the Josephson technology as a possible platform for controller design, and memory problem," Supercond. Sci. Technol., vol. 15, pp. 1669-1674, proposed some strategies that may be utilized to integrate the 2002. controller and Si:P-based qubits into a practicable model in a [10] L. C. L. Hollenberg, A. D. Greentree, A. G. Fowler, and C. J. Wellard, dilution refrigerator, such that all individual qubit control and "Two-dimensional architectures for donor-based quantum computing," Phys. Rev. B, vol. 74, pp. 045311(8), 2006. readout can be performed via techniques such as multiplexing [11] Communication with L. C. L. Hollenberg, "Architectures for future and transmission lines. These strategies also proposed scalable spin quantum computing," 2007. positioning the controller and observer circuits in a single [12] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, R. G. Clark, and A. package or in various cold-stages of the dilution refrigerator to Brawley, "Characterization of SOI RF-CMOS FETs at ultra-low minimize control-pulse signal distortions due to non-idealities temperatures for the design of integrated circuits for quantum bit control within the experiments. and readout," IEEE Trans. Electron Devices, vol. submitted, 2007.

V. ACKNOWLEDGEMENTS S. R. E thanks Robert Starrett for technical assistance with measurements in the laboratory, and discussions regarding RF experimental setups, and associated analyses and calculations. We also thank Lloyd Hollenberg for valuable discussions surrounding the conceptual LNN architecture.

109 Appendix C

Published in IEEE – NANO 2008

Qubit control-pulse generator circuits for operation at cryogenic temperatures S. Ramesh Ekanayake *, Student Member IEEE, Torsten Lehmann, Senior Member IEEE, Andrew S. Dzurak and Robert G. Clark Australian Research Council Center of Excellence for Quantum Computer Technology, and School of Electrical Engineering and Telecommunications, University of New South Wales, Kensington, NSW, 2052, Australia * Corresponding author. email: [email protected].

Abstract–Solid-state quantum bits (qubits) generally require control-pulse integrity due to effects such as damping or ringing cryogenic operating temperatures together with rapid voltage (or from line-parasitics, signal attenuation from line-thermalizing current) pulse generation for qubit control and readout. attenuators and parasitic power dissipation from terminators. Conventionally this is achieved by generating the signals at 300 K, Such an approach also appears impractical for extension to transmitting them along very long coaxial cables that span t 4 m from 300 K to sub-K (30–500 mK) into a dilution refrigerator, and scalable quantum computing involving the control of thousands, reading-out the final qubit states via similar lengths of cable. Here or millions, of qubits. A motivation therefore exists to develop we fabricate the control-pulse generator circuits using a control-measure circuitry that can control a large number of foundry-processed SOS-CMOS technology that is capable of qubits and operate at cryogenic temperatures, such as the 1 K operation down to sub-K temperatures so that control signals can stage of a dilution refrigerator, where interfacing to the qubit be generated at cryogenic temperatures in the near vicinity of the chip may be greatly simplified and signal integrity improved. qubits. We present two full-custom large-scale integrated (LSI) control-pulse generator circuits: (a) a mixed-mode; and (b) a Here we report the design, fabrication and cryogenic digital design each comprising hundreds of devices, and show pulse operation of control-pulse generator circuits using characteristics at 4.2 K, demonstrating LSI circuit operation at foundry-processed silicon-on-sapphire complementary metal- low temperatures. The mixed-mode design showed lower power oxide-semiconductor (SOS-CMOS) technology, specifically dissipation but had increasing jitter at longer dwell times. The Peregrine Semiconductor Corporation’s 500 nm ultra-thin Si digital design eliminated jitter but at the expense of increased process. We have previously demonstrated device operation power dissipation. Although power dissipation is higher in the digital design, it should be possible to thermally anchor such from this process at 300 K, 4.2 K and sub-K temperatures [7], control circuits at the 1 K stage of a dilution refrigerator thereby motivating our investigation of cryogenic operation of minimizing heat propagation to the qubits. large-scale integrated (LSI) systems. The lower capacitances present in SOS-CMOS transistors, compared with bulk CMOS, I. INTRODUCTION provide an advantage when designing low-power circuits for the Solid-state qubits have considerable potential for the generation of qubit control pulses with edge-transitions as fast realization of large-scale quantum computing [1] since as 100 ps (process limit). The requirement for low power microfabrication technologies may be employed to fabricate dissipation is critical for cryogenic operation, particularly at integrated arrays of qubits. Most solid-state qubits proposed to temperatures of 1 K and below. The use of a foundry-processed date, such as those based on superconductor [2] or technology allows fast prototyping and development of control semiconductor [3-6] systems, must be operated at cryogenic circuits for simple qubit control trials, as well as providing a temperatures (typically below 1 K, referred to as sub-K herein) convenient platform for the development of control systems for in order to maintain long coherence times relative to gate scalable solid-state quantum processors. We discuss here two operation times. Additionally, in the case of silicon donor-based full-custom control-pulse generator designs: (A) a mixed-mode qubits [4-6], each qubit has a unique physical environment that circuit fabricated with ~100 devices; and (B) a digital design will require individually tuned fast-pulse control circuitry to fabricated with ~500 devices. Both designs showed fast pulses initialize, write, process, and read out their states [6]. These at 300 K, 4.2 K and sub-K temperatures, demonstrating LSI operations can be performed by using voltage pulses with rapid SOS-CMOS circuit operation at low temperatures. edge transitions for non-adiabatic qubit control [2]. II. EXPERIMENTAL Experimentally, this has been achieved by generating the The essence of our design was based on a standard-logic control pulses at 300 K and sending them along very long voltage-pulse generator [8]. In this design, the control-pulse coaxial cables spanning t 4 m from 300 K to sub-100 mK, and trigger input (Vtrigger) signal takes two paths to the pulse readout performed along similar lengths. This approach generating AND-gate (Figs. 1 and 2): one through a inevitably introduces non-idealities in the signal path that affect logic-inverting delay element to one input and the other direct to the other input such that while Vtrigger is either at logic-low Manuscript received March 15, 2008. This work was supported by the (LO), logic-high (HI) or transitioning from HI to LO the output is Australian Research Council, the Australian Government, and the US National Security Agency (NSA), Advanced Research and Development Activity LO. The only duration the AND-gate output toggles HI is from (ARDA), and the Army Research Office (ARO) under contract number the time Vtrigger makes a transition from LO to HI until such W911NF-04-1-0290.

110 Appendix C

time Vtrigger propagates through the delay element. Once this B. Second Generation Full-Digital Design event occurs, the output toggles to LO again. The resulting Our second-generation control circuit was a full-digital AND-gate output is then boosted with a super-buffer stage. This voltage-pulse generator shown in Figs. 2a and 2c. It has several is a series of cascaded inverters with increasing load-drive improvements made to address issues identified in the first capability with each successive stage with the last stage driving generation. This design was based on the same standard-logic a NFET-gate of width WN and length LN. Thus the pulse-delay principle as before with the delay element replaced succession-multiplier \ of a N-stage super-buffer can be with a clocked ripple counter that flags when to stop the pulse. evaluated as The entire structure is based on a logic enabled load-count 1 N mechanism based on the logic level of a trigger pulse as follows: \ WN (1) WWnN,0, (2) nn1 \ > @` 1. the Vtrigger signal is set LO and RESET and SET lines are set

where W0 = 1.4 Pm and Ln = 0.5 Pm for the 500 nm ultra-thin Si HI to put the shift register and ripple counter into load-mode, process [7] used to implement this design. The super-buffer 2. the dwell-time of the control-pulse is set by a control-word stages were designed to drive a qubit-gate load of about 100 fF between 0u0000 and 0uFFFF streamed into the 16-bit shift maintaining rise-times of the order of the 100 ps estimated from register via a two-wire synchronous serial port, Cadence® Spectre simulations. On-chip decoupling capacitors 3. the sequentially sent control-word gets loaded onto the were used for charge-supply on-demand to the fast output counter in situ from the register via loading logic, switches as the power-supply lines would not be able to supply 4. if the register/counter contents is non-zero the AND-gate currents at timescales of the order of these rise-times. output flags HI, the counter clock enters ready-mode, 5. once the register is loaded the serial lines are set LO, A. First Generation Mixed-Mode Design 6. the Vtrigger is set HI selecting count-mode, Our first-generation control circuit developed was a 7. the control-pulse is set output HI, the clock is enabled, and mixed-mode voltage-pulse generator, the schematic diagram of the counter starts processing: counting from the which is shown in Figs. 1a and 1c. In this design the delay control-word down to zero, element was a pair of cascaded current-starved inverters that act 8. once the counter reaches zero or the Vtrigger is set LO as delay elements. An analog input port allowed external control whichever occurs first, the control-pulse is set output LO and of current through the current-starved inverter structures using a clock is disabled, controlled current source, which was a PFET device. Using this 9. the same control-pulse can be regenerated periodically, by technique we have been able to demonstrate sub-10 ns setting the Vtrigger frequency to a desired repetition rate, pulse-widths and 100 ps rise times at 4.2 K [9], as shown in 10. the dwell-time of the control-pulse can be set to another Fig. 1b. It is a relatively simple LSI circuit to reduce power value by repeating the process from step 1). dissipation to a practical minimum while maintaining gate-drive strength and low-temperature operation. However it enabled us We designed two versions: one with a dedicated internal ring to demonstrate that relatively sophisticated LSI circuits can be oscillator that runs at 368 MHz; and one with provision for an operated at sub-K temperatures. We also found that the pulse external clock feed-in. The latter allows testing this circuit at characteristics remain relatively unchanged during and after faster clocking speeds up to dwell-times that span few rise cool-down to sub-K temperatures, and that thermal cycling times. This is ultimately process-limited by process between 300 K and sub-K does not affect these characteristics. characteristics. Most importantly, jitter is now process-limited This design dissipates ~16 PW at a repetition rate of to the order of the rise time, a significant improvement from the 100 MHz, which is an encouraging result. Whilst low in power first generation. In addition, increased ESD protection to all dissipation, it exhibited pulse jitter far higher than the order of pads of the wafer dramatically improved chip yield and the rise time, especially for longer dwell times. This was most reliability. The shortest dwell time for this design was limited to likely due to noise on the analog input perturbing the output of 8.2 ns, corresponding to 3 clock periods (control-word the current-source based on its control characteristics producing of 0u0003) as the least-significant bit (LSB) is ignored during an uncertainty in the current which strongly-couples to the the counter output processing. This avoids counter-wrapping switching times of the current-starved inverters. In this from delays in the logic stages. Additionally, a D-flip-flop was generation we intended to minimize on-chip capacitive loads on used to latch its state once it reached zero in order to force the the output transistors by not including any ESD protection for clock into disabled-mode, in case the propagation delay of the the output pads and including weak-ESD protection for the entire circuit lets the clock wrap the counter around. This was an input pads. This was due to uncertainty in operability of such an important consideration to avoid the control-pulse restarting LSI circuit at the temperatures of interest to us. However as while Vtrigger was HI. Finally, a combinational-logic circuit expected this made chips in this generation prone to ESD (15-bit OR-gate) determines whether the counter has reached it damage that compromised chip yield and reliability. zero-state. The output from this OR-gate forms the inputs to

111 Appendix C

both the clock-enable and the pulse-generating AND-gate, as to a 1.5 k:ҏ source resistance. The purpose of this large shown in Figs. 2a and 2c. The measured rise time at 4.2 K was FET-clamp was to act as a low-resistance current path through 210 ps (see Fig. 2b), somewhat longer than that of the previous which an ESD-current can flow and dissipate its energy during design, owing to the extra loads on-chip from ESD protection an ESD event. Inclusion of diode-connected FET-clamps on all circuits. However this will not significantly affect qubit control inputs and outputs, and the inclusion of this FET-clamp on the functionality as non-adiabatic drive times are still in the power –supply rails dramatically increased the chip yield. hundreds-of-picoseconds time-scale. The rise-time measure- III. CONCLUSION ments in both Figs. 1b and 2b were performed using an Agilent 86100B DCA wide-band oscilloscope (WBO) with a We have demonstrated SOS-CMOS mixed-mode and digital 13 pF 50 : input impedance. The control-pulse generator was LSI control-pulse generator circuits for qubit control. Our work designed to drive up to a 0.1 pF high impedance load: a typical has shown that these circuits can be operated at cryogenic qubit gate fabricated in-house in the laboratory. It was not temperatures from 4.2 K to sub-K, providing a design platform designed for a 50 : load. However this is necessary for fast control systems for scaleable solid-state qubit processors. rise-time measurements and pulse characterization. Hence in Future work involves new digital designs with reduced power Fig. 2b, the measured voltage levels are very-low due to the dissipation that can operate at the 1 K or 4.2 K stages, and voltage-division between the on-resistance (~300 : of the interfacing circuits to couple qubits at the sub-K stage of output switches and the 50 : load impedance of the WBO dilution refrigerator. input. Fig. 3a shows a pulse as measured by an Agilent IV. REFERENCES DSO8104A lower bandwidth digital-storage oscilloscope [1] M. A. Nielsen and I. L. Chuang, Quantum computation and quantum (DSO) with a 13 pF 1 M: input that shows that the pulse is in information: Cambridge University Press, 2000. fact switching between the intended externally set voltage [2] Y. Nakamura, Y. A. Pashkin, and J. S. Tsai, "Coherent control of macroscopic quantum states in a single-Cooper-pair box," Nature, vol. 398, levels. The two comparisons also showed that the rise-time is pp. 786-788, 1999. not affected during thermal cycling from 300 K to sub-K (Fig. [3] D. Loss and D. P. DiVincenzo, "Quantum computation with quantum dots," 2b and 3b). In addition, the cables that carry the measured signal Phys. Rev. A, vol. 57, pp. 120-126, 1998. [4] B. E. Kane, "A silicon-based nuclear spin quantum computer," Nature, vol. span ~4 m from the chip along the dilution refrigerator to the 393, pp. 133-137, 1998. measurement instruments present further parasitic loads. [5] L. C. L. Hollenberg, et al., "Charge-based quantum computing using single However the rise-time remained reproducible. donors in semiconductors," Phys. Rev. B, vol. 69, pp. 113301(4), 2004. The power dissipation was ~80-100 W at 4.2 K at repetition [6] L. C. L. Hollenberg, A. D. Greentree, A. G. Fowler, and C. J. Wellard, P "Two-dimensional architectures for donor-based quantum computing," rates of from 100 Hz up to 1 MHz. This is several orders of Phys. Rev. B, vol. 74, pp. 045311(8), 2006. magnitude greater than the dissipation of the first generation [7] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, R. G. Clark, and A. Brawley, circuit, which was consistent with simulation results. We are "Characterization of SOI RF-CMOS FETs at ultra-low temperatures for the design of integrated circuits for quantum bit control and readout," IEEE currently preparing sub-K measurements on this chip. Trans. Electron Devices, vol. submitted, 2007. The ESD protection circuits improved the chip yield of this [8] N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems generation dramatically relative to the previous generation. The Perspective, 3rd ed. Boston; London: Pearson Addison Wesley, 2005. [9] S. R. Ekanayake, T. Lehmann, A. S. Dzurak, and R. G. Clark, "Quantum bit main ESD protection circuit was a large FET-clamp on the main controller and observer circuits in SOS-CMOS technology for gigahertz power supply metal (i.e. VDD, and VSS), which was designed low-temperature operation," presented at the 7th IEEE International using the standard 3 kV–2 A human-body model corresponding Conference on Nanotechnology (IEEE-NANO 2007), Hong Kong, 2007.

VDD Vm2 2

−2 Vtrigger Vpulse ) (mV) t ( o v

−4 Voltage,

−6 (a) (b) VSS Vm1 4.2 K −8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time, t (ns) Fig. 1 (a) Schematic of the first-generation mixed-mode design. (b) Control-pulse output showing 100 ps rise-time at 4.2 K from the first-generation circuit.

112 Appendix C

VDD Vm2 VDD VDD VDD Vm2 100R VDD C2,m2 1.4/0.5 C1,m2 Vm2 2.0/0.5 C3,m2 100R 2.0/0.5 2.0/0.5 1.4/0.5 VSS 1.4/0.5 2.0/0.5 4.5/0.5 10/0.5 1.4/0.5 1.4/0.5 1.4/0.5 1.4/0.5 20/0.5 Vtrigger ESDP 2.0/0.5 2.0/0.5 VSS

Ddwell ESDP 1.4/0.5 1.4/0.5 Vpulse 1.4/0.5 1.4/0.5 Vdwell ESDP 20/0.5 VSS 1.4/0.5 2.0/0.5 4.5/0.5 10/0.5VDD 100R Vm1 C2,m1 C1,m1 VSS (c) C3,m1

VSS Vm1 VSS VSS VSS Vm1 VSS Fig. 1 (c) The comprehensive schematic design capture. The ESD pad protection (ESDP) cells are also shown in the schematic.

VDD Vm2 15

Vtrigger 5 Vpulse 0 COUNTER EN −5 Voltage (mV) −10

−15 VSS (a) Vm1 (b) 4.2 K −20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (ns)

Ring− VDD Vm2 Oscillator VDD Vm2 100R VDD EN OSC C2,m2 C1,m2 Vm2 C3,m2 100R 1.4/0.5 ESDP D15 D15 VSS REG_DATA DATA D14 2.0/0.5 4.5/0.5 10/0.5 D13 1.4/0.5 D12 20/0.5 REG_CLK ESDP D11 VSS D10 1.4/0.5 1.4/0.5 1.4/0.5 D9 DQ ESDP D8 Vtrigger D7 Vpulse 1.4/0.5 D6 S R ESDP D5 S SET D4 20/0.5 VSS 1.4/0.5 D3 D2 2.0/0.5 4.5/0.5 10/0.5 R ESDP RESET D1 D1 VDD D0 100R Register LD/CNT D0 C2,m1 Vm1 Ripple− Counter C1,m1 VSS (c) C3,m1

VSS Vm1 VSS VDD VSS Vm1 VSS Fig. 2 (a) Schematic of the second-generation digital design. (b) Control-pulse output showing 210 ps rise-time at 4.2 K from the second-generation circuit. (c) The comprehensive schematic design capture. The ESD pad protection (ESDP) cells are also shown in the schematic.

0.3 −5

0.2 −10

0.1 −15 0.0 −20 Voltage (V) (a) (b) −0.1 Voltage (mV)

−25 −0.2

300 K 300 K −0.3 −30 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.5 1 1.5 2 Time (ms) Time (ns) Fig. 3 The control-pulse output from the second generation circuit as measured using (a) an Agilent DSO8104A DSO with a 13 pF 1 M: input impedance, (b) an Agilent 86100B DCA WBO with a 13 pF 50 : input impedance; the low levels are due to voltage-division between the 50 : load and the output switches.

113

Intentionally left void

114 References

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