A Case for Packageless Processors Saptadeep Pal∗, Daniel Petrisko†, Adeel A. Bajwa∗, Puneet Gupta∗, Subramanian S. Iyer∗, and Rakesh Kumar† ∗Department of Electrical and Computer Engineering, University of California, Los Angeles †Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign fsaptadeep,abajwa,s.s.iyer,
[email protected], fpetrisk2,
[email protected] Abstract—Demand for increasing performance is far out- significantly limit the number of supportable IOs in the pacing the capability of traditional methods for performance processor due to the large size and pitch of the package- scaling. Disruptive solutions are needed to advance beyond to-board connection relative to the size and pitch of on- incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. We argue chip interconnects (∼10X and not scaling well). In addition, that packages reduce the potential memory bandwidth of a the packages significantly increase the interconnect distance processor by at least one order of magnitude, allowable thermal between the processor die and other dies. Eliminating the design power (TDP) by up to 70%, and area efficiency by package, therefore, has the potential to increase bandwidth a factor of 5 to 18. Further, silicon chips have scaled well by at least an order of magnitude(Section II). Similarly, while packages have not. We propose packageless processors - processors where packages have been removed and dies processor packages are much bigger than the processor itself directly mounted on a silicon board using a novel integra- (5 to 18 times bigger). Removing the processor package tion technology, Silicon Interconnection Fabric (Si-IF).