A Simple Analytical Switching Loss Model for Buck Voltage Regulators

Wilson Eberle, Zhiliang Zhang, Yan-Fei Liu, P.C. Sen Queen’s Power Group, www.queenspowergroup.com Department of Electrical and Computer Engineering, Queen’s University, Kingston, Ontario, Canada, K7L 3N6 [email protected], [email protected], [email protected], [email protected]

Abstract: In this paper, a simple and accurate analytical switching loss inductance and load current on switching loss is necessary. model is proposed for high frequency synchronous buck voltage This is most easily accomplished through careful examination regulators. The proposed model uses simple equations to calculate the rise and fall times and uses piecewise linear approximations of the high side of waveforms through simulation and experiments, which are MOSFET voltage and current waveforms to allow quick and accurate included in section II following the approach presented in [8]. calculation of switching loss in a synchronous buck voltage regulator. In section III, a new switching loss model is proposed with Effects of the common source inductance and other circuit parasitic the goal of maintaining the relative simplicity of the very inductances are included. Spice simulations are used to demonstrate the accuracy of the voltage source driver model operating in a 1MHz popular conventional model in [1], while improving the synchronous buck voltage regulator at 12V input, 1.3V output. Switching accuracy for high frequency synchronous buck with parasitic loss was estimated with the proposed model and measured with Spice for circuit inductances, including common source inductance. In load current ranging from 10-30A, common source inductance ranging particular, the model predicts the large decrease in turn on loss from 250-1000pH, voltage driver supply ranging from 6-12V. and increase turn off loss that occurs as undesired circuit I. INTRODUCTION parasitic inductance increases. Model verification using Spice In order to optimally design a high frequency switching simulation is presented in section IV. converter, engineers and researchers begin their design by II. IMPACT OF PARASITIC INDUCTANCE AND LOAD CURRENT estimating the losses in a design file that is typically created using a spreadsheet, or other mathematical software. Device A synchronous buck is illustrated in Fig. 1. In a synchronous data sheet values and analytical models are used to calculate buck VR, it is well known that the input voltage, load current the losses. Using the loss models, many design parameters and and HS MOSFET gate-drain charge influence switching loss components are compared to achieve a design with the optimal in the HS MOSFET. However, it is not well known that the combination of efficiency and cost. inductances associated with the device packaging and PCB Analytical models are math based. Most often, piecewise traces also contribute significantly to HS MOSFET switching linear turn on and turn off waveforms are used, or simplified loss. It is worth noting that with proper dead time, the SR equivalent circuits are used to derive switching loss equations. switches with near zero switching loss. These methods yield closed form mathematical expressions The synchronous buck in Fig. 1 includes parasitic drain and that can be easily used to produce optimization curves within a source inductances for the high side (HS) MOSFET, M1, and design file, however the challenge is to improve accuracy synchronous rectifier (SR) MOSFET, M2. It can be assumed while minimizing complexity. Most often, piecewise linear that the source inductances, Ls1 and Ls2 are common to their turn on and turn off waveforms are used, or simplified respective drive signals. Any other inductance in the source equivalent circuits are used to derive switching loss equations. that is not common to the driver is assumed to be lumped with One of the most popular analytical models is the piecewise the drain inductances, Ld1 and Ld2. These inductances have a linear model presented in [1]. This model is referred to as the significant impact on the switching loss behavior in high conventional model and is used as a benchmark later for frequency synchronous buck voltage regulators. v ' comparison purposes with the proposed model. This model ds1 v ds1 ids1 L i enables simple and rapid estimation of switching loss, d ' L L s ' f Lf 1 d1 d1 s1 s1 1 however, the main drawback is that it neglects the switching v v d ' i Ld1 vgs1 Ls1 2 ds2 loss dependences due to common source inductance and other M M1 2 circuit inductances. Typically, this model predicts that turn on Ld 2 vLd 2 g1 vgs1' I and turn off loss are nearly similar in magnitude, however in a C o d2 f Vo real converter operating at a high switching frequency, the Vin g2 model is highly inaccurate since turn off loss is much greater. vds2 vds2 '

An analytical model is presented in [2]. This model is an vgs2 s2 extension of the model presented in [3], with the advantage v ' gs2 L that it provides accurate characterization of switching loss s2 vLs2 including common source inductance. The main drawback of s2 ' the models in [2] and [3] is their complexity. The synchronous buck remains the topology of choice for Fig. 1. Synchronous buck voltage regulator with parasitic inductances voltage regulators (VRs) in today’s computers [4]-[7]. During the switching transitions, the HS MOSFET operates However, in order to properly model switching loss in a buck in the saturation (linear) mode as a dependent current source VR, a detailed understanding of the impact of MOSFET gate simultaneously supporting the current through the device and capacitance, common source inductance, other parasitic voltage across it. At turn on and turn off, the gate-source

978-1-4244-1874-9/08/$25.00 ©2008 IEEE 36 voltage, vgs1, is held at the plateau voltage, Vpl, by the feedback values for common package types are provided by the mechanism provided by the voltage across the common source semiconductor manufacturers in application notes [9]-[10] and inductance, vLs1. range from approximately 250pH-2nH, depending on the Using the circuit in Fig. 1, at turn on, as the HS MOSFET package type. Matched inductances of 500pH each for the four current increases, vLs1 is positive in the direction noted, so this inductances were used in the simulation. The vgs1 (Actual) and voltage subtracts from the Vcc voltage applied to the gate vgs1’ (Measured; vgs1’’=vgs1+vLs1) waveforms are included in enabling vgs1=Vpl while the MOSFET operates in the saturation Fig. 2 to demonstrate that measuring vgs1’ in the lab provides mode. At the same time, the four parasitic inductances provide an inaccurate representation of the switching times. a current snubbing effect, which virtually eliminates turn on ids1 switching loss enabling a near zero current switching (ZCS).

During this transition, the rise time, tr, is dictated by the gate vds1 Current [A] driver’s ability to charge the MOSFET gate capacitances (Ciss Voltage [V] from Vth to Vpl and Cgd to Vin), which is the time for vds1 to fall to zero. Then, it is assumed that this time is independent of the vgs1 ' time it takes ids1 to rise to its final value equal to the buck vgs1 inductor current. i.e. after tr, ids1 can be less than the buck Vth Voltage [V] inductor current (Io-ΔiLf). Gate-Source t f At turn off, as the HS MOSFET current decreases, vLs1 is negative in the direction noted Fig. 1, so this voltage subtracts tr from the low impedance source voltage (ideally zero volts) PM1 applied to the gate enabling vgs1=Vpl while the MOSFET Power [W] operates in the saturation mode. During this transition, the fall time, tf, is the time for the HS MOSFET current to fall from the buck inductor current to zero. This time is dictated by both Fig. 2. Synchronous buck voltage regulator HS MOSFET waveforms (top: the gate driver’s ability to discharge the MOSFET gate actual drain-source voltage, vds1 and drain current, ids1; middle: measured gate-source voltage, v ’ and actual gate-source voltage capacitances (Cgd from Vin, and Ciss from Vpl to Vth) and by the gs1 (bold), vgs1; bottom: HS MOSFET power, vds1ids1) four parasitic inductances, which prolong the time for ids1 to To demonstrate the effects of load current and common fall to zero by limiting the dids/dt. As alluded to in the two paragraphs above, the MOSFET and source inductance, experimental testing was done at a reduced trace parasitic inductances have vastly different effects at turn frequency of 200kHz, with the source connection cut and a on and turn off. At turn on, the inductances provide a current wire inserted in the common source path to measure the snubbing effect, which decreases turn on switching loss. At MOSFET current. Measurement waveforms are illustrated in turn off, the inductances increase the turn off loss by Fig. 3, and Fig. 4, where the load current has been increased from 0A to 5A. With this method, the inductance of the wire prolonging the fall time, tf. In addition, as load current increases, fall time increases, so turn off losses increase (approximately 20nH) is much greater than the approximate 2 total package inductance of 1nH, so the package inductance proportionally to Io (proportional to Io and tf(Io)). In contrast, at turn on, the load current magnitude has ideally no effect on can be neglected allowing for measurement of vgs1 and vds1. It the rise time. Therefore, in real circuits, turn off loss is much is noted that as load increases, the rise time remains nearly greater than turn on loss. unchanged from 20ns to 22ns, but the fall time increases Another important point to note from Fig. 1 is that in a real significantly from 48ns to 96ns. In addition, at a constant load circuit, the board mounted packaged inductances are current of 5A, as illustrated in Fig. 5, as Ls1 increases with a distributed within the MOSFET devices. Therefore, when longer 3 inch wire (approximately 30nH), tr remains relatively probing in the lab, one only has access to the external unchanged from 22ns to 24ns, while tf further increases from 96ns to 160ns. terminals, g1, s1’ and d1’ for the HS MOSFET and g2, s2’ and From knowledge of the circuit operation and observation of d2’ for the SR. However, the actual nodes that provide waveform information relevant to the switching loss are at the the experimental results presented, three important observations and conclusions can be made: unavailable internal nodes s1 and d1 for the HS MOSFET. Using the plateau portion of the measured gate-source voltage, 1) In a practical synchronous buck voltage regulator, turn off loss is much greater than turn on loss since the circuit vgs1’ to determine the switching loss times is misleading since inductances provide a current snubbing effect, which the induced voltage across Ls1 is included. Probing vgs1’ in the lab, one would observe a negligible rise time at turn on, and a decreases and virtually eliminates turn on switching loss, but increases the turn off loss by prolonging the t . fall time less than one half of the actual tf. The actual vgs1 f waveform, which cannot be measured in a real circuit, more 2) tr, is dictated by the time for the voltage to fall to zero and clearly illustrates the plateau portions in the rise and fall times. is independent of the final value of the current. In Simulation waveforms are illustrated in Fig. 2 for a buck addition, load current has negligible impact on rise time, voltage regulator at 12V input, 30A load, 8V drive voltage and while common source inductance has only a small impact, 1MHz switching frequency. Typical, parasitic inductance since as Ls1 increases, the current dids/dt decreases. 3) tf is dictated by the time for the current to fall to zero.

37 Load current, common source inductance and other circuit Vds_spec, Crss_spec, Coss_spec and Ciss_spec.

parasitic inductances (i.e. Ld1, Ls2, and Ld2) increase tf. Vds _ spec C gd = 2Crss _ spec (1) Vin i ds1 Vds _ spec (2) vds1 Coss = 2Coss _ spec Vin

Cds = Coss − C gd (3)

Ciss = Ciss _ spec (4)

t f Cgs = Ciss − Cgd (5) tr vgs1 Vpl ids1 ce

r I I Vpl rr off ΔiLf Δi1 f Io Vp vds1 Ion ain-Sou Δids r Current [A] Voltage [V] Vin Fig. 3. Switching waveforms at 0A load and 20nH common source D Δt inductance (80ns/div; vds1: 10V/div; ids1: 5A/div; vgs1: 5V/div)

vgs1 vds1 V Vth Vpl pl Vth

i Voltage [V] ds1 Gate-Source t 1r t1 f t2r t t t 2 f r f Fig. 6. Synchronous buck HS MOSFET waveforms with piecewise linear tr t f v approximations of these waveforms in bold V gs1 pl A. Turn On Switching Loss Model Vpl Using the piecewise linear geometry for the voltage and current waveforms at turn on in Fig. 7, the turn on loss is

Fig. 4. Switching waveforms at 5A load and 20nH common source approximated using (6). During the rise time, the average HS inductance (80ns/div; vds1: 10V/div; ids1: 5A/div; vgs1: 5V/div) switch voltage is 0.5Vin, while the average current is 0.5Ion. The linearized power loss in (6) is the product of the average v ds1 voltage, average current, switching frequency and rise time. The two parameters that are key to accurate prediction of Pon ids1 are the current at turn on, Ion and the rise time, tr.

Irr Δids / Δt I t t f on r v gs1 ids1 Vpl Vpl 0.5Ion

t Fig. 5. Switching waveforms at 5A load with 30nH common source inductance (80ns/div; v : 10V/div; i : 5A/div; v : 5V/div) vds1 Vin ds1 ds1 gs1 0.5V V1r in III. PROPOSED SWITCHING LOSS MODEL Typical switching waveforms for a synchronous buck VR are illustrated in Fig. 6. The proposed model uses the t1r piecewise linear approximations (noted with thicker bold vgs1 Vplon lines) of the switching waveforms in Fig. 6. Turn on switching Vth t2r loss occurs during tr and turn off switching loss occurs during t tf. The key to the model is prediction of the turn on current, Ion, r the rise and fall times, tr and tf, the reverse recovery current, Fig. 7. Synchronous buck HS MOSFET waveforms at turn on with piecewise linear approximations Irr, the magnitude of the rising current slope, Δids/Δt, and the current drop, Δi , when v rises to V at turn off. The goal of P = 0.25V I t f 1f ds1 in on in on r s (6) the proposed model is to predict the switching loss trends vs. As discussed in section II, the rise time, tr, is dictated by the load current, driver supply voltage, driver gate current and gate driver’s ability to charge the MOSFET gate capacitances, total circuit inductance in a simple manner. which is the time for vds1 to fall to zero. This time is assumed The MOSFET parasitic capacitances are required in the independent of the time it takes ids1 to rise to its final value. model. They are estimated using the effective values [1] as Under this assumption, the rise time consists of two intervals, follows in (1)-(5) using datasheet specification values for t1r and t2r as given by (7).

38 t r = t1r + t 2r (7) Using (8) and (13)-(15), solving for t1r yields (16), where The HS MOSFET equivalent circuit during t1r is given in Vgs1r=0.5(Vplon+Vth). t = t + t Fig. 8. The gate resistance, Rr, represents the total series r 1ra 1rb resistance in the gate drive path, i.e. R =R +R +R , where R ΔVgsr (Ls1g fs + RrCiss1 ) r hi ext g hi t = is the resistance of the driver switch, R is any external 1ra ext 2Vgs1r (16) resistance and R represents the internal gate resistance. g [ΔV (L g + R C )]2 + 4ΔV (V −V )R C L g V gsr s1 fs r iss1 gsr cc gs1r r rss1_ spec loop fs in t1rb = 2Vgs1r Δids L + L + L vgs1 d1 s2 d 2 Δt V C pl gd1 Rr V 0.5(V +V ) d1 th plon th R r t v 1r C ds1 I g1r ds1 Vcc vgs1 = 0.5(Vplon +Vth ) Vcc I g1r s1 Cgs1 v = L Δi / Δt Ls1 Ls1 s1 ds

Fig. 8. Synchronous buck HS MOSFET equivalent circuit during t1r Fig. 9. Driver equivalent circuit during t1r

During t1r, the Cgs1 capacitance is charged from Vth to Vplon, During t2r, the gate voltage of the Cgd1 capacitance remains while the gate side of Cgd1 charges from Vth to Vplon and the constant at Vplon, while the drain of Cgd1 is discharged by drain side of the Cgd1 capacitance discharges from Vin to V1r. current Ig2r, allowing t2r to be given by (17). Therefore, the change in voltage across Cgd1 during t1r is [(Vin- Cgd1V1r t2r = (17) V )+(V -V )]. Then, t is given by (8), assuming an average I 1r plon th 1r g 2r gate charging current Ig1r, where Vplon is given by (9), and The driver equivalent circuit during t2r is illustrated in Fig. 9. ΔVgsr=Vplon-Vth. Due to the assumed constant Δids/Δt, the Ls1 inductance is Cgs1ΔVgsr + C gd1[ΔVgsr + (Vin −V1r )] replaced by an ideal voltage source. Under these assumptions, t1r = (8) I g1r the gate current is given by (18). I − 0.5Δi Rr o Lf vgs1 V plon = Vth + (9) g fs Vplon I g 2r The drain-source voltage during t1r is given by (10), where Vcc vgs1 = Vplon Lloop= Ls1+Ld1+Ls2+Ld2. t2r dids1 vds1 = Vin − Lloop (10) v = L Δi / Δt dt Ls1 s1 ds Neglecting the gate current through the inductances, the rate Fig. 10. Driver equivalent circuit during t of change of current in (10) is given by (11), which is 2r Δi approximated by (13) using (12) and the piecewise linear V −V − L ds cc plon s1 Δt (18) approximation of the gate-source voltage waveform during t1r. I = g 2r R di dg (v −V ) g dv r ds1 = fs gs1 th = fs gs1 (11) dt dt dt Using (13),(14),(16),(17) and (18), solving for t2r yields (19). di Δi ⎛ ΔVgsr ⎞ ds ds R C ⎜V − L g ⎟ ≈ (12) r gd1 ⎜ in loop fs ⎟ dt Δt t1r t = ⎝ ⎠ (19) g Δv g ΔV 2r Δids fs gs1 fs gsr ΔVgsr = = (13) Vcc −V plon − Ls1 g fs Δt Δt t1r t1r Using (10)-(13), V1r is given by (14). The final step to determine the turn on loss is to estimate g fs ΔVgsr the current Ion at the end of tr. Depending on the load current V1r = Vin − Lloop (14) t1r and parasitic inductances, Ion can require calculation of the The driver equivalent circuit during t1r is illustrated in Fig. 8. reverse recovery current, Irr. The waveform in Fig. 11 is used During this time interval, it is assumed that vgs1 is the average to estimate Irr. When the HS MOSFET turns on, the SR body value of the plateau, Vplon, and threshold voltages, Vth. In diode cannot reverse block, so the SR current goes negative addition, in the proposed model, the slope of the drain current and the HS current spikes by the same magnitude. The total reverse recovery time is t . The rising slope magnitude is is assumed constant; therefore the voltage vLs1=Ls1Δids/Δt is rr constant, so the Ls1 inductance is replaced by an ideal voltage Δids/Δt and the reverse recovery charge is Qrr, which source in the drive circuit. The gate current is given by (15). represents the shaded area as given by (20). Using the Δi geometry, the reverse recovery current as a function of trr is V − 0.5(V +V ) − L ds cc plon th s1 given by (21). Then, eliminating t from (20) and (21), (23) is I = Δt (15) rr g1r R derived, which represents I as a function of Q and the r rr rr known slope. In addition, since reverse recovery charge

39 increases with load current, Qrr is approximated using (22), circuit parasitic inductances which limit the falling time. It where Qrr_spec and Irr_spec are the datasheet specification values. consists of two components, t1f and t2f as given by (27). t1f is 1 the time required to discharge the Cgd1 capacitance by gate Qrr = I rr trr (20) 2 current Ig1f as given by (28). ΔI ds 1 t = t + t I = t (21) f 1 f 2 f (27) rr Δt 2 rr Cgd1Vin Qrr _ spec t1 f = (28) Q = I I rr o (22) g1 f I rr _ spec Vp 0.5(V +V ) ΔI in p ds vds1 I rr = Qrr (23) Vin Δt 0.5Vin t Qrr Irr Ioff Δi1 f Ioff − 0.5Δi1 f I f = Ioff − Δi1 f

Δids / Δt 0.5trr ids1 trr 0.5(Ioff − Δi1 f ) ids1 t t Fig. 11. Synchronous buck HS MOSFET current waveform approximation 1 f during reverse recovery at turn on Since the rise time is dictated by the time for the HS t vgs1 2 f MOSFET voltage, vds1, to fall to zero, the current at the end of Vploff Vth tr can be at any value equal to, or less than the inductor current plus the reverse recovery current (i.e. I is not necessarily on t equal to the inductor current, as in the conventional model [1], f Fig. 12. Synchronous buck HS MOSFET waveforms at turn off with or the inductor current plus the reverse recovery current). piecewise linear approximations Therefore, the current at the end of tr is give by (24). The driver equivalent circuit during t1f is illustrated in Fig. Δids Δids Ion = tr if tr < Io − 0.5ΔiLf + I rr 13. During this time interval, it is assumed that v remains Δt Δt (24) gs1 = I − 0.5Δi + I otherwise constant at the plateau, Vploff. As above, the Ls1 inductance is o Lf rr replaced by an ideal voltage source; however the current slope

B. Turn Off Switching Loss Model during this interval is approximated as Δi1f/t1f. Under these Using the piecewise linear geometry for the voltage and assumptions, the gate current is easily derived as given by (29) current waveforms at turn off in Fig. 12, the turn off loss is where Rf=Rlo+Rext+Rg, and Vploff is given by (30). approximated using (25), which consists of two intervals with R f vgs1 different falling current slopes during t1f and t2f. The first Vploff component of the power loss is during t1f. During t1f, the I g1 f average HS switch voltage is (1/2)Vin, while the average vgs1 =Vploff current is [Ioff-(1/2)Δi1f]. In the second interval, t2f, the average t1 f Δi1 f HS switch voltage is (1/2)(Vin+Vp), while the average current vLs1 = Ls1 t1 f is (1/2)(Ioff- Δi1f). The linearized power loss in (25) is the sum of the power in the two intervals consisting of the product of Fig. 13. Driver equivalent circuit during t1f the average voltage, average current, switching frequency and Δi1 f V plon − Ls1 fall time interval. t1 f (29) I g1 f = Poff = 0.5Vin (I off − 0.5Δi1 f )t1 f f s + 0.25(Vin + V p )(I off − Δi1 f )t2 f f s (25) R f The parameters that are key to accurate prediction of the turn I o + 0.5ΔiLf V plon = Vth + (30) off loss are the HS MOSFET current at turn off, Ioff, the value g fs of the current drop, Δi1f during the first falling slope interval The fall time, t1f, during this interval is given by (31) using t1f, and the duration of the second interval t2f and the peak (28) and (29), overshoot voltage of vds1, Vp. The turn off current is the load C gd1Vin R f current, Io, plus half of the filter inductor peak-to-peak ripple t1 f = Δi1 f (31) current, Δi as: V ploff − Ls1 Lf, t 1 f I off = I o + 0.5ΔiLf (26) The turn off loss estimated using (25) is a function of the fall In (31), the current drop, Δi1f is unknown, so we cannot solve time, t . The fall time occurs for the duration of the current for t1f. In order to estimate Δi1f, we use the synchronous buck f equivalent circuit given in Fig. 14. As previously stated, falling from Ioff to zero. It is a function of the driver capability during t1f, the voltage across the HS switch rises linearly from to discharge Cgd1 and Ciss, but in addition, it is a function of

40 zero to Vin. Additionally, the voltage across the synchronous Δi1f. Under these assumptions, the gate current is given by rectifier drops from Vin to zero as the Cds2 and Cgd2 capacitors (37). discharge into the d2 node. During this interval, the current 1 I (V +V ) − L f decrease in i is equal to the increase in current through C pl th s1 ds1 gd2 2 t2 f (37) I = and C . Neglecting the drive circuits, the current drop of Δi g 2 f ds2 1f R f is estimated using the increase in discharging current in Cgd2 Using (34), (36) and (37), solving for t2f yields (38), where and Cds2 as given by (32). Vgs2f=0.5(Vploff+Vth). Vin t2 f = t2 fa + t2 fb L I + ΔV R C ids1 d1' s1 f gs2 f f iss1 t2 fa = 2Vgs2 f (38) L v d1 Ld1 2 [Ls1I f + ΔVgs2 f R f Ciss1] + 4ΔVgs2 f Vgs2 f R f Cgd1Lloop g fs t2 fb = C 2V gd1 d1 gs2 f R f v vgs1 g1 ds1 Cds1

Cgs1 s1 Vploff 0.5(Vploff +Vth ) Vth Rf Ls1 vLs1 t I + 0.5Δi 2 f o Lf I s1' g 2 f vgs1 = 0.5(Vploff +Vth ) v Ld 2 Ld 2 I v = L f Ls1 s1 t C d 2 f gd 2 2 Vin Fig. 15. Driver equivalent circuit during t g2 vds2 C 2f Cds2 ds2 t1 f s2 IV. MODEL VERIFICATION Vin The analytical switching loss model with a voltage source Cgd 2 t isd 2 1 f Ls2 vLs2 drive was compared to SIMetrix Spice simulation and the conventional model in [1]. Results were calculated at 12V Fig. 14. Synchronous buck equivalent circuit during turn off during t1f input, 1MHz switching frequency, and 10A peak-to-peak V inductor ripple (100nH), Rhi=2Ω, Rlo=2Ω, Rg=1.5Ω, Rext=0Ω. Δi = (C + C ) in 1 f gd 2 ds2 (32) Results are included in the following sub-sections for both t1 f models. MOSFET parameters: Si7860DP HS and Si7336ADP Using (31) and (32), solving for t1f yields (33). 2 SR; Vth=2V, Vds_spec1=15V, Crss_spec1=175pF, Coss_spec1=500pF, Cgd1Vin R f + (Cgd1Vin R f ) + 4Vploff Ls1Vin (Cgd 2 + Cds2 ) Ciss_spec1=1800pF (model). t1 f = (33) 2V ploff Curves of total switching loss vs. common source inductance During t2f, the Cgs1 capacitance is discharged from the (assuming matched inductances; i.e. Ls1=Ld1=Ls2=Ld2) for the plateau voltage to the threshold, while the drain side of the proposed model, Spice simulation and the conventional model Cgd1 capacitance charges from Vin to Vp and the gate side of are given in Fig. 16. The proposed model follows the trends of Cgd1 discharges from Vploff to Vth. Therefore, the change in the Spice simulation results very well. The accuracy of the voltage across Cgd1 during t2f is [(Vp-Vin)+(Vploff-Vth)]. Then, t2f proposed model total switching loss is within 0.5W. In Fig. 16, is given by (34), where ΔVgsf=Vploff-Vth . it is noted that the conventional model does a very poor job C ΔV + C [(V −V ) + ΔV ] predicting the total switching loss as total circuit inductance t = gs1 gsf gd1 p in gsf 2 f (34) increases. In particular, at 1000pH, the conventional model I g 2 f predicts 1.5W loss, while the Spice results indicate total The drain-source voltage during t2f is given by (35), where switching loss of 3.4W – a difference of 1.9W. Lloop= Ls1+Ld1+Ls2+Ld2. Curves of total switching loss vs. load current for the dids1 vds = Vin + Lloop (35) dt proposed model, Spice simulation and the conventional model Following the approach of the approximations made in (11) are given in Fig. 17. The proposed model follows the trends of the Spice simulation results very well. The accuracy of the and (12), the peak overshoot voltage, Vp is given by (36). proposed model total switching loss is within 0.5W. In Fig. 17, g fs ΔVgsf V p = Vin + Lloop (36) t it is noted that the conventional model does a very poor job 2 f predicting the total switching loss as the load current The driver equivalent circuit during t is illustrated in Fig. 2f increases. In particular, at 30A, the conventional model 16. During this time interval, it is assumed that v is the gs1 predicts 2.2W loss, while the Spice results indicate total average value of the plateau, V , and threshold voltages, V . ploff th switching loss of 4.2W – a difference of 2.0W. As above, the L inductance is replaced by an ideal voltage s1 Curves of total switching loss vs. driver supply voltage for source, where the di /dt is assumed constant at I /t and I =I - ds f 2f f off the proposed model, Spice simulation and the conventional

41 model are given in Fig. 18. The proposed model follows the V. CONCLUSIONS trends of the Spice simulation results very well. The accuracy The switching loss characteristics and behavior in a high of the proposed model total switching loss is within 0.1W. frequency synchronous buck VR have been reviewed. 5.0 Vcc=8V, Io=20A Following the demonstrated switching loss characteristics, a Spice Simulation new simple and practical analytical switching loss model has 4.5 Proposed Model 4.0 Conventional Model been proposed for voltage source drivers. The model quickly 3.5 and accurately predicts the switching loss in a high frequency synchronous buck voltage regulator. The model uses 3.0 piecewise linear approximations of the actual vds1 and ids1 2.5 switching waveforms. The average value of the piecewise 2.0 waveforms are then used to provide expressions for the turn on 1.5 and turn off loss including the effects of common source 1.0 inductance and other parasitic inductances. Total Switching Loss [W] Loss Switching Total 0.5 To verify the proposed model, it was compared to Spice 0.0 simulation results. It was demonstrated that the proposed 250 500 750 1000 model follows the trends in turn on and turn off switching loss Common Source Inductance [pH] for variations in load current, driver supply voltage and total Fig. 16. Total switching loss at 1MHz, 12V input vs. common source circuit circuit inductance. The accuracy of the proposed voltage inductance (Vcc=8V, Io=20A) source drive model was demonstrated to be within 0.5W for 5.0 Ls1=500pH, Vcc=8V calculation of the total switching loss. Spice Simulation 4.5 Proposed Model REFERENCES 4.0 Conventional Model [1] L. Balogh, “Design And Application Guide for High Speed MOSFET Gate Drive Circuits,” 2001 TI Power Design Seminar, slup169.pdf. 3.5 [2] Y. Ren, M. Xu, J. Zhou, and F.C. Lee, “Analytical Loss Model of Power 3.0 MOSFET,” IEEE Trans. Power Electronics, Vol. 21, No.2, pp. 310-319, 2.5 March 2006. [3] D.A. Grant and J. Gower, “Power MOSFET Theory and Applications,” 2.0 Chapter 3, New York, Wiley, 1989. 1.5 [4] Z. Yang, S. Ye and Y.F. Liu, “A New Resonant Gate Drive Circuit for 1.0 Synchronous Buck Converter,” IEEE Trans. Power Electronics, Vol. 22,

Total SwitchingTotal [W] Loss No. 4, July 2007, pp. 1311-1320. 0.5 [5] X. Wang, I. Batarseh, S.A. Chickamenahalli, E. Standford, “VR Transient 0.0 Improvement at High Slew Rate Load – Active Transient Voltage 10 15 20 25 30 Compensator,” IEEE Trans. Power Electronics, Vol. 22, No. 4, July 2007, Load Current [A] pp. 1472-1479. [6] Q. Zhao, G. Stojcic, “Characterization of Cdv/dt Induced Power Loss in Fig. 17. Total switching loss at 1MHz, 12V input vs. load current (V =8V, cc Synchronous Buck DC-DC Converters,” IEEE Trans. Power Electronics, L =500pH) s1 Vol. 22, No. 4, July 2007, pp. 1505-1513. 5.0 Ls1=500pH, Io=20A [7] Y. Qiu, J. Sun, M. Xu, K. Lee and F.C. Lee, “Bandwidth Improvements Spice Simulation for Peak-Current Controlled Voltage Regulators,” IEEE Trans. Power 4.5 Proposed Model Electronics, Vol. 22, No. 4, July 2007, pp. 1253-1260. 4.0 Conventional Model [8] A. Elbanhawy, “Buck Converter Losses Under the Microscope,” Power 3.5 Electronics Technology Magazine, pp. 24-32, February 2005. [9] M. Pavier, A. Woodworth, A. Green, R. Monteiro, C. Blake, J. Chiu, 3.0 “Understanding the Effects of Power MOSFET Package Parasitics on 2.5 VRM Circuit Efficiency at Frequencies above 1MHz,” International 2.0 Rectifier Application Note, www.irf.com. [10] J. Lee, “Package Parasitics Influence Efficiency,” Power Electronics 1.5 Technology Magazine, pp. 14-21, November 2005. 1.0

Total Switching [W] Loss 0.5 0.0 6 8 10 12 Driver Supply Voltage [V] Fig. 18. Total switching loss at 1MHz, 12V input vs. driver supply voltage (Ls1=500pH, Io=20A)

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