Timing of Load Switches

Application Report SLVA883–April 2017

Nicholas Carley...... Power Switches

ABSTRACT Timing of load switches can vary depending on the operating conditions of the system and feature set of the device. At a glance, these variations can seem complex; but, when broken down, each operating condition and feature has a correlation to a change in timing. This application note goes into detail on how each condition or feature can alter the timing of a load switch so that the variations can be prepared for.

Contents 1 Overview and Main Questions ...... 2 1.1 Definition of Timing Parameters ...... 2 1.2 Alternative Timing Methods ...... 2 1.3 Why is My Rise Time Different than Expected? ...... 3 1.4 Why is My Fall Time Different than Expected? ...... 3 1.5 Why Do NMOS and PMOS Pass FETs Affect Timing Differently?...... 3 2 Effect of System Operating Specifications on Timing...... 5 2.1 Temperature...... 5 2.2 Load Resistance ...... 6 2.3 Load Capacitance ...... 7 2.4 Input Voltage ...... 7 3 Effects of Device Features on Timing...... 7 3.1 Slew Rate ...... 8 3.2 Bias Voltage ...... 9 3.3 Quick Output Discharge ...... 10 4 Conclusion ...... 11 5 References ...... 11

List of Figures

1 tDELAY, tON, tOFF, tRISE, and tFALL Waveforms ...... 2 2 Alternative Timing Waveform ...... 3 3 Voltages on NMOS FET ...... 4

4 TPS22975 tRISE and tDELAY Across Temperature ...... 5

5 TPS22975 FALL Across Temperature...... 5

6 TPS22918 tRISE and tDELAY Across Temperature ...... 6

7 TPS22918 tFALL Across Temperature ...... 6

8 RFET and RLOAD Voltage Divider ...... 6

9 TPS22976 tRISE vs VINPUT ...... 7

10 TPS22976 tDELAY vs VINPUT ...... 7

11 TPS22958 tR vs VIN With Changing CT ...... 8

12 TPS22976 tDELAY vs VINPUT ...... 9

13 TPS22976 tDELAY vs VINPUT ...... 9

14 TPS22958 tRISE vs VBIAS ...... 9

15 TPS22953 tRISE vs VBIAS ...... 10 16 QOD - Constant Current ...... 10

SLVA883–April 2017 Timing of Load Switches 1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Overview and Main Questions www.ti.com 17 QOD - Resistive Pull-Down ...... 10

1 Overview and Main Questions

1.1 Definition of Timing Parameters First, let’s look at the key behaviors of a load switch and how they relate to timing parameters. See Figure 1.

• Delay time, tDELAY, accounts for the time required to prepare the subsystems of a load switch before the pass FET can be turned on. Delay time is defined as the time from the device being enabled until VOUT starts to rise (typically to 10%).

• Rise time, tRISE, is set by the slew rate of the load switch. Rise time is defined as the time for VOUT to rise from 10% to 90%. The 10% and 90% marks are used for higher test and measurement accuracy during device characterization.

• Fall time, tFALL, is heavily affected by the load resistance and load capacitance but can be influenced by devices with quick output discharge. Fall time is defined as the time for VOUT to fall from 90% to 10%. The 90% and 10% marks are used for higher test and measurement accuracy during device characterization.

• On time, tON, represents the time for a switch to turn on. tON is typically defined as a combination of tDELAY and tRISE but can vary based on the test methodology used for each device. For this app note, tON will be defined as tDELAY + tRISE.

• Off time, tOFF, represents the time for a switch to turn off but varies based on the test methodology used for each device. For this app note, tOFF will be defined as the time from the device being disabled until VOUT begins to fall (90%).

VIH VON tON tOFF VIL

tRISE tFALL

90% tDELAY 90%

VOUT

10% SRON 10%

Figure 1. tDELAY, tON, tOFF, tRISE, and tFALL Waveforms

1.2 Alternative Timing Methods The definitions above are the way the timing parameters will be addressed in this app note, but there are other ways of defining the above parameters. The waveform in Figure 2, shows:

• Delay time as the enable signal at 50% until VOUT rises to 10%.

• On time as the enable signal at 50% until VOUT rises to 50%.

• Off time as the enable signal at 50% until VOUT falls to 50%.

• Rise time as VOUT rising from 10% to 90%.

• Fall time as VOUT falling from 90% to 10%.

50% VON tON 50% tOFF

t tRISE FALL

90%

90% t DELAY 50% VOUT

{w 50% 10% hb

10%

Figure 2. Alternative Timing Waveform

The on time for a device will be different depending on which method is used to calculate it. It is important to always double check the datasheet for how each device defines its timing.

1.3 Why is My Rise Time Different than Expected? Rise Time is affected by many operating conditions and external components around a load switch. The main factors are: Slew Rate, Load Resistance, Input Voltage and Bias Voltage. The slew rate of the device controls how quickly the output rail ramps up to the input rail when the device turns on. The load resistance, with respect to the decreasing FET resistance, determines the point at which the output rail reaches 90% of the input. Input voltage is directly proportional to rise time, a higher input voltage results in a higher rise time. Bias voltage powers the charge pump which can improve rise time if the bias voltage is higher than the input voltage.

1.4 Why is My Fall Time Different than Expected? Fall time is affected by Load Capacitance and Quick Output Discharge (part dependant). When a load switch is turned off the charge on the load capacitance needs to be discharged to bring the output rail down. Load resistance and load capacitance are directly proportional to the fall time based on RC capacitive discharging. Quick Output Discharge can be used to increase the current being pulled out of the load capacitance. Quick Output Discharge has a larger impact on discharging the load capacitance the larger the load resistance is.

1.5 Why Do NMOS and PMOS Pass FETs Affect Timing Differently? NMOS and PMOS pass FETs behave differently while the FETs are turning on. NMOS rise time is less affected by external components (load resistance and load capacitance) while the rise time of PMOS is almost exclusively controlled by external components. NMOS pass FETs have 4 key voltage parameters during turn on: input voltage, output voltage, gate

voltage, and the VGS threshold voltage. See Figure 3. The output starts at 0 V, rises to, and stops at the input voltage when the FET is fully on. The VGS threshold voltage is the difference in voltage needed between the gate voltage and the output voltage for the output to begin to rise, the VGS threshold voltage is typically around 0.7 V.

VIN VOUT

VGS +

VGATE Figure 3. Voltages on NMOS FET

As the voltage on the gate begins to rise no change occurs at the output until the difference between the

gate and output equals the VGS threshold voltage. Once the VGS threshold voltage has been hit, both the gate and output voltages increase linearly and parallel to each other. Once the output has reached the input voltage the output stops increasing. PMOS pass FETs are pulled to ground to turnon. Once the gate voltage is low and the device turns on the input is immediately passed to the output. The amount of time it takes the gate voltage to reach 0V is typically uncontrolled or hard to control. This causes the output to very quickly rise up to the input voltage. Load resistance causes voltage division between the load and the FET resistance. A low load resistance results in a slower rise time while a high load resistance causes a quick rise time, See the Load Resistance section. The way the output of an NMOS pass FET increases is dependant on how quickly the gate voltage increases and is negligibly affected by load capacitance and resistance. The way the output of a PMOS pass FET increase is heavily dependant on the load on the switch.

4 Timing of Load Switches SLVA883–April 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated www.ti.com Effect of System Operating Specifications on Timing 2 Effect of System Operating Specifications on Timing Timing parameters of a load switch are affected by many typical operating conditions and system specifications such as: Temperature, Load Resistance, Load Capacitance, Input Voltage. The effect temperature has on the timing parameters can vary greatly from device to device depending on the

specific design architecture. A larger load resistance will reduce tRISE while increasing tFALL. A larger load capacitance increases tFALL based on RC capacitive discharging. Input voltage is directly proportional to tRISE. Section 2.1 through Section 2.4 cover each of these topics individually.

2.1 Temperature The two main subsystems of a load switch that are affected by temperature which result in a timing

change are the VGS threshold of the pass FET and the reference current of the charge pump. The VGS threshold of the pass FET decreases as temperature increases. The reduction in the VGS threshold reduces tDELAY. The reference current of the charge pump controls how quickly the gate will ramp and in turn how quickly the output will rise. Typically, as temperature increases the reference current increases which causes the gate of the pass FET to charge faster. The increase in the reference current causes a

reduction in both tDELAY and tRISE. The overall affect on the device from an increase in temperature, in the case of the TPS22975, reduces

tDELAY and tRISE, as shown in Figure 4; while tFALL is relatively constant, as shown in Figure 5. Both figures are based on the following parameters: VIN = 2.5 V, VBIAS = 2.5 V, and CT = 1000 pF. Regardless of which VIN, VBIAS, and CT values are used, the change in the timing parameters, for the TPS22975, due to temperature is consistent.

240 2.5 tDELAY tFALL 220 tRISE 2.45 2.4 200 2.35 180 2.3 s) s) m m 160 2.25

Time ( Time 140 Time ( 2.2 2.15 120 2.1 100 2.05 80 2 -45 -25 -5 15 35 55 75 95 115 -45 -25 -5 15 35 55 75 95 115 Temperature (°C) Temperature (°C) D001 D003

Figure 4. TPS22975 tRISE and tDELAY Across Temperature Figure 5. TPS22975 FALL Across Temperature

SLVA883–April 2017 Timing of Load Switches 5 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Effect of System Operating Specifications on Timing www.ti.com The overall affect on the device from an increase in temperature, in the case of the TPS22918, is different

than the TPS22975. As temperature increases: tDELAY linearly decreases while tRISE linearly increases, as shown in Figure 6. Fall time is relatively constant, as shown in Figure 7. Both figures are based on the

following parameters: VIN = 2.5 V and CT = 1000 pF. Regardless of which VIN and CT values are used, the change in the timing parameters, for the TPS22918, due to temperature is consistent.

1400 2.5 tDELAY tFALL tRISE 2.45 1200 2.4 2.35 1000 2.3 s) s) m m 2.25 Time ( Time 800 Time ( 2.2 2.15 600 2.1 2.05 400 2 -45 -25 -5 15 35 55 75 95 115 -45 -25 -5 15 35 55 75 95 115 Temperature °C Temperature °C D004 D005

Figure 6. TPS22918 tRISE and tDELAY Across Temperature Figure 7. TPS22918 tFALL Across Temperature The TPS22975 is an example of both the switching threshold and the reference current changing with

temperature resulting in a larger reduction of tDELAY and tRISE than the TPS22918. The TPS22918 is largely affected by the change in switching threshold, which is why tDELAY decreases with increasing temperature; but the TPS22918 has a relatively constant reference current over temperature which is why tRISE does not decrease with increasing temperature. The fact that tRISE increases on the TPS22918 is due to many small parasitic changes that occur with increasing temperature. Temperature also affects load resistance and load capacitance values. See the Load Resistance and Load Capacitance sections to see how they affect timing.

2.2 Load Resistance The internal FET of the load switch can simply be modeled as a non-linear potentiometer, which starts

typically in the 10s of MΩ and ends at RON(typically in 10s to 100s of mΩ). The FET resistance, RFET, and the load resistance, RLOAD, make a voltage divider circuit. See Figure 8.

VIN VOUT

RFET

RLOAD

Figure 8. RFET and RLOAD Voltage Divider

If the load resistance is 500 Ω - the FET resistance will reach 55.5 Ω in time X, creating a 90% voltage

divider resulting in tON. If the load resistance is 10 Ω - the FET resistance will still reach 55.5 Ω in time X but this creates a 15% voltage divider rather than a 90%. This means a lower load resistance results in a longer time for the output to finish ramping.

Load resistance also affects tFALL, as explained in Section 2.3.

6 Timing of Load Switches SLVA883–April 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated www.ti.com Effect of System Operating Specifications on Timing 2.3 Load Capacitance

As load capacitance and load resistance increase: tFALL increases. The larger the load resistance or load capacitance is, the longer it will take to discharge the capacitor, resulting in a longer fall time. Capacitance discharge follows Equation 1.

tFALL = -RL × CL × ln(V10%/V90%) Where

• V10% is 10% of the initial output voltage

• V90% is 90% of the initial output voltage

• RL is the load resistance

• CL is the load capacitance (1) All the energy stored in the load capacitance has to discharge through the load resistance, for example

let’s use: a 0.1-uF load capacitance, a 500-Ω load resistance, and initial VOUT = 5 V, see Equation 2.

tFALL = -500Ω × 0.1uF × ln(0.5V/4.5V) = 110µsec (2)

2.4 Input Voltage

As input voltage increases: tDELAY and tRISE increase. If the output rises at a constant rate, a higher voltage will take longer to reach. Rise time and delay time are directly proportional to input voltage.

For example, in the TPS22976, tRISE and tDELAY increase with increasing input voltage, see Figure 9 and Figure 10.

3000 800

2500 700 s) s) m m 2000 600

1500 500 Rise Time ( Time Rise Delay Time ( Time Delay

-40èC -40èC 1000 25èC 400 25èC 85èC 85èC 105èC 105èC 500 300 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Input Voltage (V) D010 D011

Figure 9. TPS22976 tRISE vs VINPUT Figure 10. TPS22976 tDELAY vs VINPUT

3 Effects of Device Features on Timing Timing parameters of a load switch are affected or controlled with device features such as: Slew Rate, Bias Voltage, and Quick Output Discharge. Slew rate directly controls the rise time of the load switch. Bias

voltage can affect tRISE and tDELAY but the way timing is affected is part specific. Quick Output Discharge can be implemented to reduce tFALL. Section 3.1 through Section 3.3 cover each of these topics individually in more detail.

SLVA883–April 2017 Timing of Load Switches 7 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Effects of Device Features on Timing www.ti.com 3.1 Slew Rate Slew rate is used to manually control the rise time of a device. Slew rate can be controlled by either selecting a part with an internally fixed slew rate or by selecting a part that has the ability to adjust the slew rate with external components. An example of a integrated load switch with adjustable slew rate is the TPS22975 which uses a CT pin. An equation for slew rate is given in each datasheet for parts that have an adjustable slew rate, Equation 3 is pulled as an example from the TPS22975 datasheet (SLVSDD0). This estimate does not apply for CT capacitor values less than 100 pF. For this device, values smaller than 100 pF have little describable impact on the slew rate because they are relatively small compared to the FET gate capacitance. Whereas a larger CT capacitance will be the dominant factor in determining the slew rate. This can be seen in Figure 11, the slopes of the CT = 0 pF and CT = 220 pF lines are marginally discernable from each other, showing minimal impact of a 220-pF CT capacitor over an open CT pin. In general, a lower CT capacitor value in this range results in higher deviation of the estimated slew rate from the actual slew rate as shown in Equation 3. SR = 0.43 × CT + 26 Where • SR = Slew Rate (in µs/V) • CT = The capacitance value of the CT pin (in µF) • The units for the constant 26 are µs/V. • The units for the constant 0.43 are us/(V × pF) (3) Equation 3 is an approximation. Slew rate can be affected by the tolerance of the CT or dV/dt capacitor and the board parasitics around the device. Selecting a CT or dV/dt capacitor tolerance with the application in mind can help reduce unwanted board-to-board rise time variation. Proper board layout is important due to the low value CT or dV/dt capacitor value (100 pF to 1000 pF) being used. Capacitance due to board traces or other planes can be in the 10s to 100s of pF and can affect the overall capacitance on the pin. The CT or dV/dt capacitor should have the shortest traces available between the pin and ground. Refer to the datasheet (SLVSDD0) for a board layout example. Slew rate affects rise time following Equation 4.

tRISE = VOUT × SR × 0.8 Where

• tRISE is the rise time (in µs)

• VOUT is the final output voltage (in V) • SR is the slew rate (in µs/V) • 0.8 constant accommodates the 10% to 90% definition (4)

Figure 11, from the TPS22958 datasheet (SLVSCX7), shows the change of tRISE across VIN with multiple slew rates due to different CT values ranging from 0 pF to 10 nF.

7000 CT=0pF 6000 CT=220pF CT=470pF CT=1000pF 5000 CT=2200pF CT=4700pF 4000 CT=10000pF s) m ( R t 3000

2000

1000

0 0 1 2 3 4 5 6 V (V) IN D027

Figure 11. TPS22958 tR vs VIN With Changing CT

Bias Voltage, VBIAS, can be utilized to reduce tRISE and tDELAY. VBIAS, when available, is used to power the charge pump. In order for VBIAS to affect tDELAY and tRISE, VBIAS must be higher than VIN. If VBIAS is equal to VIN, there will be no timing difference over just using VIN.

Figure 12 (VBIAS = 2.5V) and Figure 13 (VBIAS = 5 V) from the TPS22976 datasheet (SLVSDE7) show that a higher VBIAS results in a smaller delay time. Figure 12 only shows VIN up to 2.5 V because it is not advised to operate a load switch with VIN higher than VBIAS.

1600 800

1400 700

1200 600 s) s) m m 1000 500

800 400

600 300 Delay Time ( Time Delay Delay ( Time

400 -40èC 200 -40èC 25èC 25èC 200 85èC 100 85èC 105èC 105èC 0 0 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5 Input Voltage (V) Input Voltage (V) D016 D017

Figure 12. TPS22976 tDELAY vs VINPUT Figure 13. TPS22976 tDELAY vs VINPUT

The reduction in tRISE is observed for the same reason that tDELAY was reduced; a higher VBIAS allows the device to turn on faster. Figure 14 from the TPS22958 datasheet (SLVSCX7) shows a VBIAS sweep with VIN at 2.5 V and CT = 1000 pF.

1200 -40°C 1100 25°C 85°C 1000 105°C 900

s) 800 m ( R

t 700

600

500

400

300 2.5 3.0 3.5 4.0 4.5 5.0 V (V) BIAS D026

Figure 14. TPS22958 tRISE vs VBIAS

Typically, rise time decreases with an increasing VBIAS, although some parts can be designed to have a flat rise time response with an increasing VBIAS as seen in Figure 15 from the TPS22953 datasheet (SLVSCT5).

810 105°C 800 85°C 790 25°C 780 -40°C 770 760 s)

m 750 ( R t 740 730 720 710 700 690 2.5 3 3.5 4 4.5 5 5.5 6 V (V) BIAS D030

Figure 15. TPS22953 tRISE vs VBIAS

It is important to double check the AC characteristics of each device to verify its behavior.

3.3 Quick Output Discharge Quick Output Discharge, QOD, is implemented with a bipolar transistor in series with an internal pull-down resistor. The way that the load capacitor is discharged with QOD depends on the operating mode of the transistor. The transistor operating modes are controlled by the bias voltage conditions of the transistor. As voltage on the capacitor falls, the transistor moves from forward-active mode into saturation then into cutoff mode. • If the transistor is the forward-active mode, it acts as a constant current sink. This pulls current out of the load capacitance at a constant rate regardless of output voltage. An example circuit is shown in Figure 16. Discharging of a capacitor with a constant current sink follows Equation 5.

VOUT(t) = 1/CL × IT × t + VOUT(0) Where

• VOUT(t) is the output voltage at time t

• CL is the load capacitance

• IT is the current pulled to ground by the transistor

• VOUT(0) is the initial output voltage (5) • If the transistor is in saturation mode, it acts as a resistor in series with the pull down resistor. This pulls current out of the load capacitance based on the output voltage at a given time. An example circuit is shown in Figure 17. In this mode, the current pulled out of the capacitor follows the typical RC Discharge Equation as described in the Load Capacitance section. • Once the transistor reaches cutoff mode, the transistor opens the connection from the pull-down resistor to ground. Current will only follow through the load resistance now.

RPULL RPULL

CL RL CL RL

+ V + V CE I CE R - PULL - T

Figure 16. QOD - Constant Current Figure 17. QOD - Resistive Pull-Down

4 Conclusion When characterizing the timing of load switches within each system it is best to consider the effect of each of the above conditions, components, and features. Although seemingly complex when all combined together, each operating condition has a direct effect on each of the timing parameters. It is best to consult the datasheet to determine how each part will be affected by the operating specifications and features discussed in this app note.

5 References 1. TPS22975 5.7V, 6A, 16mΩ Load Switch with Adjustable Rise Time & Optional QOD for Cost- Conscious Applications (SLVSDD0) 2. TPS22976 5.5V, 6A, 14mΩ, Dual Load Switch with Adj. Rise Time & Optional QOD for Cost-Conscious Applications (SLVSDE7) 3. TPS22958 5.5V, 4A 13mΩ Load Switch with Adjustable Rise Time and Optional Quick Output Discharge (SLVSCX7) 4. TPS22918 5.5V, 2A, 52mΩ Load Switch with Adjustable Rise Time and Adjustable Quick Output Discharge (SLVSD76) 5. TPS22953 5.7V, 5A, 14mΩ Load Switch with Voltage Monitoring and Reverse Current Protection(SLVSCT5)

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