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Application Report

SLVA88 3 – A pril 2017

Timing of Load Switches

Nicholas Carle y........................................................................................................... Power Switches

ABSTRACT

Timing of load switches can vary depending on the operating conditions of the system and feature set of the device. At a glance, these variations can seem complex; but, when broken down, each operating condition and feature has a correlation to a change in timing. This application note goes into detail on how each condition or feature can alter the timing of a load switch so that the variations can be prepared for.

Contents

1

Overview and Main Questions ............................................................................................. 2

1.1 1.2 1.3 1.4 1.5

Definition of Timing Parameters .................................................................................. 2 Alternative Timing Methods ....................................................................................... 2 Why is My Rise Time Different than Expected? ................................................................ 3 Why is My Fall Time Different than Expected? ................................................................. 3

Why Do NMOS and PMOS Pass FETs Affect Timing Differently?........................................... 3
2

3

Effect of System Operating Specifications on Timing................................................................... 5

2.1 2.2 2.3 2.4

Temperature......................................................................................................... 5 Load Resistance .................................................................................................... 6 Load Capacitance .................................................................................................. 7 Input Voltage ........................................................................................................ 7
Effects of Device Features on Timing..................................................................................... 7

3.1 3.2 3.3

Slew Rate............................................................................................................ 8 Bias Voltage ......................................................................................................... 9 Quick Output Discharge .......................................................................................... 10

45

Conclusion .................................................................................................................. 11 References .................................................................................................................. 11

List of Figures

1

tDELAY, tON, tOFF, tRISE, and tFALL Waveforms .................................................................................. 2 Alternative Timing Waveform .............................................................................................. 3 Voltages on NMOS FET .................................................................................................... 4 TPS22975 tRISE and tDELAY Across Temperature .......................................................................... 5

234

  • 5
  • TPS22975

Across Temperature....................................................................................... 5

FALL

6

TPS22918 tRISE and tDELAY Across Temperature .......................................................................... 6 TPS22918 tFALL Across Temperature ...................................................................................... 6 RFET and RLOAD Voltage Divider ............................................................................................. 6 TPS22976 tRISE vs VINPUT ..................................................................................................... 7 TPS22976 tDELAY vs VINPUT ................................................................................................... 7 TPS22958 tR vs VIN With Changing CT ................................................................................... 8 TPS22976 tDELAY vs VINPUT ................................................................................................... 9 TPS22976 tDELAY vs VINPUT ................................................................................................... 9 TPS22958 tRISE vs VBIAS ...................................................................................................... 9 TPS22953 tRISE vs VBIAS .................................................................................................... 10 QOD - Constant Current .................................................................................................. 10

78910 11 12 13 14 15 16

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Overview and Main Questions

17

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QOD - Resistive Pull-Down ............................................................................................... 10

  • 1
  • Overview and Main Questions

1.1 Definition of Timing Parameters

First, let’s look at the key behaviors of a load switch and how they relate to timing parameters. See

Figure 1.

•••
Delay time, tDELAY, accounts for the time required to prepare the subsystems of a load switch before the pass FET can be turned on. Delay time is defined as the time from the device being enabled until VOUT starts to rise (typically to 10%).

Rise time, tRISE, is set by the slew rate of the load switch. Rise time is defined as the time for VOUT to rise from 10% to 90%. The 10% and 90% marks are used for higher test and measurement accuracy during device characterization.

Fall time, tFALL, is heavily affected by the load resistance and load capacitance but can be influenced by devices with quick output discharge. Fall time is defined as the time for VOUT to fall from 90% to 10%. The 90% and 10% marks are used for higher test and measurement accuracy during device characterization.

•

•
On time, tON, represents the time for a switch to turn on. tON is typically defined as a combination of tDELAY and tRISE but can vary based on the test methodology used for each device. For this app note, tON

  • will be defined as tDELAY + tRISE
  • .

Off time, tOFF, represents the time for a switch to turn off but varies based on the test methodology used for each device. For this app note, tOFF will be defined as the time from the device being disabled until VOUT begins to fall (90%).

VIH

  • VON
  • tON

tOFF

VIL

tFALL tRISE

90%

tDELAY

90%

VOUT
SRON

10%
10%

Figure 1. tDELAY, tON, tOFF, tRISE, and tFALL Waveforms

1.2 Alternative Timing Methods

The definitions above are the way the timing parameters will be addressed in this app note, but there are other ways of defining the above parameters. The waveform in Figure 2, shows:

•••••
Delay time as the enable signal at 50% until VOUT rises to 10%. On time as the enable signal at 50% until VOUT rises to 50%. Off time as the enable signal at 50% until VOUT falls to 50%. Rise time as VOUT rising from 10% to 90%. Fall time as VOUT falling from 90% to 10%.

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Overview and Main Questions

50%

VON tON tOFF

50%

tFALL tRISE

90%
90%

tDELAY

50%

VOUT

{whb

50%
10%

10%

Figure 2. Alternative Timing Waveform

The on time for a device will be different depending on which method is used to calculate it. It is important to always double check the datasheet for how each device defines its timing.

1.3 Why is My Rise Time Different than Expected?

Rise Time is affected by many operating conditions and external components around a load switch. The

main factors are: Slew Rate, Load Resistance, Input Voltage and Bias Voltage. The slew rate of the

device controls how quickly the output rail ramps up to the input rail when the device turns on. The load resistance, with respect to the decreasing FET resistance, determines the point at which the output rail reaches 90% of the input. Input voltage is directly proportional to rise time, a higher input voltage results in a higher rise time. Bias voltage powers the charge pump which can improve rise time if the bias voltage is higher than the input voltage.

1.4 Why is My Fall Time Different than Expected?

Fall time is affected by Load Capacitance and Quick Output Discharge (part dependant). When a load switch is turned off the charge on the load capacitance needs to be discharged to bring the output rail down. Load resistance and load capacitance are directly proportional to the fall time based on RC capacitive discharging. Quick Output Discharge can be used to increase the current being pulled out of the load capacitance. Quick Output Discharge has a larger impact on discharging the load capacitance the larger the load resistance is.

1.5 Why Do NMOS and PMOS Pass FETs Affect Timing Differently?

NMOS and PMOS pass FETs behave differently while the FETs are turning on. NMOS rise time is less affected by external components (load resistance and load capacitance) while the rise time of PMOS is almost exclusively controlled by external components.

NMOS pass FETs have 4 key voltage parameters during turn on: input voltage, output voltage, gate voltage, and the VGS threshold voltage. See Figure 3. The output starts at 0 V, rises to, and stops at the input voltage when the FET is fully on. The VGS threshold voltage is the difference in voltage needed between the gate voltage and the output voltage for the output to begin to rise, the VGS threshold voltage is typically around 0.7 V.

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VIN
VOUT

-
VGS
+

VGATE

Figure 3. Voltages on NMOS FET

As the voltage on the gate begins to rise no change occurs at the output until the difference between the gate and output equals the VGS threshold voltage. Once the VGS threshold voltage has been hit, both the gate and output voltages increase linearly and parallel to each other. Once the output has reached the input voltage the output stops increasing.

PMOS pass FETs are pulled to ground to turnon. Once the gate voltage is low and the device turns on the input is immediately passed to the output. The amount of time it takes the gate voltage to reach 0V is typically uncontrolled or hard to control. This causes the output to very quickly rise up to the input voltage. Load resistance causes voltage division between the load and the FET resistance. A low load resistance results in a slower rise time while a high load resistance causes a quick rise time, See the Load

Resistance section.

The way the output of an NMOS pass FET increases is dependant on how quickly the gate voltage increases and is negligibly affected by load capacitance and resistance. The way the output of a PMOS pass FET increase is heavily dependant on the load on the switch.

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Effect of System Operating Specifications on Timing

  • 2
  • Effect of System Operating Specifications on Timing

Timing parameters of a load switch are affected by many typical operating conditions and system

specifications such as: Temperature, Load Resistance, Load Capacitance, Input Voltage. The effect

temperature has on the timing parameters can vary greatly from device to device depending on the specific design architecture. A larger load resistance will reduce tRISE while increasing tFALL. A larger load capacitance increases tFALL based on RC capacitive discharging. Input voltage is directly proportional to tRISE. Section 2.1 through Section 2.4 cover each of these topics individually.

2.1 Temperature

The two main subsystems of a load switch that are affected by temperature which result in a timing change are the VGS threshold of the pass FET and the reference current of the charge pump. The VGS threshold of the pass FET decreases as temperature increases. The reduction in the VGS threshold reduces tDELAY. The reference current of the charge pump controls how quickly the gate will ramp and in turn how quickly the output will rise. Typically, as temperature increases the reference current increases which causes the gate of the pass FET to charge faster. The increase in the reference current causes a

  • reduction in both tDELAY and tRISE
  • .

The overall affect on the device from an increase in temperature, in the case of the TPS22975, reduces tDELAY and tRISE, as shown in Figure 4; while tFALL is relatively constant, as shown in Figure 5. Both figures are based on the following parameters: VIN = 2.5 V, VBIAS = 2.5 V, and CT = 1000 pF. Regardless of which VIN, VBIAS, and CT values are used, the change in the timing parameters, for the TPS22975, due to temperature is consistent.

240

2.5
2.45
2.4

tDELAY tRISE

tFALL

220 200 180 160 140 120 100
80

2.35
2.3
2.25
2.2
2.15
2.1
2.05
2

  • -45
  • -25
  • -5
  • 15
  • 35
  • 55
  • 75
  • 95
  • 115

  • -45
  • -25
  • -5
  • 15
  • 35
  • 55
  • 75
  • 95
  • 115

Temperature (°C)

Temperature (°C)

D001

D003

  • Figure 4. TPS22975 tRISE and tDELAY Across Temperature
  • Figure 5. TPS22975 FALL Across Temperature

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The overall affect on the device from an increase in temperature, in the case of the TPS22918, is different than the TPS22975. As temperature increases: tDELAY linearly decreases while tRISE linearly increases, as shown in Figure 6. Fall time is relatively constant, as shown in Figure 7. Both figures are based on the following parameters: VIN = 2.5 V and CT = 1000 pF. Regardless of which VIN and CT values are used, the change in the timing parameters, for the TPS22918, due to temperature is consistent.

1400 1200 1000
800

2.5
2.45
2.4

tDELAY tRISE

tFALL

2.35
2.3
2.25
2.2
2.15
2.1

600

2.05
2

400

  • -45
  • -25
  • -5
  • 15
  • 35
  • 55
  • 75
  • 95
  • 115

  • -45
  • -25
  • -5
  • 15
  • 35
  • 55
  • 75
  • 95
  • 115

Temperature °C

Temperature °C

D004

D005

  • Figure 6. TPS22918 tRISE and tDELAY Across Temperature
  • Figure 7. TPS22918 tFALL Across Temperature

The TPS22975 is an example of both the switching threshold and the reference current changing with temperature resulting in a larger reduction of tDELAY and tRISE than the TPS22918. The TPS22918 is largely affected by the change in switching threshold, which is why tDELAY decreases with increasing temperature; but the TPS22918 has a relatively constant reference current over temperature which is why tRISE does not decrease with increasing temperature. The fact that tRISE increases on the TPS22918 is due to many small parasitic changes that occur with increasing temperature.

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  • Block Diagrams, Feedback and Transient Response Specifications

    Block Diagrams, Feedback and Transient Response Specifications

    Block Diagrams, Feedback and Transient Response Specifications This module introduces the concepts of system block diagrams, feedback control and transient response specifications which are essential concepts for control design and analysis. (This command loads the functions required for computing Laplace and Inverse Laplace transforms. For more information on Laplace transforms, see the Laplace Transforms and Transfer Functions module.) Block Diagrams and Feedback Consider the example of a common household heating system. A household heating system usually consists of a thermostat that measures the room temperature and compares it with an input desired temperature. If the measured temperature is lower than the desired temperature, the thermostat sends a signal that opens the gas valve and starts the combustion in the furnace. The heat from the furnace is then transferred to the rooms of the house which causes the air temperature in the rooms to rise. Once the measured room temperature exceeds the desired temperature by a certain amount, the thermostat turns off the furnace and the cycle repeats. This is an example of a control system and in this case the variable being controlled is the room temperature. This system can be sub-divided into its major parts and represented by the following diagram which shows the directions of information flow. This type of diagram, known as a block diagram, is very useful in understanding how the different components interact and effect the variable of interest. Fig. 1: Block diagram of a household heating system The gas valve, furnace and house can be combined to get one block which can be called the plant of the system.