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Timing of Load Switches Application Report SLVA883–April 2017 Timing of Load Switches Nicholas Carley........................................................................................................... Power Switches ABSTRACT Timing of load switches can vary depending on the operating conditions of the system and feature set of the device. At a glance, these variations can seem complex; but, when broken down, each operating condition and feature has a correlation to a change in timing. This application note goes into detail on how each condition or feature can alter the timing of a load switch so that the variations can be prepared for. Contents 1 Overview and Main Questions ............................................................................................. 2 1.1 Definition of Timing Parameters .................................................................................. 2 1.2 Alternative Timing Methods ....................................................................................... 2 1.3 Why is My Rise Time Different than Expected? ................................................................ 3 1.4 Why is My Fall Time Different than Expected? ................................................................. 3 1.5 Why Do NMOS and PMOS Pass FETs Affect Timing Differently?........................................... 3 2 Effect of System Operating Specifications on Timing................................................................... 5 2.1 Temperature......................................................................................................... 5 2.2 Load Resistance .................................................................................................... 6 2.3 Load Capacitance .................................................................................................. 7 2.4 Input Voltage ........................................................................................................ 7 3 Effects of Device Features on Timing..................................................................................... 7 3.1 Slew Rate ............................................................................................................ 8 3.2 Bias Voltage ......................................................................................................... 9 3.3 Quick Output Discharge .......................................................................................... 10 4 Conclusion .................................................................................................................. 11 5 References .................................................................................................................. 11 List of Figures 1 tDELAY, tON, tOFF, tRISE, and tFALL Waveforms .................................................................................. 2 2 Alternative Timing Waveform .............................................................................................. 3 3 Voltages on NMOS FET .................................................................................................... 4 4 TPS22975 tRISE and tDELAY Across Temperature .......................................................................... 5 5 TPS22975 FALL Across Temperature....................................................................................... 5 6 TPS22918 tRISE and tDELAY Across Temperature .......................................................................... 6 7 TPS22918 tFALL Across Temperature ...................................................................................... 6 8 RFET and RLOAD Voltage Divider ............................................................................................. 6 9 TPS22976 tRISE vs VINPUT ..................................................................................................... 7 10 TPS22976 tDELAY vs VINPUT ................................................................................................... 7 11 TPS22958 tR vs VIN With Changing CT ................................................................................... 8 12 TPS22976 tDELAY vs VINPUT ................................................................................................... 9 13 TPS22976 tDELAY vs VINPUT ................................................................................................... 9 14 TPS22958 tRISE vs VBIAS ...................................................................................................... 9 15 TPS22953 tRISE vs VBIAS .................................................................................................... 10 16 QOD - Constant Current .................................................................................................. 10 SLVA883–April 2017 Timing of Load Switches 1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Overview and Main Questions www.ti.com 17 QOD - Resistive Pull-Down ............................................................................................... 10 1 Overview and Main Questions 1.1 Definition of Timing Parameters First, let’s look at the key behaviors of a load switch and how they relate to timing parameters. See Figure 1. • Delay time, tDELAY, accounts for the time required to prepare the subsystems of a load switch before the pass FET can be turned on. Delay time is defined as the time from the device being enabled until VOUT starts to rise (typically to 10%). • Rise time, tRISE, is set by the slew rate of the load switch. Rise time is defined as the time for VOUT to rise from 10% to 90%. The 10% and 90% marks are used for higher test and measurement accuracy during device characterization. • Fall time, tFALL, is heavily affected by the load resistance and load capacitance but can be influenced by devices with quick output discharge. Fall time is defined as the time for VOUT to fall from 90% to 10%. The 90% and 10% marks are used for higher test and measurement accuracy during device characterization. • On time, tON, represents the time for a switch to turn on. tON is typically defined as a combination of tDELAY and tRISE but can vary based on the test methodology used for each device. For this app note, tON will be defined as tDELAY + tRISE. • Off time, tOFF, represents the time for a switch to turn off but varies based on the test methodology used for each device. For this app note, tOFF will be defined as the time from the device being disabled until VOUT begins to fall (90%). VIH VON tON tOFF VIL tRISE tFALL 90% tDELAY 90% VOUT 10% SRON 10% Figure 1. tDELAY, tON, tOFF, tRISE, and tFALL Waveforms 1.2 Alternative Timing Methods The definitions above are the way the timing parameters will be addressed in this app note, but there are other ways of defining the above parameters. The waveform in Figure 2, shows: • Delay time as the enable signal at 50% until VOUT rises to 10%. • On time as the enable signal at 50% until VOUT rises to 50%. • Off time as the enable signal at 50% until VOUT falls to 50%. • Rise time as VOUT rising from 10% to 90%. • Fall time as VOUT falling from 90% to 10%. 2 Timing of Load Switches SLVA883–April 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated www.ti.com Overview and Main Questions 50% VON tON 50% tOFF t tRISE FALL 90% 90% t DELAY 50% VOUT Sw 50% 10% hb 10% Figure 2. Alternative Timing Waveform The on time for a device will be different depending on which method is used to calculate it. It is important to always double check the datasheet for how each device defines its timing. 1.3 Why is My Rise Time Different than Expected? Rise Time is affected by many operating conditions and external components around a load switch. The main factors are: Slew Rate, Load Resistance, Input Voltage and Bias Voltage. The slew rate of the device controls how quickly the output rail ramps up to the input rail when the device turns on. The load resistance, with respect to the decreasing FET resistance, determines the point at which the output rail reaches 90% of the input. Input voltage is directly proportional to rise time, a higher input voltage results in a higher rise time. Bias voltage powers the charge pump which can improve rise time if the bias voltage is higher than the input voltage. 1.4 Why is My Fall Time Different than Expected? Fall time is affected by Load Capacitance and Quick Output Discharge (part dependant). When a load switch is turned off the charge on the load capacitance needs to be discharged to bring the output rail down. Load resistance and load capacitance are directly proportional to the fall time based on RC capacitive discharging. Quick Output Discharge can be used to increase the current being pulled out of the load capacitance. Quick Output Discharge has a larger impact on discharging the load capacitance the larger the load resistance is. 1.5 Why Do NMOS and PMOS Pass FETs Affect Timing Differently? NMOS and PMOS pass FETs behave differently while the FETs are turning on. NMOS rise time is less affected by external components (load resistance and load capacitance) while the rise time of PMOS is almost exclusively controlled by external components. NMOS pass FETs have 4 key voltage parameters during turn on: input voltage, output voltage, gate voltage, and the VGS threshold voltage. See Figure 3. The output starts at 0 V, rises to, and stops at the input voltage when the FET is fully on. The VGS threshold voltage is the difference in voltage needed between the gate voltage and the output voltage for the
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