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Equivalent Rise Time for Resonance in Power/Ground Noise Estimation

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Equivalent Rise Time for Resonance in Power/Ground Noise Estimation Equivalent Rise Time for Resonance in Power/Ground Noise Estimation Emre Salman, Eby G. Friedman Radu M. Secareanu, Olin L. Hartin Department of Electrical and Computer Engineering Freescale Semiconductor University of Rochester MMSTL Rochester, New York 14627 Tempe, Arizona 85284 [salman, friedman]@ece.rochester.edu [r54143,lee.hartin]@freescale.com R p L p Abstract— The non-monotonic behavior of power/ground noise ΔnVdd− with respect to the rise time tr is investigated for an inductive power distribution network with a decoupling capacitor. A time I (t) L (I swi ) p domain solution is provided for the rise time that produces C resonant behavior, thereby maximizing the power/ground noise. d I C (t) I swi The sensitivity of the ground noise to the decoupling capacitance V dd Cd and parasitic inductance Lg is evaluated as a function of R d the rise time. Increasing the decoupling capacitance is shown (t r ) i to efficiently reduce the noise for tr ≤ 2 LgCd. Alternatively, reducing the parasitic inductance Lg is shown to be effective for Δ ≥ n tr 2 LgCd. R g L g I. INTRODUCTION Fig. 1. Equivalent circuit model to estimate power supply noise and ground The distribution of robust power supply and ground voltages bounce. Rp, Lp, and Rg, Lg represent the power and ground rail impedances, is a challenging task in modern integrated circuits due to scaled respectively. Cd is the decoupling capacitor and Rd is the effective series resistance (ESR) of the capacitor. The load circuit is represented by a current power supply voltages and the increased switching activity of source with a rise time (tr)i and peak current (Iswi)p. the load circuit [1], [2]. The parasitic resistance and inductance of the power and ground distribution networks produce IR+ L ∂i/∂t voltage drops, reducing the overall voltage at the load. case rise time producing the maximum noise in the presence The changing voltages increase the delay uncertainty while of a decoupling capacitor is presented. The sensitivity of the reducing the noise margin in high performance integrated noise to the decoupling capacitance and parasitic inductance circuits, possibly causing a timing violation or logic failure. is also evaluated. Decoupling capacitors are often used to reduce power/ground The rest of the paper is organized as follows. The equivalent noise by decreasing the overall impedance of the power circuit model to estimate the peak-to-peak power/ground noise distribution network [3], [4], [5]. is described in Section II. The non-monotonic noise behavior The parallel combination of the decoupling capacitor Cd with respect to the rise time is investigated in Section III. The with the parasitic inductance Lg of the power distribution paper is concluded in Section IV. network, however, produces a peak impedance at the resonant = /( π ) frequency f 1 2 LgCd due to the LC tank circuit. The II. POWER/GROUND NOISE MODEL impedance at the resonant frequency should, therefore, be smaller than the target impedance to satisfy noise constraints. The equivalent circuit model to investigate the noise be- The impedance characteristics of a power distribution system havior with respect to the rise time is shown in Fig. 1, have been investigated with particular focus on the resonant where Rp, Lp, and Rg, Lg represent the power and ground rail behavior [6], [7]. The corresponding rise time that produces impedances, respectively. Cd is the decoupling capacitor and the maximum noise in the time domain, however, has not Rd is the effective series resistance (ESR) of the capacitor. received much attention. The load circuit is represented by a current source with a The non-monotonic behavior of power/ground noise with rise time (tr)i and peak current (Iswi)p. The current provided respect to the rise time is investigated in this paper. A worst by the decoupling capacitance IC(t) and the current flowing through the parasitic inductance IL(t) from the power supply are, respectively, This research is supported in part by the Semiconductor Research Corpo- ∂V ration under Contract No. 2004-TJ-1207, the National Science Foundation I (t)=−C C , (1) under Contract Nos. CCR-0304574 and CCF-0541206, grants from the New C d ∂t York State Office of Science, Technology & Academic Research to the Center Z for Advanced Technology in Electronic Imaging Systems, and by grants t from Intel Corporation, Eastman Kodak Company, Intrinsix Corporation, and 1 IL(t)= VL(t)∂t, (2) Freescale Semiconductor Corporation. Lg 0 978-1-4244-1684-4/08/$25.00 ©2008 IEEE 2422 where VC(t) and VL(t) are, respectively, Note that if the capacitive current is much greater than the inductive current, e.g., (9) (10) or (11) (12), the second V (t)=V − 2Δn + I (t)R , (3) C dd C d term in (13) can be neglected without a significant loss in VL(t)=Δn − IL(t)Rp. (4) accuracy, guaranteeing the pessimism of the expression. In this case, the peak ground noise is approximated by Assuming a ramp function for the noise Δn(t)= [(Vgnd)p/(tr)v]t, replacing (3) in (1) and (4) in (2), and (Vgnd)p ≈ (Iswi)p/GC(tr). (15) taking the derivative with respect to time results in the following differential equations, Alternatively, if the inductive current is much greater, the first term in (13) can be neglected and the peak noise is estimated 2Cd(Vgnd)p ∂IC(t) IC(t)= − RdCd , (5) as (tr)v ∂t (Vgnd)p ≈ (Iswi)p/GL(tr). (16) ∂IL(t) (Vgnd)pt Rp = − IL(t). (6) If the circuit is underdamped, i.e., the damping factor is ∂t L (t ) L g r v g smaller than one, oscillations occur due to a parallel combi- Solving these differential equations with the initial conditions nation of the parasitic inductance and decoupling capacitor. In IC(0)=0 and IL(0)=0 produces the inductive and capacitive this case, the peak-to-peak ground noise voltage is current, respectively, √ ( ) =( ) [ + −πζ/ 1−ζ2 ], 2C Vgnd pp Vgnd p 1 e (17) d −t/(RdCd ) IC(t)=(Vgnd)p (1 − e ), (7) tr where ζ =[(2Rg + Rd)/2] Cd/2Lg is the damping factor. t L −t/ L ( )=( ) [ − ( − Rg )]. ON MONOTONIC OISE EHAVIOR IL t Vgnd p 2 1 e (8) III. N - N B trRg trRg The impedance of a parallel LC circuit is maximum at the These currents can be rewritten as resonant frequency, ω = 1/ (LC). At this frequency, both the capacitive and inductive paths carry a significant amount IC(t)=GC(t)(Vgnd)p, (9) of current, giving rise to resonant behavior. Similarly, in the IL(t)=GL(t)(Vgnd)p, (10) time domain, there exists a rise time at which the capacitive and inductive currents are close and the peak-to-peak noise is where G (t), the conductance of the capacitance path, and C maximum. The worst case rise time producing the maximum G (t), the conductance of the inductance path, are given, L noise is described in Section III-A. The sensitivity of the noise respectively, by to the decoupling capacitance and parasitic inductance as a 2Cd −t/(R C ) function of the rise time is investigated in Section III-B. GC(t)= (1 − e d d ), (11) (tr)v A. Worst Case Rise Time − / Lg t Lg t R GL(t)= − (1 − e g ). (12) The capacitive and inductive currents and the corresponding (t ) R (t ) R2 r v g r v g ground noise are plotted as a function of rise time in Fig. 2 Note that these conductances are both a function of the rise using (7) and (8) for the currents, and (17) for the noise voltage time (tr)v. Specifically, as the rise time becomes smaller, GC(t) when (Iswi)p = 11.5 mA, Lg = 1 nH, Cd = 10 pF, Rg = 2.2 Ω, increases and GL(t) decreases. The capacitive current, there- and Rd = 0.1 Ω. Equation (17) is also compared with SPICE fore, increases with decreasing rise time. Alternatively, the in Fig. 2. inductive current increases with longer rise times. Intuitively, a The model accurately captures the non-monotonic depen- smaller rise time corresponds to a higher frequency, where the dence of noise on rise time, exhibiting a maximum error impedance of the capacitance is smaller and the inductance is of 12.5%. As shown in Fig. 2, for sufficiently small rise higher. The capacitance is, therefore, more effective at smaller times, the capacitive current dominates, and the inductance rise times and becomes less effective as the rise time increases. does not affect the ground noise. As the rise time increases, Assuming the peak noise occurs when the switching current the capacitive current decreases and the inductive current reaches the maximum current, e.g., (tr)v =(tr)i = tr, the peak increases. The peak noise occurs at a rise time where these ground noise at t = tr can be expressed as currents are approximately equal, denoted as the worst case rise time (similar to the resonant behavior in the frequency 1 GC(tr) GL(tr) = + . (13) domain). If the rise time increases further, the noise decreases (V ) (I ) (I ) gnd p swi p swi p due to a lower L ∂i/∂t noise, making the capacitance inef- Replacing (11) and (12) in (13) produces fective. The assumption of fast transients as the worst case (I ) R2t scenario for noise can be overly optimistic in a circuit with ( ) = swi p g r . Vgnd p Lg sufficient decoupling. This conclusion is similar to reducing −tr/ 2( − −tr/(RdCd )) − ( − Rg )+ 2CdRg 1 e L 1 e Rgtr the resonant frequency with a larger capacitance.
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