CMOS Inverter: DC Analysis • Analyze DC Characteristics of CMOS Gates by studying an Inverter

• DC Analysis – DC value of a signal in static conditions

• DC Analysis of CMOS Inverter –Vin, input voltage – Vout, output voltage – single power supply, VDD – Ground reference –find Vout = f(Vin)

• Voltage Transfer Characteristic (VTC) – plot of Vout as a function of Vin – vary Vin from 0 to VDD – find Vout at each value of Vin

ECE 410, Prof. A. Mason Lecture Notes 7.1 Inverter Voltage Transfer Characteristics

• Output High Voltage, VOH – maximum output voltage • occurs when input is low (Vin = 0V) • pMOS is ON, nMOS is OFF • pMOS pulls Vout to VDD

–VOH = VDD

• Output Low Voltage, VOL – minimum output voltage • occurs when input is high (Vin = VDD) • pMOS is OFF, nMOS is ON • nMOS pulls Vout to Ground

–VOL = 0 V •Logic Swing – Max swing of output signal

•VL = VOH -VOL •VL = VDD

ECE 410, Prof. A. Mason Lecture Notes 7.2 Inverter Voltage Transfer Characteristics • Gate Voltage, f(Vin) •Drain Voltage, f(Vout)

–VGSn=Vin, VSGp=VDD-Vin –VDSn=Vout, VSDp=VDD-Vout + V • Transition Region (between VOH and VOL) SGp –Vinlow - •Vin< Vtn + –Mnin Cutoff, OFF VGSn – Mp in Triode, Vout pulled to VDD - •Vin> Vtn< ~Vout – Mn in Saturation, strong current

– Mp in Triode, VSG & current reducing – Vout decreases via current through Mn – Vin = Vout (mid point) ≈ ½VDD – Mn and Mp both in Saturation – maximum current at Vin = Vout Vin < VIL –Vinhigh input logic LOW • Vin > ~Vout, Vin < VDD - |Vtp| – Mn in Triode, Mp in Saturation Vin > VIH • Vin > VDD - |Vtp| input logic HIGH –Mnin Triode, Mp in Cutoff

ECE 410, Prof. A. Mason Lecture Notes 7.3 Noise Margin

•Input Low Voltage, VIL

– Vin such that Vin < VIL = logic 0 – point ‘a’ on the plot ∂Vin •where slope, −= 1 ∂Vout

• Input High Voltage, VIH

– Vin such that Vin > VIH = logic 1 – point ‘b’ on the plot •where slope =-1 • Voltage Noise Margins – measure of how stable inputs are with respect to signal interference

–VNMH = VOH -VIH = VDD - VIH

–VNML = VIL -VOL = VIL

– desire large VNMH and VNML for best noise immunity

ECE 410, Prof. A. Mason Lecture Notes 7.4 Switching Threshold • Switching threshold = point on VTC where Vout = Vin

– also called midpoint voltage, VM

– here, Vin = Vout = VM

• Calculating VM

–at VM, both nMOS and pMOS in Saturation

– in an inverter, IDn = IDp, always!

– solve equation for VM μ WC β β I = OXn VV )( 2 n VV )( 2 p )( 2 =−=−=− IVV Dn 2 L GSn tn 2 GSn tn 2 SGp tp Dp

– express in terms of VM β β 2 β p 2 n n tnM )( −−=− VVVVV tpMDD VV tnM )( ( −−=− VVV tpMDD ) β 2 2 ⇒ p β – solve for VM +− VVVDD n tntp β V = p M β 1+ n β p

ECE 410, Prof. A. Mason Lecture Notes 7.5 Effect of Transistor Size on VTC

⎛W ⎞ β •Recall k'n ⎜ ⎟ +− VVVDD n β L tntp W n ⎝ ⎠n β p = V = β = k'nn M β p ⎛W ⎞ β L k' ⎜ ⎟ n p L 1+ ⎝ ⎠ p β p • If nMOS and pMOS are same size ⎛W ⎞ –(W/L)n = (W/L)p μ C ⎜ ⎟ β oxnn L μ n = ⎝ ⎠n n ≅= or32 –Coxn= Coxp(always) β ⎛W ⎞ μ p μ C p ⎛W ⎞ oxpp ⎜ ⎟ ⎜ ⎟ ⎝ L ⎠ p μ ⎝ L ⎠ p β n = then n = 1, since L normally min. size for all tx, •Ifμ ⎛W ⎞ β p ⎜ ⎟ p can get betas equal by making Wp larger than Wn ⎝ L ⎠n • Effect on switching threshold

–if βn ≈βp and Vtn = |Vtp|, VM = VDD/2, exactly in the middle

• Effect on noise margin

–if βn ≈βp, VIH and VIL both close to VM and noise margin is good

ECE 410, Prof. A. Mason Lecture Notes 7.6 Example •Given – k’n = 140uA/V2, Vtn = 0.7V, VDD = 3V – k’p = 60uA/V2, Vtp = -0.7V •Find

– a) tx size ratio so that VM= 1.5V

–b) VM if tx are same size

transition pushed lower as beta ratio increases

ECE 410, Prof. A. Mason Lecture Notes 7.7 CMOS Inverter: Transient Analysis • Analyze Transient Characteristics of CMOS Gates by studying an Inverter

• Transient Analysis – signal value as a function of time

• Transient Analysis of CMOS Inverter – Vin(t), input voltage, function of time – Vout(t), output voltage, function of time – VDD and Ground, DC (not function of time) – find Vout(t) = f(Vin(t))

• Transient Parameters –output signal rise and fall time – propagation delay

ECE 410, Prof. A. Mason Lecture Notes 7.8 Transient Response • Response to step change in input – delays in output due to parasitic R & C •Inverter RC Model – Resistances

–Rn= 1/[βn(VDD-Vtn)] + –Rp= 1/[βn(VDD-|Vtp|)] Vout –Output Cap. (only output is important) CL -

•CDn (nMOS drain capacitance)

–CDn = ½ Cox Wn L + Cj ADnbot + Cjsw PDnsw

•CDp (pMOS drain capacitance)

–CDp = ½ Cox Wp L + Cj ADpbot + Cjsw PDpsw • Load capacitance, due to gates attached at the output

–CL = 3 Cin = 3 (CGn + CGp), 3 is a “typical” load • Total Output Capacitance –Cout= C + C + C term “fan-out” describes Dn Dp L # gates attached at output

ECE 410, Prof. A. Mason Lecture Notes 7.9 Fall Time

• Fall Time, tf – time for output to fall from ‘1’ to ‘0’

–derivation: ∂Vout Vout −= Ci out = ∂t Rn • initial condition, Vout(0) = VDD • solution time constant − t τ n τ = R C )( = DDeVtVout n n out

⎛ VDD ⎞ t = τ n ln⎜ ⎟ ⎝Vout ⎠ – definition

•tf is time to fall from

90% value [V1,tx] to 10% value [V0,ty] ⎡ ⎛ V ⎞ ⎛ V ⎞⎤ ⎜ DD ⎟ ⎜ DD ⎟ t = τ n ⎢ln⎜ ⎟ − ln⎜ ⎟⎥ ⎣ ⎝ 1.0 VDD ⎠ ⎝ 9.0 VDD ⎠⎦

•tf = 2.2 τn

ECE 410, Prof. A. Mason Lecture Notes 7.10 Rise Time

•Rise Time, tr – time for output to rise from ‘0’ to ‘1’

–derivation: ∂Vout DD −VV out = Ci out = ∂t Rp • initial condition, Vout(0) = 0V • solution time constant − t ⎡ τ p ⎤ DD ⎢1)( −= eVtVout ⎥ τp = RpCout ⎣ ⎦ – definition

•tf is time to rise from

10% value [V0,tu] to 90% value [V1,tv]

•tr = 2.2 τp • Maximum Signal Frequency

–fmax = 1/(tr + tf) • faster than this and the output can’t settle

ECE 410, Prof. A. Mason Lecture Notes 7.11 Propagation Delay

• Propagation Delay, tp – measures speed of output reaction to input change

–tp = ½(tpf + tpr) • Fall propagation delay, tpf – time for output to fall by 50% • reference to input change by 50%

• Rise propagation delay, tpr – time for output to rise by 50% • reference to input change by 50% •Ideal expression (if input is step change)

–t = ln(2) τn pf Propagation delay measurement: τ –tpr = ln(2) p - from time input reaches 50% value • Total Propagation Delay - to time output reaches 50% value –t= 0.35(τ + τ ) p n p Add rise and fall propagation delays for total value

ECE 410, Prof. A. Mason Lecture Notes 7.12 Switching Speed -Resistance • Rise & Fall Time τn = RnCout τp = RpCout –tf = 2.2 τn, tr = 2.2 τp,

• Propagation Delay Rn = 1/[βn(VDD-Vtn)] β= μCox (W/L)

–t= 0.35(τn + τp) p Rp = 1/[βp(VDD-|Vtp|)] • In General Cout = CDn + CDp + CL –delay ∝τn + τp

– τn + τp = Cout (Rn+Rp) β β β •Define delay in terms of Beta Matched if n= p= , design parameters Rn+Rp = 2 = 2 L β (V -Vt) μCox W (V -Vt) –Rn+Rp= (VDD-Vt)(βn +βp) DD DD

β β (V -Vt)2 Width Matched and L=L =L n p DD if Wn=Wp=W, n p μ μ –Rn+Rp= βn + βp Rn+Rp = L ( n+ p)

βn βp(VDD-Vt) (μn μp) Cox W (VDD-Vt)

• if Vt = Vtn = |Vtp| To decrease R’s, ⇓L, ⇑W, ⇑VDD, ( ⇑μp, ⇑Cox )

ECE 410, Prof. A. Mason Lecture Notes 7.13 Switching Speed -Capacitance

•From Resistance we have Cout = CDn + CDp + CL – ⇓L, ⇑W, ⇑VDD, ( ⇑μ , ⇑Cox ) p if L=Ln=Lp estimate ⇑ –but VDD increases power CL = 3 (CGn + CGp) = 3 Cox (WnL+WpL) – ⇑ W increases Cout CDn = ½ Cox Wn L + Cj ADnbot + Cjsw PDnsw •Cout CDp = ½ Cox Wp L + Cj ADpbot + Cjsw PDpsw

– Cout = ½ Cox L (Wn+Wp) + Cj 2L ~2L (Wn+Wp) + 3 Cox L (Wn+Wp) • assuming junction area ~W•2L W • neglecting sidewall capacitance L – Cout ≈ L (Wn+Wp) [3½ Cox +2 Cj]

– Cout ∝ L (Wn+Wp) To decrease Cout, ⇓L, ⇓W, (⇓Cj, ⇓Cox ) •Delay ∝ Cout(Rn+Rp) ∝ L W L = L2 W VDD VDD Decreasing L (reducing feature size) is best way to improve speed!

ECE 410, Prof. A. Mason Lecture Notes 7.14 Switching Speed -Local Modification • Previous analysis applies to the overall design – shows that reducing feature size is critical for higher speed – general result useful for creating cell libraries • How do you improve speed within a specific gate?

– increasing W in one gate will not increase CG of the load gates • Cout = CDn + CDp + CL • increasing W in one logic gate will increase CDn/p but not CL –CL depends on the size of the tx gates at the output – as long as they keep minimum W, CL will be constant –thus, increasing W is a good way to improve the speed within a local point –But, increasing W increases chip area needed, which is bad • fast circuits need more chip area (chip “real estate”)

• Increasing VDD is not a good choice because it increases power consumption

ECE 410, Prof. A. Mason Lecture Notes 7.15 CMOS Power Consumption

•P = PDC + Pdyn –PDC: DC (static) term

–Pdyn: dynamic (signal changing) term

•PDC –P = IDD VDD •IDD DC current from power supply • ideally, IDD = 0 in CMOS: ideally only current during switching action • leakage currents cause IDD > 0, define quiescent leakage current, IDDQ (due largely to leakage at substrate junctions)

–PDC = IDDQ VDD •Pdyn, power required to switch the state of a gate – charge transferred during transition, Qe = Cout VDD – assume each gate must transfer this charge 1x/clock cycle 2 –Paverage= VDD Qe f = Cout VDD f, f = frequency of signal change Power increases with Cout and 2 frequency, and strongly with • Total Power, P = IDDQ VDD + Cout VDD f VDD (second order).

ECE 410, Prof. A. Mason Lecture Notes 7.16 Multi-Input Gate Signal Transitions • In multi-input gates multiple signal transitions produce output changes • What signal transitions need to be analyzed?

– for a general N-input gate with M0 low output states and M1 high output states

• # high-to-low output transitions = M0⋅M1

• # low-to-high output transitions = M1⋅M0

• total transitions to be characterized = 2⋅M0⋅M1

• example: NAND has M0 = 1, M1 = 3 – don’t test/characterize cases without output transitions •Worst-case delayis the slowest of all possible cases – worst-case high-to-low – worst-case low-to-high – often different input transitions for each of these cases

ECE 410, Prof. A. Mason Lecture Notes 7.17 Series/Parallel Equivalent Circuits • Scale both W and L – no effective change in W/L – increases gate capacitance β = μCox (W/L) inputs must be at same value/voltage • Series Transistors – increases effective L

effective β⇒½ β

• Parallel Transistors – increases effective W

effective β⇒2β

ECE 410, Prof. A. Mason Lecture Notes 7.18 NAND: DC Analysis • Multiple Inputs • Multiple Transitions •Multiple VTCs – VTC varies with transition • transition from 0,0 to 1,1 pushed right of others •why?

–VM varies with transition •assume all txhave same L

•VM = VA = VB = Vout – can merge transistors at this point

•if WpA=WpB and WnA=WnB – series nMOS, βN ⇒ ½ βn

– parallel pMOS, βP ⇒ 2 βp

– can now calculate the NAND VM

ECE 410, Prof. A. Mason Lecture Notes 7.19 NAND Switching Point • Calculate VM for NAND – 0,0 to 1,1 transition • all tx change states (on, off) • in other transitions, only 2 change

–VM = VA = VB = Vout –set I = I , solve for V Dn Dp M series nMOS means 1 β +− VVVDD n more resistance to tntp 2 β V = p output falling, M 1 β 1+ n 2 β p shifts VTC to right – denominator reduced more •VTC shifts right to balance this effect and set VM to VDD/2, • For NAND with N inputs can increase β by

1 β n increasing Wn +− VVVDD tntp N β p VM = but, since μn>μp, VM≈VDD/2 1 β 1+ n when Wn = Wp N β p ECE 410, Prof. A. Mason Lecture Notes 7.20 NOR: DC Analysis • Similar Analysis to NAND • Critical Transition – 0,0 to 1,1 – when all transistors change

•VM for NOR2 critical transition

–if WpA=WpB and WnA=WnB • parallel nMOS, βn ⇒ 2 βn •series pMOS, βp ⇒ ½ βp

β n β n tp +− 2VVVDD tn tp +− NVVVDD tn β p β p V = VM = M β β + 21 n 1+ N n β p β p for NOR2 for NOR-N – series pMOS resistance means slower rise – VTC shifted to the left

–to set VM to VDD/2, increase Wp • this will increase βp

ECE 410, Prof. A. Mason Lecture Notes 7.21 NAND: Transient Analysis • NAND RC Circuit – R: standard channel resistance

– C: Cout = CL + CDn + 2CDp

• Rise Time, tr – Worst case charge circuit •1 pMOS ON

–tr = 2.2 τp

• τp = Rp Cout – best case charge circuit •2 pMOS ON, Rp⇒ Rp/2

• Fall Time, tf – Discharge Circuit •2 series nMOS, Rn⇒ 2Rn • must account for internal cap, Cx

–tf = 2.2 τn Cx = CSn + CDn • τn = Cout (2 Rn ) + Cx Rn

ECE 410, Prof. A. Mason Lecture Notes 7.22 NOR: Transient Analysis •NOR RC Circuit – R: standard channel resistance

– C: Cout = CL + 2CDn + CDp

• Fall Time, tf – Worst case discharge circuit •1 nMOS ON

–tf = 2.2 τn

• τn = Rn Cout – best case discharge circuit • 2 nMOS ON, Rn ⇒ Rn/2

• Rise Time, tr – Charge Circuit •2 series pMOS, Rp⇒ 2Rp Cy = CSp + CDp • must account for internal cap, Cy

–tr = 2.2 τp

• τp = Cout (2 Rp ) + Cy Rp

ECE 410, Prof. A. Mason Lecture Notes 7.23 NAND/NOR Performance

• Inverter: symmetry (VM=VDD/2), βn = βp

– (W/L)p = μn/μp (W/L)n • Match INV performance with NAND β is adjusted by – pMOS, βP = βp, same as inverter changing transistor

– nMOS, βN = 2βn, to balance for 2 series nMOS size (width) • Match INV performance with NOR

– pMOS, βP = 2 βp, to balance for 2 series pMOS

– nMOS, βN = βn, same as inverter • NAND and NOR will still be slower due to larger Cout

• This can be extended to 3, 4, … N input NAND/NOR gates

ECE 410, Prof. A. Mason Lecture Notes 7.24 NAND/NOR Transient Summary • Critical Delay Path – paths through series transistors will be slower – more series transistors means worse delays

• Tx Sizing Considerations – increase W in series transistors

– balance βn/βp for each cell

• Worst Case Transition – when all series transistor go from OFF to ON – and all internal caps have to be • charged (NOR) •discharged (NAND)

ECE 410, Prof. A. Mason Lecture Notes 7.25 Performance Considerations • Speed based on βn, βp and parasitic caps

• DC performance (VM, noise) based on βn/βp • Design for speed not necessarily provide good DC performance • Generally set tx size to optimize speed and then test DC characteristics to ensure adequate noise immunity •Review Inverter: Our performance reference point

– for symmetry (VM=VDD/2), βn = βp

• which requires (W/L)p = μn/μp (W/L)n • Use inverter as reference point for more complex gates • Apply slowest arriving inputs to series node closest to output output slower – let faster signals begin to charge/discharge signal faster nodes closer to VDD and Ground signal power supply

ECE 410, Prof. A. Mason Lecture Notes 7.26 Timing in Complex Logic Gates • Critical delay path is due to series-connected transistors • Example: f = x (y+z) – assume all tx are same size • Fall time critical delay – worst case, x ON, and y or z ON

–tf = 2.2 τn

• τn = Rn Cn + 2 Rn Cout –Cout = 2CDp + CDn + CL –Cn= 2CDn + CSn • Rise time critical delay size vs. tx speed considerations – worst case, y and z ON, x OFF ⇑Wnx ⇒⇓Rn but ⇑Cout and ⇑Cn –tr = 2.2 τp ⇓Wny ⇒⇓Cn but ⇑Rn

• τp = Rp Cp + 2 Rp Cout –Cout = 2CDp + CDn + CL ⇑Wpz ⇒⇓Rp but ⇑Cout and ⇑Cp –Cp = CDp + CSp ⇓Wpx ⇒ no effect on critical path

ECE 410, Prof. A. Mason Lecture Notes 7.27 Sizing in Complex Logic Gates • Improving speed within a single logic gate • An Example: f=(a b+c d) x •nMOS –discharge through 3 series nMOS

–set βN = 3βn •pMOS – charge through 2 series pMOS

–set βP = 2βp

–but, Mp-x is alone so βP1 = βp

•but setting βP1 = 2βp might make layout easier • These large transistors will increase capacitance and layout area and may only give a small increase in speed • Advanced logic structures are best way to improve speed

ECE 410, Prof. A. Mason Lecture Notes 7.28 Timing in Multi-Gate Circuits • What is the worst-case delay in multi-gate circuits?

A A B C D F C↑ B F 0 0 0 0 0 C 0 0 0 1 0 D C↑D↓ 0 0 1 0 1

– too many transitions to test manually 1 0 0 0 0 B↑ • Critical Path 1 1 0 0 1 – longest delay through a circuit block 1 1 1 1 1 – largest sum of delays, from input to output – intuitive analysis: signal that passes through most gates • not always true. can be slower path through fewer gates

A B F path through most gates C D critical path if delay due to D input is very slow

ECE 410, Prof. A. Mason Lecture Notes 7.29 Power in Multi-Input Logic Gates • Inverter Power Consumption 2 –P = PDC + Pdyn = VDDIDDQ + CoutV DDf • assumes gates switches output state once per clock cycle, f •Multi-Input Gates

– same DC component as inverter, PDC = VDDIDDQ – for dynamic power, need to estimate “activity” of the gate, how often will the output be switching 2 NOR NAND –Pdyn = aCoutV DDf, a = activity coefficient – estimate activity from truth table

•a = p0p1

–p0 = prob. output is at 0

–p1 = prob. of transition to 1 p0=0.75 p0=0.25 p1=0.25 p1=0.75 a=3/16 a=3/16

ECE 410, Prof. A. Mason Lecture Notes 7.30 Timing Analysis of Transmission Gates • TG = parallel nMOS and pMOS

•RC Model – in general, only one tx active at same time • nMOS pulls output low •pMOS pushes output high

–RTG = max (Rn, Rp)

–Cin= CSn + CDp • if output at higher voltage than input – larger W will decrease R but increase Cin

• Note: no connections to VDD-Ground. Input signal, Vin, must drive TG output; TG just adds extra delay

ECE 410, Prof. A. Mason Lecture Notes 7.31 Pass Transistor • Single nMOS or pMOS tx • Often used in place of TGs – less area and wiring – can’t pull to both VDD and Ground – typically use nMOS for better speed • Rise and Fall Times Φ=1 y ID – τn = Rn Cout time x=0 y=1 ⇒ 0 –t= 2.94 τ f n Φ=1 y ID –tr = 18 τn time • much slower than fall time x=1 y=0 ⇒ 1

• nMOS can’t pull output to VDD – rise time suffers from threshold loss in nMOS

ECE 410, Prof. A. Mason Lecture Notes 7.32