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CMOS Inverter: DC Analysis • Analyze DC Characteristics of CMOS Gates by Studying an Inverter

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CMOS Inverter: DC Analysis • Analyze DC Characteristics of CMOS Gates by Studying an Inverter CMOS Inverter: DC Analysis • Analyze DC Characteristics of CMOS Gates by studying an Inverter • DC Analysis – DC value of a signal in static conditions • DC Analysis of CMOS Inverter –Vin, input voltage – Vout, output voltage – single power supply, VDD – Ground reference –find Vout = f(Vin) • Voltage Transfer Characteristic (VTC) – plot of Vout as a function of Vin – vary Vin from 0 to VDD – find Vout at each value of Vin ECE 410, Prof. A. Mason Lecture Notes 7.1 Inverter Voltage Transfer Characteristics • Output High Voltage, VOH – maximum output voltage • occurs when input is low (Vin = 0V) • pMOS is ON, nMOS is OFF • pMOS pulls Vout to VDD –VOH = VDD • Output Low Voltage, VOL – minimum output voltage • occurs when input is high (Vin = VDD) • pMOS is OFF, nMOS is ON • nMOS pulls Vout to Ground –VOL = 0 V •Logic Swing – Max swing of output signal •VL = VOH -VOL •VL = VDD ECE 410, Prof. A. Mason Lecture Notes 7.2 Inverter Voltage Transfer Characteristics • Gate Voltage, f(Vin) •Drain Voltage, f(Vout) –VGSn=Vin, VSGp=VDD-Vin –VDSn=Vout, VSDp=VDD-Vout + V • Transition Region (between VOH and VOL) SGp –Vinlow - •Vin< Vtn + –Mnin Cutoff, OFF VGSn – Mp in Triode, Vout pulled to VDD - •Vin> Vtn< ~Vout – Mn in Saturation, strong current – Mp in Triode, VSG & current reducing – Vout decreases via current through Mn – Vin = Vout (mid point) ≈ ½VDD – Mn and Mp both in Saturation – maximum current at Vin = Vout Vin < VIL –Vinhigh input logic LOW • Vin > ~Vout, Vin < VDD - |Vtp| – Mn in Triode, Mp in Saturation Vin > VIH • Vin > VDD - |Vtp| input logic HIGH –Mnin Triode, Mp in Cutoff ECE 410, Prof. A. Mason Lecture Notes 7.3 Noise Margin •Input Low Voltage, VIL – Vin such that Vin < VIL = logic 0 – point ‘a’ on the plot ∂Vin •where slope, −= 1 ∂Vout • Input High Voltage, VIH – Vin such that Vin > VIH = logic 1 – point ‘b’ on the plot •where slope =-1 • Voltage Noise Margins – measure of how stable inputs are with respect to signal interference –VNMH = VOH -VIH = VDD - VIH –VNML = VIL -VOL = VIL – desire large VNMH and VNML for best noise immunity ECE 410, Prof. A. Mason Lecture Notes 7.4 Switching Threshold • witching threshold = point on VTC where VoutS = Vin – also called midpoint voltage, VM – ere, Vinh = Vout = VM • alculating VCM V t –aM, both nMOS and pMOS in Saturation – in an inverter, IDn = IDp, always! – olve equation for VsM μCW β β I = n OX −VV() =2 nVV() −2 =VVIp() −2 = Dn 2 L GSn tn 2 GSn tn 2 SGp tp Dp – xpress in terms of VeM β β 2 β p 2 n n VVVVV()−M tn =DD − M − tp VV()−M tn =VVVDD( − M −) tp β 2 2 ⇒ p β – olve for VsM VDD− V + n V tp tn β V = p M β 1+ n β p ECE 410, Prof. A. Mason ecLture Notes 7.5 Effect of Transistor Size on VTC ⎛W ⎞ β •Recall k'n ⎜ ⎟ VDD− V + n V β L tp tn W n ⎝ ⎠n β p = V = βn= k' n M β p ⎛W ⎞ β L k' ⎜ ⎟ n p L 1+ ⎝ ⎠ p β p • If nMOS and pMOS are same size ⎛W ⎞ –(W/L)n = (W/L)p μ C ⎜ ⎟ β n oxn L μ n = ⎝ ⎠n=n 2 ≅ or 3 –Coxn= Coxp(always) β ⎛W ⎞ μ p μ C p ⎛W ⎞ p oxp⎜ ⎟ ⎜ ⎟ ⎝ L ⎠ p μ ⎝ L ⎠ p β n = ,then n = 1 since L normally min. size for all tx, •Ifμ ⎛W ⎞ β p ⎜ ⎟ p can get betas equal by making Wp larger than Wn ⎝ L ⎠n • Effect on switching threshold –if βn ≈βp and Vtn = |Vtp|, VM = VDD/2, exactly in the middle • Effect on noise margin –if βn ≈βp, VIH and VIL both close to VM and noise margin is good ECE 410, Prof. A. Mason Lecture Notes 7.6 Example •Given – k’n = 140uA/V2, Vtn = 0.7V, VDD = 3V – k’p = 60uA/V2, Vtp = -0.7V •Find – a) tx size ratio so that VM= 1.5V –b) VM if tx are same size transition pushed lower as beta ratio increases ECE 410, Prof. A. Mason Lecture Notes 7.7 CMOS Inverter: Transient Analysis • Analyze Transient Characteristics of CMOS Gates by studying an Inverter • Transient Analysis – signal value as a function of time • Transient Analysis of CMOS Inverter – Vin(t), input voltage, function of time – Vout(t), output voltage, function of time – VDD and Ground, DC (not function of time) – find Vout(t) = f(Vin(t)) • Transient Parameters –output signal rise and fall time – propagation delay ECE 410, Prof. A. Mason Lecture Notes 7.8 Transient Response • Response to step change in input – delays in output due to parasitic R & C •Inverter RC Model – Resistances –Rn= 1/[βn(VDD-Vtn)] + –Rp= 1/[βn(VDD-|Vtp|)] Vout –Output Cap. (only output is important) CL - •CDn (nMOS drain capacitance) –CDn = ½ Cox Wn L + Cj ADnbot + Cjsw PDnsw •CDp (pMOS drain capacitance) –CDp = ½ Cox Wp L + Cj ADpbot + Cjsw PDpsw • Load capacitance, due to gates attached at the output –CL = 3 Cin = 3 (CGn + CGp), 3 is a “typical” load • Total Output Capacitance –Cout= C + C + C term “fan-out” describes Dn Dp L # gates attached at output ECE 410, Prof. A. Mason Lecture Notes 7.9 Fall Time • Fall Time, tf – time for output to fall from ‘1’ to ‘0’ –derivation: ∂Vout Vout i= − Cout = ∂t Rn • initial condition, Vout(0) = VDD • solution time constant − t τ n τ = R C Vout() t= DD V en n out ⎛ VDD ⎞ t = τ n ln⎜ ⎟ ⎝Vout ⎠ – definition •tf is time to fall from 90% value [V1,tx] to 10% value [V0,ty] ⎡ ⎛ V ⎞ ⎛ V ⎞⎤ ⎜ DD ⎟ ⎜ DD ⎟ t = τ n ⎢ln⎜ ⎟ − ln⎜ ⎟⎥ ⎣ ⎝ 1.0 VDD ⎠ ⎝ 9.0 VDD ⎠⎦ •tf = 2.2 τn ECE 410, Prof. A. Mason Lecture Notes 7.10 Rise Time •Rise Time, tr – time for output to rise from ‘0’ to ‘1’ –derivation: ∂Vout VVDD − out i= Cout = ∂t Rp • initial condition, Vout(0) = 0V • solution time constant − t ⎡ τ p ⎤ Vout( )= tDD ⎢ V 1 − ⎥ eτp = RpCout ⎣ ⎦ – definition •tf is time to rise from 10% value [V0,tu] to 90% value [V1,tv] •tr = 2.2 τp • Maximum Signal Frequency –fmax = 1/(tr + tf) • faster than this and the output can’t settle ECE 410, Prof. A. Mason Lecture Notes 7.11 Propagation Delay • Propagation Delay, tp – measures speed of output reaction to input change –tp = ½(tpf + tpr) • Fall propagation delay, tpf – time for output to fall by 50% • reference to input change by 50% • Rise propagation delay, tpr – time for output to rise by 50% • reference to input change by 50% •Ideal expression (if input is step change) –t = ln(2) τn pf Propagation delay measurement: τ –tpr = ln(2) p - from time input reaches 50% value • Total Propagation Delay - to time output reaches 50% value –t= 0.35(τ + τ ) p n p Add rise and fall propagation delays for total value ECE 410, Prof. A. Mason Lecture Notes 7.12 Switching Speed -Resistance • Rise & Fall Time τn = RnCout τp = RpCout –tf = 2.2 τn, tr = 2.2 τp, • Propagation Delay Rn = 1/[βn(VDD-Vtn)] β= μCox (W/L) –t= 0.35(τn + τp) p Rp = 1/[βp(VDD-|Vtp|)] • In General Cout = CDn + CDp + CL –delay ∝τn + τp – τn + τp = Cout (Rn+Rp) β β β •Define delay in terms of Beta Matched if n= p= , design parameters Rn+Rp = 2 = 2 L β (V -Vt) μCox W (V -Vt) –Rn+Rp= (VDD-Vt)(βn +βp) DD DD β β (V -Vt)2 Width Matched and L=L =L n p DD if Wn=Wp=W, n p μ μ –Rn+Rp= βn + βp Rn+Rp = L ( n+ p) βn βp(VDD-Vt) (μn μp) Cox W (VDD-Vt) • if Vt = Vtn = |Vtp| To decrease R’s, ⇓L, ⇑W, ⇑VDD, ( ⇑μp, ⇑Cox ) ECE 410, Prof. A. Mason Lecture Notes 7.13 Switching Speed -Capacitance •From Resistance we have Cout = CDn + CDp + CL – ⇓L, ⇑W, ⇑VDD, ( ⇑μ , ⇑Cox ) p if L=Ln=Lp estimate ⇑ –but VDD increases power CL = 3 (CGn + CGp) = 3 Cox (WnL+WpL) – ⇑ W increases Cout CDn = ½ Cox Wn L + Cj ADnbot + Cjsw PDnsw •Cout CDp = ½ Cox Wp L + Cj ADpbot + Cjsw PDpsw – Cout = ½ Cox L (Wn+Wp) + Cj 2L ~2L (Wn+Wp) + 3 Cox L (Wn+Wp) • assuming junction area ~W•2L W • neglecting sidewall capacitance L – Cout ≈ L (Wn+Wp) [3½ Cox +2 Cj] – Cout ∝ L (Wn+Wp) To decrease Cout, ⇓L, ⇓W, (⇓Cj, ⇓Cox ) •Delay ∝ Cout(Rn+Rp) ∝ L W L = L2 W VDD VDD Decreasing L (reducing feature size) is best way to improve speed! ECE 410, Prof. A. Mason Lecture Notes 7.14 Switching Speed -Local Modification • Previous analysis applies to the overall design – shows that reducing feature size is critical for higher speed – general result useful for creating cell libraries • How do you improve speed within a specific gate? – increasing W in one gate will not increase CG of the load gates • Cout = CDn + CDp + CL • increasing W in one logic gate will increase CDn/p but not CL –CL depends on the size of the tx gates at the output – as long as they keep minimum W, CL will be constant –thus, increasing W is a good way to improve the speed within a local point –But, increasing W increases chip area needed, which is bad • fast circuits need more chip area (chip “real estate”) • Increasing VDD is not a good choice because it increases power consumption ECE 410, Prof. A. Mason Lecture Notes 7.15 CMOS Power Consumption •P = PDC + Pdyn –PDC: DC (static) term –Pdyn: dynamic (signal changing) term •PDC –P = IDD VDD •IDD DC current from power supply • ideally, IDD = 0 in CMOS: ideally only current during switching action • leakage currents cause IDD > 0, define quiescent leakage current, IDDQ (due largely to leakage at substrate junctions) –PDC = IDDQ VDD •Pdyn, power required to switch the state of a gate – charge transferred during transition, Qe = Cout VDD – assume each gate must transfer this charge 1x/clock cycle 2 –Paverage= VDD Qe f = Cout VDD f, f = frequency of signal change Power increases with Cout and 2 frequency, and strongly with • Total Power, P = IDDQ VDD + Cout VDD f VDD (second order).
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