Delay is RC Charging ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Lec 5: September 11, 2015 Delay and RC Response
Penn ESE370 Fall2015 – Khanna Penn ESE370 Fall2015 – Khanna 2
Delay is RC Charging Today
Strategy: ! RC Charging ! Use zero-order model " RC Step Response Curve to understand switch ! What is the C?
state " Capacitive Load on Gate Output
! Break into output/ ! What is the R?
input stages " Equivalent Output Resistance ! For each stage ! Approximating and Measuring Delay
" Understand Rdrive
" Understand Cload
Penn ESE370 Fall2015 – Khanna 3 Penn ESE370 Fall2015 – Khanna 4
90% Rise Time? What does response look like?
What is time constant, τ? ~ 2ps for 90% rise
Penn ESE370 Fall2015 – Khanna 5 Penn ESE370 Fall2015 – Khanna 6
1 Governing Equations? (KCL) Governing Equations? (KCL)
IR
IC
! KCL @ Vmeasure ! KCL @ Vmeasure " Kirchoff’s Current Law " Kirchoff’s Current Law
" Sum of all currents into a node = 0 " Sum of all currents into a node = 0
" Current entering a node = current exiting a node " Current entering a node = current exiting a node
" IR=IC
Penn ESE370 Fall2015 – Khanna 7 Penn ESE370 Fall2015 – Khanna 8
Governing Equations? (KCL) Governing Equations? (KCL)
IR IR
IC IC
dV V I = I I = I 0 = measure + 1 V − in R C R C dt RC measure RC V dV V dV R = C C R = C C R dt R dt V = V 1− e−t/RC V −V dV V −V dV measure in ( ( )) in measure = C measure in measure = C measure R dt R dt τ = RC Penn ESE370 Fall2015 – Khanna 9 Penn ESE370 Fall2015 – Khanna 10
What does look like? Shape of Curve t (in ps) e-t/RC 1-e-t/RC 0 0.1 1 2 2.3
−t/RC −t/RC Vin=1 V V 1 e V V 1 e measure = in −( ) measure = in ( −( )) ( )
Penn ESE370 Fall2015 – Khanna 11 Penn ESE370 Fall2015 – Khanna 12
2 Shape of Curve Rise Time: 10—90% t (in ps) e-t/RC 1-e-t/RC 0 1 0 0.1 0.9 0.1 10% 1 1/e = 0.37 0.66 2 1/e2 = 0.14 0.86 2.3 0.1 0.9 90%
−t/RC Vin=1 V V 1 e measure = in ( −( )) Trise ~= 2.2ps ~= 2.2τ Penn ESE370 Fall2015 – Khanna 13 Penn ESE370 Fall2015 – Khanna 14
Rise Time: 10—90%
What is C? τ=RC
Trise ~= 2.2ps ~= 2.2τ Penn ESE370 Fall2015 – Khanna 15 Penn ESE370 Fall2015 – Khanna 16
Capacitance Fanout
! Wire ! Number of things to which a gate output connects ! Fanout -- Total gate load
" Logical Gate
" MOSFET gate
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3 Fanout in Circuit Fanout in Circuit
! Output routed to many gate inputs ! Maximum fanout? ! Second? ! Min?
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Fanout in Circuit Fanout in Circuit
! Maximum fanout? ! Maximum fanout? ! Second? ! Second? ! Min? ! Min?
2
3 3
Penn ESE370 Fall2015 – Khanna 21 Penn ESE370 Fall2015 – Khanna 22
Fanout in Circuit Fanout in Circuit
! Maximum fanout? ! Maximum fanout? ! Second? ! Second? ! Min? ! Min? 1 1 1 1 0 1 2 1 2 0 1 1 1 1 3 3
Penn ESE370 Fall2015 – Khanna 23 Penn ESE370 Fall2015 – Khanna 24
4 MOSFET Capacitance First Order Model
! “load of 1”?
" Capacitive
2 2
1 1
Out A 2
1 ! Switch 2
1 B " Loads input capacitively
Penn ESE370 Fall2015 – Khanna 25 Penn ESE370 Fall2015 – Khanna 26
MOSFET Capacitance First Order Model
! “load of 1”?
" Capacitive
2 2
1 1
Out A 2
1 ! Switch 2
1 B " Loads input capacitively
! As we dig into the device structure understand:
" Origin of capacitance
" How to engineer device parameters like Cg, RON, Vth " Tradeoffs
Penn ESE370 Fall2015 – Khanna 27 Penn ESE370 Fall2015 – Khanna 28
Lumped Capacitive Load
What is R?
C = C + C load ∑ gi ∑ wi i∈ fanout i∈wires
€ Penn ESE370 Fall2015 – Khanna 29 Penn ESE370 Fall2015 – Khanna 30
5 Resistance First Order Model
! Switch ! Wire resistance " Resistive driver " From supply (Vdd or Gnd) to transistor source ! As we dig into the device structure understand:
" From transistor output to gate it is driving " More sophisticated view, not just RON
! Transistor equivalent resistance (Ron) " How to engineer device parameters like Cg, RON, Vth " Tradeoffs
Penn ESE370 Fall2015 – Khanna 31 Penn ESE370 Fall2015 – Khanna 32
Equivalent Resistance Equivalent Resistance
! What resistances might transistors contribute?
" How many cases?
2 2 2 2 1 1 " Assume Ron=Ron,p=Ron,n 1 1 Out Out A A 2 2
1 1
2 2 B 1 B 1
Penn ESE370 Fall2015 – Khanna 33 Penn ESE370 Fall2015 – Khanna 34
Equivalent Resistance Equivalent Resistance
! What resistances might ! What resistances might transistors contribute? transistors contribute?
" How many cases? " How many cases?
2 2 2 2 " Assume Ron=Ron,p=Ron,n 1 1 " Assume Ron=Ron,p=Ron,n 1 1 Out Out A A 2 2
1 1
2 2
Input Rout 1 Input Rout 1 B B 00 00 Ron/2
01 01 Ron
10 10 Ron
11 11 2Ron
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6 Rise/Fall Times Lumped Resistive Source
! Rise and Fall time may differ
" Why?
2 2 " What is ratio? 1 1 R R R drive = tr,net + wi Out ∑ " A 2 i∈wires 1
2
Input Rout 1 B 00 Ron/2 Rtr,net = transistor network resistance = parallel and 01 Ron series combination of Rtr 10 Ron
11 2Ron
Penn ESE370 Fall2015 – Khanna 37 Penn ESE370 Fall2015 – Khanna 38
Voltage Waveform at Input/Output Node
Measuring Delay
Rdrive from CLoad from output stages input stages and wires and wires
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Measuring Gate Delay Characterizing Gate/Technology
! Delay measure will be
" Function of load on gate 67ps 80ps tdel = 13ps " Function of input rise time
" Which, in turn, may be a function of input loading
! Next stage starts to switch before first finishes ! Measure from 50% of input swing to 50% of output swing
Penn ESE370 Fall2015 – Khanna 41 Penn ESE370 Fall2015 – Khanna 42
7 Delay vs. Risetime Characterizing Gate/Technology
1ps rise 100ps rise ! Delay measure will be
" Function of load on gate
" Function of input rise time
" Which, in turn, may be a function of input loading
! Want to understand typical delay times
" Allows us to compare designs with a (somewhat) normalized delay metric
10ps delay 20ps delay
! If we didn’t know the input rise time, we wouldn’t know what a 13ps delay meant Penn ESE370 Fall2015 – Khanna 43 Penn ESE370 Fall2015 – Khanna 44
Standard Measurement for Characterization HW3 Measurement Setup
! Drive with a gate
" Not an ideal source
" Input rise time typically would see in circuit ! Measure loaded gate
" Typical loading – FO4
Function Oscilloscope Generator
Not realistic measurement
Penn ESE370 Fall2015 – Khanna 45 Penn ESE370 Fall2015 – Khanna 46
Measurement for Characterization Measurement for Characterization
! Drive with a gate ! Drive with a gate
" Not an ideal source (how does delay change if drive is " Not an ideal source
ideal?) " Input rise time typically would see in circuit " Input rise time typically would see in circuit ! Measure loaded gate ! Measure loaded gate " Typical loading – FO4 (how does delay change if gate is " Typical loading – FO4 unloaded?)
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8 Delay is RC Charging Admin
! “Normal Week”
" 3 Lecture Week (all here)
" MOS Operation and Devices ! Spice Flow
" access to electric, setup for spice, run ngspice
Penn ESE370 Fall2015 – Khanna 49 Penn ESE370 Fall2015 – Khanna 50
Admin
! “Normal Week”
" 3 Lecture Week (all here)
" MOS Operation and Devices ! Spice Flow
" access to electric, setup for spice, run ngspice ! HW quality
" Show your work
" Label axes, explain your results
" If we can’t understand it, we can’t grade it ! HW turnin
" Must turn in by the time I start lecturing (12:05)
" Won’t accept any more after that Penn ESE370 Fall2015 – Khanna 51
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