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2017 Symposium on VLSI Technology 2017 Symposium on VLSI Technology Kyoto, Japan 5 – 8 June 2017 IEEE Catalog Number: CFP17VTS-POD ISBN: 978-1-5090-2989-1 Copyright © 2017, The Japan Society of Applied Physics (JSAP) All Rights Reserved *** This is a print representation of what appears in the IEEE Digital Library. Some format issues inherent in the e-media version may also appear in this print version. IEEE Catalog Number: CFP17VTS-POD ISBN (Print-On-Demand): 978-1-5090-2989-1 ISBN (Online): 978-4-86348-605-8 ISSN: 0743-1562 Additional Copies of This Publication Are Available From: Curran Associates, Inc 57 Morehouse Lane Red Hook, NY 12571 USA Phone: (845) 758-0400 Fax: (845) 758-2633 E-mail: [email protected] Web: www.proceedings.com TABLE OF CONTENTS SESSION 1 - Welcome and Plenary Session [Shunju I, II, III] SESSION 3 - III-V [Shunju I] Tuesday, June 6, 8:00-10:10 Tuesday, June 6, 14:00-15:40 Chairpersons: M. Masahara, AIST Chairpersons: T. Tsunomura, Tokyo Electron Ltd. C.-P. Chang, Applied Materials P. Ye, Purdue Univ. T1-1 - 8:00 T3-1 - 14:00 Welcome and Opening Remarks Record Performance for Junctionless Transistors in S. Inaba, Toshiba Memory Corp. InGaAs MOSFETs, C. B. Zota, M. Borg, L.-E. Wernersson and M. Khare, IBM E. Lind, Lund Univ., Sweden 20 T1-2 - 8:45 (Plenary) T3-2 - 14:25 5G and It's Surrounding Situations until 2020, T. Tsutsui, Vertical Heterojunction InAs/InGaAs Nanowire MOSFETs SoftBank Corp., Japan 1 on Si with Ion = 330 μA/μm at Ioff = 100 nA/μm and VD = 0.5V, O.-P. Kilpi, J. Wu, J. Svensson, E. Lind and L.-E. T1-3 - 9:25 (Plenary) Wernersson, Lund Univ., Sweden 22 Privacy and Security: Key Requirements for Sustainable IoT Growth, F. Assaderaghi, G. Chindalore, B. Ibrahim, H. de T3-3 - 14:50 Jong, M. Joye, S. Nassar, W. Steinbauer, M. Wagner and T. Wille, First Demonstration of ~3500 cm2/V-s Electron Mobility NXP Semiconductors, USA 6 and Sufficient BTI Reliability (Max Vov Up to 0.6V) In0.53Ga0.47As nFET Using an IL/LaSiOx/HfO2 Gate Stack, S. Circuits SESSION 1 - Welcome and Plenary Session Sioncke*, J. Franco*, A. Vais*, V. Putcha**, L. Nyns*, A. Sibaja- [Shunju I, II, III] Hernandez*, R. Rooyackers*, S. C. Ardila*, V. Spampinato*, A. Tuesday, June 6, 10:30-12:30 Franquet*, J. W. Maes***, Q. Xie***, M. Givens****, F. Chairpersons: M. Ikeda, The Univ. of Tokyo Tang****, X. Jiang****, M. Heyns**, D. Linten*, J. Mitard*, A. K. Chang, Xilinx Inc. Thean*****, D. Mocuta* and N. Collaert*, *imec, **also at KU Leuven, ***ASM Belgium, Belgium, ****ASM America, USA C1-1 - 10:30 and *****currently at National Univ. of Singapore, Singapore 24 Welcome and Opening Remarks M. Motomura, Hokkaido Univ. T3-4 - 15:15 G. Lehmann, Infineon Technologies AG High Performance and Low Leakage Current InGaAs-on- Silicon FinFETs with 20 nm Gate Length, X. Sun*, C. C1-2 - 10:50 (Plenary) D’Emic*, C.-W. Cheng*, A. Majumdar*, Y. Sun*, E. Cartier*, R. Innovative Solutions toward Future Society with AI, L. Bruce*, M. Frank*, H. Miyazoe*, K.-T. Shiu*, S. Lee**, J. Robotics, and IoT, T. Yukitake, Panasonic Corp., Japan N/A Rozen*, J. Patel*, T. Ando*, W.-B. Song**, M. Lofaro*, M. Krishnan*, B. Obrodovic***, K.-T. Lee*, H. Tsai*, W.-E. C1-3 - 11:40 (Plenary) Wang***, W. Spratt*, K. Chan*, S. Lee*, J.-B. Yau*, P. Hashemi*, Inside Waymo's Self-Driving Car: My Favorite Transistors, M. Khojasteh*, M. Cantoro**, J. Ott*, T. Rakshit***, Y. Zhu*, D. D. L. Rosenband, Waymo, USA N/A Sadana*, C.-C. Yeh*, V. Narayanan*, R. T. Mo*, Y.-C. Heo**, D.-W. Kim**, M. S. Rodder*** and E. Leobandung*, *IBM T. J. SESSION 2 - Technology Focus Session - Nonvolatile & Watson Research Center, USA, **Samsung Electronics Co., Ltd., Embedded Memory [Shunju II, III] Korea and ***Samsung Advanced Logic Lab, USA 26 Tuesday, June 6, 14:00-15:40 Chairpersons: S. S. Chung, National Chiao Tung Univ. SESSION 4 - Technology Focus Session - 1D and 2D K. Baker, Freescale Semiconductor, Inc. / Atomic Thin Materials and Devices [Shunju II, III] NXP Semiconductors N.V. Tuesday, June 6, 16:00-17:40 Chairpersons: K. Uchida, Keio Univ. T2-1 - 14:00 (Invited) E. Pop, Stanford Univ. Memory Technology for the Terabit Era: from 2D to 3D, J. Van Houdt, KU Leuven and imec, Belgium 12 T4-1 - 16:00 (Invited) Scaling, Stacking, and Printing: How 1D and 2D T2-2 - 14:25 (Invited) Nanomaterials still Hold Promise for a New Era of Embedded Memories for Mobile, IoT, Automotive and Electronics, A. D. Franklin, Duke Univ., USA 28 High Performance Computing, J. Chang, H.-J. Liao, Y.-D. Chih, M. Sinangil, Y.-H. Chen, M. Clinton and S.-L. L. Lu, TSMC, T4-2 - 16:25 (Invited) Taiwan 14 One and Two Dimensional Nanocarbon Materials for Innovative Functional Devices, S. Sato, Fujitsu Laboratories T2-3 - 14:50 Ltd. and Fujitsu Ltd., Japan A Low-Power Cu Atom Switch Programmable Logic 30 Fabricated in a 40nm-Node CMOS Technology, X. Bai, T. T4-3 - 16:50 Sakamoto, M. Tada, M. Miyamura, Y. Tsuji, A. Morioka, R. Experimental Demonstration of Electrically-Tunable Nebashi, N. Banno, K. Okamoto, N. Iguchi, H. Hada and T. Bandgap on 2D Black Phosphorus by Quantum Confined Sugibayashi, NEC Corp., Japan 16 Stark Effect, L. Yang*, Y.-M. Lin**, W. Tsai** and P. D. Ye*, *Purdue Univ., USA and **TSMC, Taiwan 32 T2-4 - 15:15 A Cross Point Cu-ReRAM with a Novel OTS Selector for Storage Class Memory Applications, S. Yasuda, K. Ohba, T. Mizuguchi, H. Sei, M. Shimuta, K. Aratani, T. Shiimoto, T. Yamamoto, T. Sone, S. Nonoguchi, J. Okuno, A. Kouchiyama, W. Otsuka and K. Tsutsui, Sony Semiconductor Solutions Corp., Japan 18 vi T4-4 - 17:15 SESSION 6 - Highlight [Shunju I, II, III] Statistical Analyses of Random Telegraph Noise Wednesday, June 7, 8:30-10:10 Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon Chairpersons: Y.-C. Yeo, TSMC Nanowire Transistors, H. Qiu*, K. Takeuchi*, T. Mizutani*, T. W. Rachmady, Intel Corp. Saraya*, J. Chen**, M. Kobayashi* and T. Hiramoto*, *The Univ. of Tokyo, Japan and **Shandong Univ., China 34 T6-1 - 8:30 Highly Manufacturable 7nm FinFET Technology SESSION 5 - Hetero Integration [Shunju I] Featuring EUV Lithography for Low Power and High Tuesday, June 6, 16:00-17:40 Performance Applications, D. Ha, C. Yang, J. Lee, S. Lee, S. Chairpersons: T. Tanaka, Tohoku Univ. H. Lee, K.-I. Seo, H. S. Oh, E. C. Hwang, S. W. Do, S. C. Park, N. Collaert, imec M.-C. Sun, D. H. Kim, J. H. Lee, M. I. Kang, S.-S. Ha, D. Y. Choi, H. Jun, H. J. Shin, Y. J. Kim, J. Lee, C. W. Moon, Y. W. Cho, S. H. T5-1 - 16:00 Park, Y. Son, J. Y. Park, B. C. Lee, C. Kim, Y. M. Oh, J. S. Park, S. Wafer Level Integration of an Advanced Logic-Memory S. Kim, M. C. Kim, K. H. Hwang, S. W. Nam, S. Maeda, D.-W. System Through 2nd Generation CoWoS® Technology, W. Kim, J.-H. Lee, M. S. Liang and E. S. Jung, Samsung Electronics C. Chen, C. Hu, K. C. Ting, V. Wei, T. H. Yu, S. Y. Huang, V. C. Y. Co., Ltd., Korea 46 Chang, C. T. Wang, S. Y. Hou, C. H. Wu and D. Yu, TSMC, Taiwan 36 T6-2 - 8:55 T5-2 - 16:25 10nm High Performance Mobile SoC Design and Enabling Low Power and High Speed OEICs: First Technology Co-Developed for Performance, Power, and Monolithic Integration of InGaAs n-FETs and Lasers on Area Scaling, S. Yang*, Y. Liu*, M. Cai*, J. Bao*, P. Feng*, X. Si Substrate, A. Kumar*, S.-Y. Lee**, S. Yadav*, K. H. Tan**, Chen*, L. Ge*, J. Yuan*, J. Choi*, P. Liu*, Y. Suh*, H. Wang*, J. W. K. Loke**, D. Li**, S. Wicaksono**, G. Liang*, S.-F. Yoon**, Deng*, Y. Gao*, J. Yang*, X.-Y. Wang*, D. Yang*, J. Zhu*, P. X. Gong*, D. Antoniadis*** and Y.-C. Yeo*, *National Univ. of Penzes*, S. C. Song*, C. Park**, S. Kim**, J. Kim**, S. Kang**, Singapore, **Nanyang Technological Univ., Singapore and E. Terzioglu*, K. Rim* and P. C. Chidambaram*, *Qualcomm ***Massachusetts Institute of Technology, USA 38 Technologies Inc., USA and **Samsung Electronics Co., Ltd., Korea 48 T5-3 - 16:50 Enhancement-Mode N-Channel TFT and Room- T6-3 - 9:20 Temperature Near-Infrared Emission Based on n+/p First Demonstration of Flash RRAM on Pure CMOS Logic Junction in Single-Crystalline GeSn on Transparent 14nm FinFET Platform Featuring Excellent Immunity to Substrate, H. Oka, M. Koyama, T. Hosoi, T. Shimura and H. Sneak-Path and MLC Capability, E. R. Hsieh*, Y. C. Kuo**, Watanabe, Osaka Univ., Japan 40 C. H. Cheng*, J. L. Kuo*, M. R. Jiang*, J. L. Lin*, H. W. Cheng*, S. S. Chung*, C. H. Liu**, T. P. Chen***, Y. H. Yeah***, T. J. T5-4 - 17:15 Chen*** and O. Cheng***, *National Chiao Tung Univ., High Vth Enhancement Mode GaN Power Devices with **National Taiwan Normal Univ. and ***United Microelectronics High ID,max Using Hybrid Ferroelectric Charge Trap Gate Corp., Taiwan 50 Stack, C. H. Wu*, S. C. Liu*, C. K. Huang*, Y. C. Chiu*, P. C. Han**, P. C. Chang*, F. Lumbantoruan*, C. A. Lin*, Y. K. Lin*, C. T6-4 - 9:45 Y. Chang*, C. Hu***, H. Iwai*,** and E. Y. Chang*, *National First Demonstration of 3D SRAM Through 3D Monolithic Chiao Tung Univ., Taiwan, **Tokyo Institute of Technology, Japan Integration of InGaAs n-FinFETs on FDSOI Si CMOS with and ***Univ.
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