A Field Programmable Transistor Array Featuring Single-Cycle Partial

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A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconﬁguration Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz Jr., Yiorgos Makris and Carl Sechen Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080 Email: {jxt122130, gxr141930, jxw143630, wps100020, gxm112130, cms057000}@utdallas.edu

Abstract—We introduce a CMOS computational fabric con- In the following, we discuss the FPTA architecture and sisting of carefully arranged regular rows and columns of tran- design features which support each of the above three ob- sistors which can be individually configured and appropriately jectives (Sections II-IV). To demonstrate the aforementioned interconnected in order to implement a target digital circuit. Termed Field Programmable Transistor Array (FPTA), this capabilities, we designed and laid out an FPTA prototype in novel reconfigurable architecture enables several highly-desirable the IBM 130nm 1.2V process and we developed a CAD tool features including (i) simultaneous storage of three configurations flow (Section V) to synthesize, place and route designs onto it. along with the ability to dynamically switch between them Results using various benchmark circuits (Section VI) confirm in a fraction of a single cycle, while retaining the fabric’s that, despite the added features of single-cycle switching computational state, (ii) rapid or full modification of a stored configuration in a time proportional to the number of modified between multiple designs and rapid partial reconfiguration, configuration bits through the use of hierarchically arranged, our FPTA achieves better area utilization in comparison to high throughput, asynchronously pipelined memory buffers, and a typical FPGA in the same technology node. (iii) support for libraries containing cells of the same height and variable width, just as in a typical standard cell circuit, thereby II. TRANSISTOR-LEVEL PROGRAMMING simplifying transition from a prototype to a custom IC design. Besides presenting the design details of this fabric in a 130nm To present our FPTA’s ability to support transistor-level pro- technology and demonstrating the aforementioned capabilities, gramming, we first describe its overall architecture, including we also briefly discuss the development of a complete CAD flow the basic logic cell structure and the routing resources. for programing this fabric and we use numerous benchmark circuits to contrast its area efficiency against a typical FPGA A. FPTA Architecture Overview implemented in the same technology node. The FPTA architecture, which resembles a standard cell I. INTRODUCTION circuit, consists of numerous long rows of transistors and can work with cell libraries similar to those used for a typical We present a novel field programmable device, developed standard cell-based ASIC, where each cell has the same height on conventional static CMOS processes, which has significant and variable width. In the FPTA, the granularity of the width differences and potential advantages over field programmable of the cells is one column of transistors. As shown in Fig. gate arrays (FPGAs). Specifically, our design seeks to: 1(a), a column consists of two pMOS transistors above two 1) Improve area utilization: Unlike the basic configurable nMOS transistors. This basic column is replicated repeatedly logic block (CLB) of FPGAs, which employs look-up tables in the horizontal direction, forming a row. Vertical transistors (LUTs) to generate combinational logic functions [1], our in Fig. 1(a) can be programmed to be always on, always off, FPTA relies on a carefully-arranged, configurable array of or to receive logic signals. Among the horizontal transistors, transistors, which can be interconnected to implement standard while the innermost (blue-colored) ones are strictly used for library cells. Thereby, for logic outside the custom cells isolation, the outermost ones not only support isolation but (e.g., full adders, D flip-flops, multiplexers) that both FPGAs also enable the use of logic functions that require up to and our FPTA explicitly possess, we surmise that transistor three transistor in series. The metal1 (M1) layer is used to utilization in our FPTA is better than in FPGA LUTs. In other interconnect the transistors and various logic gates. words, an FPGA may allocate an entire LUT to implement The actual hardware implementation of the row-based FPTA even a relatively simple gate, while our FPTA allocates only groups every four columns of transistors into so-called ‘logic the precise number of columns of transistors required. cells’. In Fig. 1(a), a potential logic gate output is illustrated 2) Enable time-sharing between multiple circuits: Our by means of a small green rectangle. Each potential output design supports simultaneous storage of three separate con- is optionally connected to a vertical metal2 (M2) track, by figurations, each with its own computational state. Therefore, means of a programmed switch. In addition, the two pMOS we also provide the means to switch, in a fraction of a single and the two nMOS inputs in a column are directly connected cycle, between any of the three stored configurations, or load to individual vertical M2 tracks. Each of these tracks is driven a new configuration while toggling between the other two. by either a programming bit or a logic signal. 3) Support rapid circuit updates: Instead of being serially In addition to the four columns of transistors, each logic loaded, our FPTA configuration is stored in hierarchically cell comes with a custom D-flip-flop (DFF), a full adder arranged, high throughput, asynchronously pipelined memory (FA) and a multiplexer (MUX), whose inputs and outputs buffers. This enables not only faster configuration but also (I/Os) are optionally connected to logic cell I/Os. The D input rapid dynamic partial reconfiguration wherein only a portion of (Signal in) of the DFF, which is shown in Fig. 1(b), is either a circuit is reloaded by addressing specific transistor columns. connected to a logic transistor in the first column of the logic

978-3-9815370-8-6/17/$31.00 c 2017 IEEE 1336

07Dsg,Atmto n eti uoe(DATE) Europe in Test and Automation Design, 2017 1337

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07Dsg,Atmto n eti uoe(DATE) Europe in Test and Automation Design, 2017 1338

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(a) (b) (d) Fig. 5: (a) Local memory structure, (b) Asynchronous memory buffer pipeline, (c) Memory buffer, and (d) Muller C-element In summary, it is possible to store the programming for three bits, the various memory buffers are, in fact, bi-directional; separate systems and switch between them in a fraction of a for brevity, this part is not presented here. clock cycle, or toggle between two systems while loading a Fig. 5(c) shows the structure of the programming bit register. third one. In order to properly enable toggling between running The clk triggers the DFF to pass the data from the bus to systems, not unlike swapping jobs in a central processing unit the BL. The DFFs in the L2, L1, and L0 memory buffers are of a computer, separate system or finite state machine flip- controlled by distinct clk signals. These clk signals are derived flops must be available for each copy signal. Along those lines, from an asynchronous pipeline control unit, described next. with respect to Fig. 1(b) which was simplified, there is not just B. Programming Bit Asynchronous Pipeline one flip-flop whose output may optionally appear at the first column of each logic cell, but, in fact, three different flip-flops We use an asynchronous pipeline to achieve a high program- enabled by, respectively, cpa, cpb,orcpc. ming rate. For example, after an L2 memory buffer receives a 33-bit payload from off-chip, it forwards it (along with the IV. RAPID PARTIAL RECONFIGURATION address) to the corresponding L1 memory buffer as soon as the latter is ready to receive it. When the L1 memory buffer Lastly, we describe the architecture through which the FPTA receives the address and payload, the L2 memory buffer is configurations are stored and we explain how they can be freed to accept a new address and payload from off-chip. The selectively updated to support rapid partial reconfiguration. rate at which programming bits can be sent from off-chip is extremely high. In fact, detailed circuit simulations show that A. Memory Buffers L2, L1 and L0 the programming bit data rate is nominally 9.0 Gbps. The Level 0 Memory (L0) shown on the left side of Fig. 4 is We used a bounded-delay asynchronous pipeline control actually a memory buffer used to supply programming bits to scheme [3]. Each stage of the asynchronous pipeline consists the local memory for each of the 8 units comprising the block. of a Muller C-element, shown in Fig. 5(d). When a stage Each unit has 16 columns, each of which contains a payload Ri receives a request (req) from the previous stage Ri-1, if of 33 programming bits. The total number of columns for each the acknowledge (ack) from the next stage Ri+1 is available group is, therefore, 16 x 8, or 128. This means that 7 address (active low), then a request is generated to Ri+1 along with bits must be appended to the 33-bit payload to direct it to the an acknowledge to Ri-1. proper column. Three of the address bits select a unit and the The asynchronous control scheme for writing programming remaining four select a column within that unit. Thus, when bits to the local memories is shown in Fig. 6. The signal clki writing a 33-bit payload to a local memory, the L0 Memory (where i is the stage index of the memory buffer) is generated buffer passes a word of 40 bits to the group. by the logical AND of Ri and the inversion of the (bounded) We designed an asynchronous memory buffer pipeline to delayed Ri. This is basically a pulse generator that ensures rapidly program the FPTA. Our prototype has six groups that the various local clocks (clki) are non-overlapping in their horizontally and four groups vertically, as shown in Fig. high portions. The signal clki is used to trigger the DFFs in 5(b). When writing programming bits, L0 memory buffers are the Li memory buffer, as shown in Fig. 5(c). R2 receives the supplied by Level 1 memory buffers (L1). Each L1 memory request to write programming bits (RQ WR) from off-chip. buffer supplies a word to one of four L0 memory buffers, Since the L2 memory buffer feeds any of six L1 memory arranged vertically. The word size for the L1 memory is 42 buffers in the prototype, acknowledge signals from all six of bits: 40 bits needed by the selected L0 memory buffer plus them are OR-ed to form the acknowledge for R2. Also, since 2 address bits to select that L0 memory buffer. The six L1 each L1 memory buffer feeds any of four L0 memory buffers, memory buffers are fed by a Level 2 memory buffer (L2), acknowledge signals from all four of them are OR-ed to form as shown in Fig. 5(b)). Its word size consists of 45 bits: 42 the acknowledge for R1. The local memory driven by the L1 bits needed by an L1 memory buffer plus 3 bits to select memory buffer is controlled by local clock clk00. Note that the particular L1 memory buffer. An off-chip memory then the last stage uses the delayed request as its acknowledge. supplies 45-bit words to the L2 memory buffer. In order to The delay elements (Ds), shown in Fig. 6, are set based facilitate fast (i.e., pipelined) read-out of the programming on careful worst-case simulation of the extracted layout of the

2017 Design, Automation and Test in Europe (DATE) 1339 3 2 decoder decoder TABLE I: Area utilization compared to a commercial FPGA RQ_WR Benchmark Cell Count FPTA Altera OR6 OR4 (Synopsys Utilization Stratix ...... DC) Utilization

B04 317 1.02% 2% R2 R1 R0 R00 B05 353 1.29% 2% B12 539 2.02% 4% D D D D SPI 1240 4.27% 8% B14 2123 8.69% 10% Tv80 3077 11.13% 19% clk2 clk1 clk0 clk00 B15 3461 12.18% 22% B20 4407 17.78% 20% Fig. 6: Asynchronous write-in control scheme B21 4635 19.07% 20% B22 6702 26.85% 29% B17 10942 37.75% 68% AES cipher 9422 38.91% 47% AES inv cipher 13578 52.07% 72% WB conmax 16436 70.00% 148% ∗ B18 25303 87.85% 140%

(∗) One instance of B15 is removed from B18 to reduce the size of the benchmark in order to ensure that it ﬁts within the available resources

Fig. 7: Layout of prototype comprising a 6X4 array of groups, (Versatile Place and Route) [5], [6] to make it compatible with each group comprising 8 logic cells our architecture. Finally, bit-stream generation is done through a Python script which we developed for this purpose. prototype. Since this pipeline is used for programming bits and VI. DEMONSTRATIONS is not a signal datapath, maximum throughput is not required. Therefore, we conservatively double the worst-case simulated We designed and laid out a prototype for fabrication using delay (including worst-case corner) to set the delay element the IBM 130nm 1.2V process. It includesa6x4array of value with sufficient margin to handle process, voltage, and groups, each containing 8 logic cells, for a total of 192 logic temperature (PVT) variations. cells. The layout is shown in Fig. 7, and its overall size is 4113.41um x 2769.50um. V. C ELL LIBRARY AND CAD TOOL FLOW Our base library consists of all the possible inverting gates A. Area Utilization Efficiency that are feasible with our FPTA and its series limit of three In order determine the area utilization efficiency of our transistors. The 24 base library components are: INV, NAND2, FPTA, we compared it with a commercial FPGA, Altera NOR2, AOI12, AOI22, OAI12, OAI22, NAND3, NOR3, Stratix EP1S10, which uses the same 130nm technology and AOI31, OAI31, AOI41, OAI41, AOI32, OAI32, AOAI311, has a core size of 23mm X 23mm [7]. To make a fair OAOI311, AOAI211, OAOI211, AOOAI212, OAAOI212, comparison, we scaled up our FPTA to the same size, resulting AOAAI2111, OAOOI2111 and MAJI (which is the inverted in an array of 51 x 35 groups of 8 logic cells, for a total of mirror carry). In addition, the following custom cells are built 14,280 logic cells. We then implemented various benchmarks into the logic cells: FA, FAI, DFF, MUX and MUXI. from ITC’99 [8] and opencores [9] on both our FPTA and To further increase logic density, following the philosophy the Altera chip. A comparison of the resource utilization is of [2], numerous compounds of the 24 base library cells are presented in Table I. Note that the same switchbox sizes were also provided. Compound cells are created by appending an used throughout the scaled up array and the benchmarks were inverter (or a NAND2 or NOR2) to one input and/or the 100% routed. output of each of the 24 base cells, resulting in a total of 234 Despite the additional area overhead due to having three compound cells. Compound cells are placed as a unit but are memory cells per programming bit, the density (or utilization) decomposed into their constituent base cells prior to routing. of the FPTA is quite competitive with the Altera chip. We We also developed the necessary CAD tool-flow for pro- attribute this observation to the fact that for logic outside the gramming the FPTA. Our tool-flow consists of industry- custom cells (e.g., full adders, carry units, flip-flops, multi- standard commercial tools along with open-source software plexers) that both designs possess, the transistor utilization which has been modified to work with our architecture. Syn- of the logic cells in the FPTA is better than the transistor opsys Design Compiler is used to synthesize a gate-level netlist utilization of the LUTs in the Altera design. Essentially, even from the Register-Transfer Level (RTL) description of the a relatively simple logic function might take up an entire LUT, design. The cell library, consisting of 24 base cells, 11 built-in whereas in the FPTA, only the precise number of columns cells and 234 compounds was characterized using Synopsys needed to implement the gate are used. Thus, simple gates SiliconSmart. Placement is done through TimberWolf [4], such as NAND2, NAND3, NOR2, NOR3, and up to three or which is very effective in row-based placement. For routing, even four input AOI and OAI gates are comparatively very we modified the source code of the open-source tool VPR area-efficient in the FPTA.

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