EE141-Fall 2010 Digital Integrated Circuits

MOS Capacitance Lecture 11 MOS Capacitance and Delay

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Announcements MOS Capacitances G ‰ No lab Fri., Mon. ƒ Labs restart next week CGS CGD = C + C GCS GSO = CGCD + CGDO ‰ Midterm #1 Thurs. Oct. 7th, 6:30-8:00pm SD ƒ Exam is open notes, book, calculators, etc. CSB CGB CDB = C = Cdiff diff = CGCB B

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Class Material Gate Capacitance

‰ Last lecture ƒ Using the MOS model: Inverter VTC ‰ Today’s lecture ƒ MOS Capacitance ƒ Using the MOS Model: Delay ‰ Reading (3.3.2, 5.4.2) ‰ Capacitance (per area) from gate across ε the oxide is W·L·Cox, where Cox= ox/tox

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S W D L

C OL C G C OL xj C JC CjSB C jDB

‰ Distribution between terminals is complex LD ƒ Capacitance is really distributed ƒ Channel is formed and acts as the other terminal –C drops to zero (shielded by channel) – Useful models lump it to the terminals GCB ƒ Several operating regions: ƒ Model by splitting oxide cap equally between source and drain – Way off, off, transistor linear, transistor saturated – Changing either voltage changes the channel charge 7 10 EECS141EE141 Lecture #11 7 EECS141EE141 Lecture #11 10

Transistor In Cutoff Transistor in Saturation Region G G

S D W S W D L L

C OL C GB C OL C OL C G C OL x j x j C JC C jSB C jDB CjSB CjDB

LD ƒ When the transistor is off, no carriers in channel ƒ Changing source voltage doesn’t change V to form the other side of the capacitor. GC uniformly – Substrate acts as the other capacitor terminal – E.g. V at pinch off point still V – Capacitance becomes series combination of gate GC TH oxide and depletion capacitance ƒ Bottom line: CGCS ≈ 2/3·W·L·Cox

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Transistor In Cutoff (cont’d) Transistor in Saturation Region (cont’d)

G G

S D W S W D L L

C OL C GB C OL C OL C G C OL x j x j C JC C jSB C jDB CjSB CjDB ƒ When |V | < |V |, total C much smaller than LD GS T GCB ƒ Drain voltage no longer affects channel charge W·L·Cox – Set by source and VDS_sat – Usually just approximate with CGCB = 0 in this region.

ƒ (If VGS is “very” negative (for NMOS), depletion ƒ If change in charge is 0, CGCD = 0 region shrinks and CGCB goes back to ~W·L·Cox) 9 12 EECS141EE141 Lecture #11 9 EECS141EE141 Lecture #11 12 Gate Capacitance Diffusion Capacitance

NA+ ƒ Bottom Side wall –Area cap Source –C = C ·L ·W W bottom j S ND Bottom ƒ Sidewalls xj Side wall – Perimeter cap Channel LS Substrate –Csw = Cjsw·(2LS+W) NA C vs. V gate GS Cgate vs. operating region (with VDS = 0) ƒ GateEdge

–Cge = Cjgate·W – Usually automatically included in the SPICE model 13 16 EECS141EE141 Lecture #11 13 EECS141EE141 Lecture #11 16

Gate Overlap Capacitance Junction Capacitance (2)

Polysilicon gate 1.0

ƒ Junction caps 0.9 Gate oxide are nonlinear 0.8 tox –CJ is a Source Drain 0.7 W n+ L n+ function of n+ xd xd n+ junction bias 0.6 N+ junction area Capacitance [arbitrary units] Cross section 0.5 N+ junction perimeter P+ junction area Gate-bulk P+ junction perimeter L d overlap ƒ SPICE model 0.4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 = ⋅ Node voltage (V) Top view CO Cox xd equations: φ mj – Area CJ = area × CJ0 / (1+ |VDB|/ Β) φ mjsw – Perimeter CJ = perim × CJSW / (1 + |VDB|/ Β) Off/Lin/Sat Æ CGSO = CGDO = CO·W φ mjswg – Gate edge CJ = W × CJgate / (1 + |VDB|/ Β)

ƒ How do we deal with nonlinear capacitance? 14 17 EECS141EE141 Lecture #11 14 EECS141EE141 Lecture #11 17

Gate Fringe Capacitance Linearizing the Junction Capacitance

Fringing fields Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest n+ n+

Cross section

ƒ COV not just from metallurgic overlap – get fringing fields too

ƒ Typical value: ~0.2fF·W(in µm)/edge

15 18 EECS141EE141 Lecture #11 15 EECS141EE141 Lecture #11 18 Capacitance Model Summary Capacitance Model Summary Model Calibration - Capacitance ‰ Gate-Channel Capacitance ƒ C ≈ 0(|V| < |V |) GC GS T ƒ Can calculate Cg, Cd based on tech. parameters ƒ CGC = Cox·W·Leff (Linear) – But these models are simplified too – 50% G to S, 50% G to D ƒ Another approach: ƒ CGC = (2/3)·Cox·W·Leff (Saturation) – 100% G to S – Tune (e.g., in spice) the linear capacitance until it makes the simplified circuit match the real circuit ‰ Gate Overlap Capacitance – Matching could be for delay, power, etc.

ƒ CGSO = CGDO = CO·W (Always)

Cload ‰ Junction/Diffusion Capacitance Delay1 Match Delay2

ƒ Cdiff = Cj·LS·W + Cjsw·(2LS + W) + CjgW(Always)

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Capacitances in 0.25 µm CMOS Process Model Calibration for Delay

A Cload Delay1 Match Delay2

ƒ For gate capacitance: – Make inverter fanout 4

– Adjust Cload until Delay1 = Delay2 ƒ For diffusion capacitance – Replace inverter “A” with a diffusion capacitance load

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Simplified Model Delay Calibration ƒ Capacitance models important for analysis 1 4 16 64 and intuition – But often need something simpler to work with

ƒ Simple switch model: Delay

– Lump together as effective linear capacitance to "Edge Shaper" Load ??? (ac) ground

– In most processes: CG = CD = 1.5 – 2fF·W(µm) ƒ Why did we need that last inverter stage?

V Vin out Vin Vout

CL

21 24 EECS141EE141 Lecture #11 21 EECS141EE141 Lecture #11 24 The Miller Effect MOS Transistor as a Switch ƒ As V increases, V drops in out C – Once get into the transition region, gain gd1 ‰ Saw that real transistors aren’t exactly ∆V Vout from Vin to Vout > 1 resistors ∆V Vin ƒ Look more like current sources in saturation ƒ So, Cgd experiences voltage swing M1 larger than Vin – Which means you need to provide more charge ‰ Two questions: – Makes C look larger than it really is gd ƒ Which region of IV curve determines delay?

ƒ Known as the “Miller Effect” in the ƒ How can that match up with the RC model? analog world

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Transistor Driving a Capacitor • With a step input:

VDD Æ VDD/2 ID VGS = VDD CMOS Switching Delay VDS

VVSAT VDD /2 VDD

• Transistor is in (velocity) saturation during entire transition

from VDD to VDD/2

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MOS Transistor as a Switch Switching Delay • Discharging a capacitor • In saturation, transistor basically acts like a current source: V V OUT i = i ()v OUT D D DS V C DD dVDS I C i = C DSAT V /2 D dt DD • We modeled this with: t t R p

C tp = ln (2) RC VOUT = VDD -(IDSAT/C)t tp = C(VDD/2)/IDSAT

27 30 EECS141EE141 Lecture #11 27 EECS141EE141 Lecture #11 30 Switching Delay (with Output Conductance) The Book’s Method • Including output conductance:

VOUT

IDSAT 1/(λIDSAT) C

−−() + 11-t C λIDSAT V=VOUT() DD λ e - λ

CV()2 •For “small”λ: t ≈ DD p ()+ 1 λVIDDDSAT

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RC Model The Transistor as a Switch

5 x 10 • Transistor current not linear on VOUT –how is the RC 7 model going to work? 6 • Look at waveforms: 2.5 5 2.3 • Voltage looks like a 2.1 4

1.9 (Ohm)

ramp for RC too 3eq 1.7 NMOS R OUT V 1.5 2

1.3 1 RC 1.1 0 0.9 0.5 1 1.5 2 2.5 V (V) DD 0 0.2 0.4 0.6 0.8 1 t/τ 32 35 EECS141EE141 Lecture #11 32 EECS141EE141 Lecture #11 35

Finding Req The Transistor as a Switch • Match the delay of the RC model with the actual delay:

t=tppRC, () CVDD 2 ()V 2 = ln() 2 RC R = DD ()+ eq eq ()(+ ) 1 λVIDD DSAT ln 2 1 λVIDDDSAT

1 V • Often just: R ≈ DD eq ⋅ () 2ln2 IDSAT

• Note that the book uses a different method and gets

0.75·VDD/IDSAT instead of ~0.72·VDD/IDSAT. • Why did we do it this way vs. the book’s method?

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