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CuEval2 Report Bin Wei 8/13/2004 Introduction zBelle DAQ system Introduction (cont) zCurrent Readout subsystem uses FASTBUS as system bus. zWeakness of FASTBUS ySlow trigger rate: 100-250Hz yBandwidth: around 10MB/s yCPU have to control whole transfer procedure. Introduction(cont) zCOPPER readout subsystem yfast trigger rate: 10k-40kHz yBandwidth: 125MB/s (33MHz, 32bit PCI bus) yUsing DMA mode directly transfer data to memory without CPU control yThere are lots of PCI modules we can choose (Radisys 6315 as embeded CPU platform) COPPER II PMCPMC ADC/TDC VMEVME--9U9U sizedsized boardboard ProcessorProcessor ••44 ADC/TDCADC/TDC slotsslots ADC/TDC ••11 MBMB ×× 44 FIFOFIFO ••3232--bitbit locallocal busbus ADC/TDC ADC/TDC ••33 PMCPMC slotsslots Trigger ••3232--bitbit 33MHz33MHz PCIPCI busbus ADC/TDC Trigger ••LocalLocal--PCIPCI bridgebridge ADC/TDC Generic On-board Ether PMC slot ••VMEVME I/FI/F On-board Ether COmmon Pipelined Platform for Electronics Readout COPPER II CuEval system Send test data Receive test data Test system Status info ReadOut CPU Singal Monitor system Detector PCI NIC Event data Event builder CoPPER CuEval board zCuEval I y16 local bus yserial FPGA setup x(need continuous data) zCuEval II y32 local bus yparallel FPGA setup CuEval board concept Pin Pong strategy MEM USB FPGA Local bus MEM MEM Local bus USB FPGA MEM CuEval2-Firmware (FPGA) USB Empty USB Read MEM address Fetch Ram A Counter clock Mem Full Switch Switch Control Mem Full Event FIFO Send Counter clock Ram B FULL MEM address Event FIFO Write Switch memory when one is full, another is empty Ram Data USB Data Switch Switch Event FIFO Data Ram Data CuEval2-Firmware (CPLD) Reset Clear FPGA Program Disable Write Parallel write FPGA Write Enable Write command Init command Address Address Command Initialize Analyzer Analyzer FPGA Program FPGA Init done Local Data FPGA Data CuEval-Test system (PC) Send queue CuEval2 Input Package data USB Typing File Automatic Receive queue Net Output unpackage data COPPER II Compare CuEval-Test system (PC) Event FIFO readout (Linux) PCI Event data Send data queue Interrupt queue (Pin Pong) Event Net Test system Event data FIFO Package data Process Ethernet or Terminal Monitor Commad Status Situation zCuEval II board hardware design yon July 2004 zCuEval II board firmware design yFPGA update (this week) yCPLD update (3 bit-7 bit address) zTest system software design (windows finished) Situation (cont) zEvent data Readout software design (Linux) yUnderstand new device driver yCPU readout yDMA readout.

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