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SIS4100 VME to FASTBUS Interface User Manual

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SIS4100 VME to FASTBUS Interface User Manual SIS Documentation SIS4100 FASTBUS Master SIS4100 VME to FASTBUS Interface User Manual SIS GmbH Moorhof 2d 22399 Hamburg Germany Phone: ++49 (0) 40 60 87 305 0 Fax: ++49 (0) 40 60 87 305 20 email: [email protected] http://www.struck.de Version: 1.01 as of 27.07.99 Page 1 of 57 SIS Documentation SIS4100 FASTBUS Master Revision Date Modification 0.1 01.02.99 Generation 1.0 26.07.99 First official release 1.01 27.07.99 some additions Copyright note: You are welcome to copy or reproduce this manual in part or whole as long as SIS GmbH is clearly indicated as originator (by the SIS GmbH FASTBUS icon on the top of the page e.g.). Page 2 of 57 SIS Documentation SIS4100 FASTBUS Master Table of contents 1 Introduction..................................................................................................................................................... 5 2 NGF Working Principle .................................................................................................................................. 6 3 Design ............................................................................................................................................................. 7 3.1 Features ................................................................................................................................................... 7 3.2 Mechanical concept................................................................................................................................. 7 3.3 VME properties....................................................................................................................................... 7 4 VME slave port ............................................................................................................................................... 8 4.1 VME Address space................................................................................................................................ 8 4.2 VME Address map.................................................................................................................................. 9 4.3 VME Register description..................................................................................................................... 10 4.3.1 Internal FASTBUS I/O Bus (0x1000, Read)................................................................................. 10 4.3.2 VME out register (0x1000, Write) ................................................................................................ 11 4.3.3 FASTBUS last primary address register (0x1x04, Read).............................................................. 12 4.3.4 Internal AUX-port register (0x1x10, Write) ................................................................................. 12 4.3.5 FASTBUS timeout register (0x2x00, READ/Write)..................................................................... 13 4.3.6 FASTBUS Arbitration level register (0x2x04, read/write) ........................................................... 14 4.3.7 FASTBUS protocol register (0x2x08, read).................................................................................. 15 4.3.8 Sequencer FIFO flag and ECL/NIM input register (0x2x0C, read) .............................................. 16 4.3.9 VME IRQ level and vector register (0x2x10, Read/Write)........................................................... 17 4.3.10 VME IRQ source and mask register (0x2x14, Read/Write).......................................................... 18 4.3.11 Next sequencer RAM address register (0x2x18, Read/Write) ...................................................... 19 4.3.12 Last sequencer protocol register (0x2x1C Read) .......................................................................... 20 4.3.13 Sequencer Status Register (0x2x20 Read) .................................................................................... 21 4.3.14 FASTBUS primary status register (0x2x24 Read)........................................................................ 22 4.3.15 FASTBUS data status register (0x2x28 Read)............................................................................. 23 4.3.16 Pedestal Pointer Register (0x2x000, read/write) ........................................................................... 24 4.3.17 Pedestal and Remap Register (0x2x004, read/write)..................................................................... 24 4.4 Minimum operation test ........................................................................................................................ 25 5 VME interrupt sources .................................................................................................................................. 26 6 Sequencer...................................................................................................................................................... 28 6.1 Sequencer enable/arm ........................................................................................................................... 28 6.2 Sequencer command structure............................................................................................................... 29 6.3 FASTBUS action sequencer command structure .................................................................................. 30 6.3.1 VME mode and limit counter........................................................................................................ 31 6.3.2 Block transfer restrictions ............................................................................................................. 32 6.3.3 DMA status and word counter....................................................................................................... 33 6.4 Sequencer control action command structure........................................................................................ 34 6.4.1 Sequencer out register ................................................................................................................... 35 7 Pedestal Subtraction Unit (PSU)................................................................................................................... 36 7.1 Configuration of pedestal subtraction ................................................................................................... 37 7.2 Example LRS 1885F ADC.................................................................................................................... 37 7.3 Event length determination ................................................................................................................... 38 8 Front panel elements ..................................................................................................................................... 39 8.1 LEDs ..................................................................................................................................................... 39 8.1.1 LED self test.................................................................................................................................. 40 8.2 Connectors ............................................................................................................................................ 40 9 AUX interface............................................................................................................................................... 42 9.1 Trigger interface.................................................................................................................................... 42 9.2 Direct mode interface............................................................................................................................ 43 9.2.1 Trigger interface examples............................................................................................................ 43 10 Jumper and rotary switch locations and functions .................................................................................... 45 10.1 Input Termination.................................................................................................................................. 45 10.1.1 NIM Inputs.................................................................................................................................... 45 10.1.2 ECL Inputs .................................................................................................................................... 45 10.2 A24/A32 Slave address width and VME slave base address ................................................................ 46 10.3 JP_SH1 and JP_SH2 ............................................................................................................................. 46 10.4 Shark1 and Shark2 ................................................................................................................................ 46 10.5 J_BREQ and J_BGX............................................................................................................................. 47 Page 3 of 57 SIS Documentation SIS4100 FASTBUS Master 10.6 VME arbiter type JP219....................................................................................................................... 47 10.7 Boot File Selection and Sysreset behaviour J960.................................................................................. 48 11 JTAG........................................................................................................................................................
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