MOS Gate Dielectrics

Prof. Krishna Saraswat

Department of Electrical Engineering Stanford University Stanford, CA 94305 [email protected]

araswat tanford University 1 EE311 / Gate Dielectric

Outline

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 2 EE311 / Gate Dielectric

1 Scaling of MOS Gate Dielectric

ID ∝ Charge x velocity ∝ Cox (VGS - VT) x velocity ∝ Cox (VGS - VT) x velocity

K C " ox thickness

! (Ref: S. Asai, Microelectronics Engg., Sept. 1996)

Gate SiO2 thickness is approaching < 20 Å to improve device performance • How far can we push MOS gate dielectric thickness? • How will we grow such a thin layer uniformly? • How long will such a thin dielectric live under electrical stress? • How can we improve the endurance of the dielectric? araswat tanford University 3 EE311 / Gate Dielectric

Problems in Scaling of Gate Oxide

Polysilicon gate electrode

Dopant Leakage current penetration

gate oxide

Reliability due to Defects and charge injection nonuniformity of film Dielectric breakdown Si substrate

•Below 20 Å problems with SiO2 – Gate leakage => circuit instability, power dissipation – Performance degradation due to tox(electrical) > tox(physical) • Carrier quantization in the channel and depletion in poly-Si gate – Degradation and breakdown – Dopant penetration through gate oxide – Defects araswat tanford University 4 EE311 / Gate Dielectric

2 Leakage Current Contributions

VDD

poly gate IG n+ n+ ISUB IGIDL p-well IJ

Source: Marcyk, Intel Relative contributions of OFF-state leakage (but magnitude of total leakage getting exponentially worse for deeper submicron nodes) 130nm 100nm 65nm

ISUB Subthreshold leakage from source

IGIDL Gate-induced drain leakage (GIDL)

IJ Junction reverse-bias leakage

IG Gate leakage (direct tunneling)

Source: Assenmacher, Infineon (2003) araswat tanford University 5 EE311 / Gate Dielectric

Quantum Mechanical Effect under gate oxide . Band bending under gate oxide creates a quantum well that splits carrier energy band into subbands . The spatial distribution of carriers is modified with the maxima in the semiconductor . This results in additional capacitance

Carrier Concentration - Classical Carrier Concentration - Quantum Mechanical

y Conduction Band g r e n e

n o r t

c Depth Under Gate Oxide e l

E Energy Band Split

CQ : additional capacitance from quantum mechanical effect Cox CQ araswat tanford University 6 EE311 / Gate Dielectric

3 Performance degradation due to

tox(electrical) > tox(physical) reduced Cox 2.00E+20 increase EOT ) m 3 c

/ 2.5 nm gate oxide ( . n o

i 1.50E+20 t a r t QuCalnatsusmic malechanical n e c

n 1.00E+20 o C

n o r

t 5.00E+19

c Quantum mechanical

e Classical l E 0.00E+00 0 1 2 3 4 5 Depth (nm) Ref: T.-Y. Oh PhD thsis, Stanford Univ. 2004 Ref: Buchanan et al., Proc. ECS Vol. PV 96-1, 1996

• The maximum of carrier concentration is located ~ 1nm under the gate oxide • Corresponds > 20% of physical gate oxide thickness of current technology

• Effect of quantization is to increase effective tox and thus reduce Cox araswat tanford University 7 EE311 / Gate Dielectric

Carrier depletion in poly-Si gate.

Gate depletion

Reduced Cox tox(electrical) increased EOT

tox(phy sical)

Gate Substrate Oxide

(Buchanan and Lo, Proc. ECS Vol. PV 96-1, 1996)

. High E - field due to a combination of higher supply voltage and thinner gate oxide causes band bending even in heavily doped poly-Si gate . This causes depletion in poly-Si gate, especially for boron doping

. Effect of depletion is to increase effective tox and thus reduce Cox araswat tanford University 8 EE311 / Gate Dielectric

4 Combined Effects of Depletion and Quantization

Si surface charge C = ε / EOT centroid few Å’s away ox ox from oxide interface EOT = Equivalent Oxide Thickness Poly-Si Gate VG

poly depletion (band Depletion Region CD.R. bending) results from C nonzero conductivity Gate Dielectric G.D. p-well Q.M. Thickness CQ.M. gate charge centroid few Å’s away from Si Substrate oxide interface gate + n poly gate oxide EOTTOT = EOTD.R. + EOTG.D. + EOTQ.M. • Combined effect of depletion and quantization is to

increase effective tox and thus reduce Cox • A reduced Cox implies reduction in gm and thus ID(on) araswat tanford University 9 EE311 / Gate Dielectric

Outline

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 10 EE311 / Gate Dielectric

5 Resistance Heated Furnace

(or H20) Si + O2 = SiO2

Si + 2H2O = SiO2 + 2H2 • Batch processing ⇒ low cost • High thermal mass ⇒ long process times. • Ideal for growing thick oxides. • Multiprocessing for nitrided oxides not easy to do. araswat tanford University 11 EE311 / Gate Dielectric

Lamp Heated Rapid Thermal Oxidation

Control System

Shroud

Quartz Window Gas Wafer out Gas In

Chamber

TemAcousticperature Thermometersensor

• Single wafer processing ⇒ real time measurement and control • Low thermal mass ⇒ short process times. • Ideal for growing ultrathin gate oxides. • Multiprocessing ideal for composite dielectrics, e.g., nitrided oxides.

• Rapid thermal CVD of ultrathin Si3N4 araswat tanford University 12 EE311 / Gate Dielectric

6 Plasma CVD System RF ~

Plasma

Chuck

Primarily used in low temperature applications, e.g., TFTs for displays

araswat tanford University 13 EE311 / Gate Dielectric

Atomic layer CVD (ALCVD)

Gas input 1) ZrCl4(g) Showerhead

2) ZrCl4(ad)

Wafer

3) ZrCl4(ad) + 2H2O (g) →ZrO2 (ad) + 4HCl (g)

Heated Pedestal (>400oC)

4) ZrO2(ad)

•Deposition is done one monolayer at a time: excellent control

•Being investigated for high-k dielectrics like ZrO2, HfO2

araswat tanford University 14 EE311 / Gate Dielectric

7 Microstructure of SiO2 Amorphous SiO

Crystalline quartz 2

Tetrahedra O

O

Crystalline SiO consists of ordered networks of O

2 O

O

O Si

corner-sharing SiO4 tetrahedra In the amorphous O

O Si

O

SiO2, the basic structural unit is the SiO4 O

O Si O

O

O tetrahedron with each Si atom surrounded by four Si O

O

Si O Si

O atoms. The angle of O-Si-O bonds is fixed at O

O Si

O

109.5o. However, the Si-O-Si angle is rather O

O Si O

O

O Si flexible. Each O atom bridges two neighboring O O

Si O Si

SiO4 tetrahedrons. The bond is relatively easy to O

O Si

O O

bend, stretch or rotate. The Si-O-Si bonds are O Si

Si O capable of accommodating large lattice distortion O O araswat tanford University 15 EE311 / Gate Dielectric

MOS Gate Dielectrics

Outline

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 16 EE311 / Gate Dielectric

8 Ideal MOS

Oxide 3.1 eV Si 1.1 eV Si

+ 3.8 eV

+

• The microstructure gives rise to a band structure with a large band gap of about 9 eV

• Large barriers between Si and SiO2

araswat tanford University 17 EE311 / Gate Dielectric

Conduction in Dielectrics: Tunneling

Fowler-Nordheim Tunneling Direct Tunneling

Oxides < 3 nm Oxides > 5 nm !b Vox !b e Vox n+ poly e n+ poly

sub sub

(a) (b) B $ V 3 ' " "B%1 " (1" ox ) 2 ( 2 Eox # J = AE e 2 & b ) ox J = AE ox exp Eox 3 3 q m 8" 2m # 2 m is the mass of electron in vacuum A = B = ox b mox is the average electron mass in the oxide 8"hmox#b 3hq araswat tanford University 18 EE311 / Gate Dielectric

!

9

! !

! Conduction in Dielectrics: Leakage Trap Assisted Tunneling

Traps Traps

• Trap assisted tunneling resulting in leakage at low gate voltage • An increase in traps will cause more leakage • Traps are present in as grown dielectric • Traps can be generated by electrical stress araswat tanford University 19 EE311 / Gate Dielectric

Conduction in Thin Oxides THIN OXIDE Direct tunneling

P.E.

THICK OXIDE FN tunneling

P.E. Ref: Gupta, et al., IEEE Electron Dev. Lett. Dec. 1997

Below ~35 Å direct tunneling causes excessive gate current araswat tanford University 20 EE311 / Gate Dielectric

10 Hot Carrier Generation due to High E-field Channel Source Drain

• The E-field can be very high in the channel, especially near the drain • The free carriers passing through the high-field can gain sufficient energy araswat tanford University 21 EE311 / Gate Dielectric

Hot Electrons and Holes

• At high electric fields the carriers are accelerated to high velocities • These energetic carriers are termed as hot carriers

araswat tanford University 22 EE311 / Gate Dielectric

11 Hot electron injection

Fowler-Nordheim Tunneling Hot electron injection e

e

(a) (b) •Electrons being injected have to •Requires sufficient band be highly energetic to overcome bending for electrons to tunnel the barrier into the conduction band of the •Hot electrons can be produced oxide in drain depletion region •Hot holes behave similarly araswat tanford University 23 EE311 / Gate Dielectric

Hot carrier effects in an MOS transistor

• The free carriers passing through the high-field can gain sufficient energy to cause several hot-carrier effects. • This can cause many serious problems for the device operation,

e.g. change in Vt, gm, leakage, junction breakdown araswat tanford University 24 EE311 / Gate Dielectric

12 Non Volatile Memories

• Carrier injection is also used beneficially for making non volatile memories

• Vt shift due to carrier trapping during program and erase functions araswat tanford University 25 EE311 / Gate Dielectric

Dielectric Degradation Mechanisms

• Degradation during device operation due to high E field causing current injection • Degradation during fabrication due to charging in plasma processing

Electron energy at anode

After DiMaria et al. (IBM) e (1) n(E)

Cathode (3) 0 5 10 e E (eV)

(5) (2) (6) (1) Electron injection h e (2) Energy released by hot electron (3) Anode (3) Bond breaking - trap generation (4) (4) Hot hole generation h (5) Energy released by hot hole - trap generation Oxide (6) Hydrogen release - trap generation

Dielectric damage and breakdown is due to interface trap generation initiated by the energy loss of injected electrons and holes araswat tanford University 26 EE311 / Gate Dielectric

13 Intrinsic Dielectric Breakdown

Damage Damage cluster Cathode

SiO2

Anode

Damage initiation Damage propagation Breakdown

• Damage initiates at anode and cathode interfaces causing degradation. • Eventually it spreads throughout the body of the dielectric causing breakdown. • Degradation can be minimized if damage at the interfaces is prevented

araswat tanford University 27 EE311 / Gate Dielectric

Extrinsic Breakdown

Particle Structural weakness Interface roughness Pinhole

SiO2

• Damage initiates at an extrinsic defect present in the oxide • Eventually it spreads throughout the body of the dielectric causing breakdown. • Degradation is minimized by careful processing to reduce process induced defects araswat tanford University 28 EE311 / Gate Dielectric

14 Methods of testing degradation and breakdown in dielectric films A voltage (or current) stress is applied to a gate capacitor. The current (or voltage) is I v(t) monitored till the device breaksdown. Time

substrate to breakdown (tbd) and total injected charge to breakdown (Qbd) are then determined

Ramped voltage stress Constant current stress Constant voltage stress

Vg Voltage

BV hole electron trapping Vbd trapping Breakdown

Qbd=Jstress x tbd

t Time bd tbd araswat Time tanford University 29 EE311 / Gate Dielectric

Stress Induced leakage Current

Ref: Dumin, et. al., IEEE Trans. Electron Devices. May 1993

traps

• Electrical stress in SiO2 causes leakage to increase at low gate voltages • Electrical stress generates traps • Leakage is caused by traps assisted tunneling araswat tanford University 30 EE311 / Gate Dielectric

15 Breakdown Statistics 100

80 Intrinsic Breakdown

60

40 Breakdown due to defects 20

0 0.1 1.0 10.0 100.0 2 Charge to breakdown Qbd (C/cm )

• Intrinsic breakdown has higher Qbd • Extrinsic breakdown results in early breakdown • A good set of devices should not have early breakdown

araswat tanford University 31 EE311 / Gate Dielectric

Qbd vs. Trap Generation Rate≈ 102 ) 2 101 Tox = 30 - 250 Å

100 T = 20 - 300°C (Coul/cm

bd -2 2

Q Jox = 10 - 1 A/cm 10-1 Ref: Apte et. al., J. Electrochem. Soc, March, 1993 10-2 10-1 100 101 102 103 (Trap Generation Rate)-1 2 dQinj/dVg (Coul/V-cm )

• Qbd and net trap generation track for different oxide thickness, stress current density and temperature

• Higher trap generation rate causes lower Qbd • Dielectric damage and breakdown is due to interface trap generation initiated by the energy loss of injected electrons and holes araswat tanford University 32 EE311 / Gate Dielectric

16 Dependence of tbd on Electric Field

10 ! E < E ! b1 E1 1 2 b 2 E2 4 nm E e - Q bd1 > Q F n+ bd2 p+ n+ Si gate EF e -

p+ SiGe gate p- (90%) (ms)) p- bd p+ Si gate (a) (b) const I log(t const V on n+Si gate 1 9 10 11 12 13 14 Energy diagrams for (a) n+ poly-Si and (b) p+ E (MV/cm) poly-Si gate MOS capacitor on p- substrates.

Ref: Yang, et. al., IEEE Trans. Electron Dev., July 1999 Barrier height is 3.1 eV for n+ gate and 4 eV for p+ gate. Higher barrier height gives larger

oxide electric field and therefore lower Qbd at a fixed current density.

Higher E field in gate oxide ⇒ higher electron energy at the anode ⇒ lower Tbd araswat tanford University 33 EE311 / Gate Dielectric

Effect of Area on tBD

Area A1

Breakdown site

Area A2 Ref: Degreve, IRPS 1997

• Device with larger area has higher probability of containing a breakdown site ⇒ Larger area devices have lower tBD • Measurements made on larger area capacitors need to be correlated to smaller area transistors araswat tanford University 34 EE311 / Gate Dielectric

17 Effect of Electrical Stress Temperature

on Qbd 100

25 C 7 nm SiO B B 2 B B B 10 B B 100 C B B J J J B J J B J 1 J J 200 C

Qbd (C/cm2) H H H H H H H H 0.1 300 C F F F F

0.01 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 Jox (A/cm2)

• Higher stress temperature results in lower Qbd • Important for plasma induced damage araswat Ref: Apte et. al., J. Electrochem. Soc, March, 1993 tanford University 35 EE311 / Gate Dielectric

Substrate vs. Gate Injection Gate THIN OXIDE: Direct tunneling

-Vg P.E.

Si

THICK OXIDE: FN tunneling

Si Gate

P.E. +Vg Ref: M. Depas et al., Electrochem Soc., Vol. PV96-1, p. 352, 1996

.Qbd is lower for gate injection of electrons ⇒ Effect of the strained transition layer .As gate oxide thickness decreases Qbd is not affected much for substrate injection but decreases for gate injection ⇒ Effect of the strained transition layer .For ultrathin oxide direct tunneling dominates resulting in lower energy electrons in

the SiO2. Thus damage is reduced and Qbd increases. araswat tanford University 36 EE311 / Gate Dielectric

18 Transition (Strained) Layer at the Substrate Interface

THICK OXIDE THIN OXIDE

SiO2 Gate

SiO2

Transition layer SiOx Substrate

Transition Layer

• Structural inhomogenity (1-2 monolayers) due to transition from Si to SiO2

• Stress due to volume change during SiO2 formation.

• Strained bonds are easier to break resulting in lower Qbd for gate injection of electrons. • For thinner films the transition layer becomes a significant fraction of the total layer. For increased reliability of deep submicron devices, technology must be developed to reduce the impact of the transition layer araswat tanford University 37 EE311 / Gate Dielectric

Why is there a stress?

During thermal oxidation, +126% volume increase from Si --> SiO2

SiO2 compressive stress

Si

SiO2 O O O O ! ! ! ! Si Si Si Si Si Si Si Si Si higher stress lower stress (less viscous flow) (more viscous flow) araswat tanford University 38 EE311 / Gate Dielectric

19 Correlation Between Stress and Qbd

100 Tbd e 50% wet O2 1000 J= - 300mA/cm2 Vg- Si " 2% wet O2 1000°C,30% O2 Gate ! 100 1000°C,70% O2 Si 10 dry O2 800°C,30% O2 (90%) (sec) bd !’ t 10

Si substrate (90%) (sec) 800°C,70% O2 bd T

1 1 20 40 60 80 100 120 750 800 850 900 950 1000 1050 growth temperature (°C) Tox (Å) Relaxed Si-O-Si bonds Stressed Si-O-Si bonds in the oxide bulk in the transition layer Ref: Yang and Saraswat, IEEE Trans. Electron Dev., April 2000

• Thinner SiO2 films are more susceptible to degradation (for FN tunneling) • Degradation is always more for conditions resulting in higher physical stress

in SiO2. • Higher temperatures, steam oxidation and longer growth times allow stress

relaxation through viscous flow and hence result in SiO2 of better reliability.

araswat tanford University 39 EE311 / Gate Dielectric

Effect of Gate Electrode

10 4 nm Poly-Si gate n+ Si gate

Rough interface Gate oxide p+ SiGe gate (90%) (ms))

Silicon substrate bd p+ Si gate const I log(t const V on n+Si gate 1 9 10 11 12 13 14 E (MV/cm)

• Gate electrode roughness at the oxide/gate interface causing enhanced localized electric field intensity. • Gate electrode workfunction impacts electric field intensity • Higher electric field intensity results in lower reliability

araswat tanford University 40 EE311 / Gate Dielectric

20 Effect of Bulk Electron Trapping Constant Current Stress e e Vg e e e e !Vg

Time 4.0 50 3.5 Dry oxide Silane - 600 oC 3.0 40 Silane-1000oC 2.5 o o TEOS - 1000 C 30 TEOS-1000 C 2.0 1.5 20 1.0 Silane - 1000 oC 0.5 10 Silane-600oC 0.0 Dry oxide -0.5 0 0 10 20 30 40 50 60 70 80 90 100 2.0 2.5 3.0 3.5 4.0 Stress time (sec) Change in |Vg|(V) Ref: Bhat, et. al., IEEE Trans. Electron Devices., April 1996 • Degradation by bulk electron trap generation is observed in deposited oxides used as gate dielectrics in applications such as non volatile memories and TFTs for flat panel displays • It can be minimized by a high temperature anneal araswat tanford University 41 EE311 / Gate Dielectric

MOS Gate Dielectrics

Outline

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 42 EE311 / Gate Dielectric

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