MOS Gate Dielectrics Prof. Krishna Saraswat Department of Electrical Engineering Stanford University Stanford, CA 94305 [email protected] araswat tanford University 1 EE311 / Gate Dielectric Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 2 EE311 / Gate Dielectric 1 Scaling of MOS Gate Dielectric ID ∝ Charge x velocity ∝ Cox (VGS - VT) x velocity ∝ Cox (VGS - VT) x velocity K C " ox thickness ! (Ref: S. Asai, Microelectronics Engg., Sept. 1996) Gate SiO2 thickness is approaching < 20 Å to improve device performance • How far can we push MOS gate dielectric thickness? • How will we grow such a thin layer uniformly? • How long will such a thin dielectric live under electrical stress? • How can we improve the endurance of the dielectric? araswat tanford University 3 EE311 / Gate Dielectric Problems in Scaling of Gate Oxide Polysilicon gate electrode Dopant Leakage current penetration gate oxide Reliability due to Defects and charge injection nonuniformity of film Dielectric breakdown Si substrate •Below 20 Å problems with SiO2 – Gate leakage => circuit instability, power dissipation – Performance degradation due to tox(electrical) > tox(physical) • Carrier quantization in the channel and depletion in poly-Si gate – Degradation and breakdown – Dopant penetration through gate oxide – Defects araswat tanford University 4 EE311 / Gate Dielectric 2 Leakage Current Contributions VDD poly gate IG n+ n+ ISUB IGIDL p-well IJ Source: Marcyk, Intel Relative contributions of OFF-state leakage (but magnitude of total leakage getting exponentially worse for deeper submicron nodes) 130nm 100nm 65nm ISUB Subthreshold leakage from source IGIDL Gate-induced drain leakage (GIDL) IJ Junction reverse-bias leakage IG Gate leakage (direct tunneling) Source: Assenmacher, Infineon (2003) araswat tanford University 5 EE311 / Gate Dielectric Quantum Mechanical Effect under gate oxide . Band bending under gate oxide creates a quantum well that splits carrier energy band into subbands . The spatial distribution of carriers is modified with the maxima in the semiconductor . This results in additional capacitance Carrier Concentration - Classical Carrier Concentration - Quantum Mechanical y Conduction Band g r e n e n o r t c Depth Under Gate Oxide e l E Energy Band Split CQ : additional capacitance from quantum mechanical effect Cox CQ araswat tanford University 6 EE311 / Gate Dielectric 3 Performance degradation due to tox(electrical) > tox(physical) reduced Cox 2.00E+20 increase EOT ) m 3 c / 2.5 nm gate oxide ( . n o i 1.50E+20 t a r t QuCalnatsusmic malechanical n e c n 1.00E+20 o C n o r t 5.00E+19 c Quantum mechanical e Classical l E 0.00E+00 0 1 2 3 4 5 Depth (nm) Ref: T.-Y. Oh PhD thsis, Stanford Univ. 2004 Ref: Buchanan et al., Proc. ECS Vol. PV 96-1, 1996 • The maximum of carrier concentration is located ~ 1nm under the gate oxide • Corresponds > 20% of physical gate oxide thickness of current technology • Effect of quantization is to increase effective tox and thus reduce Cox araswat tanford University 7 EE311 / Gate Dielectric Carrier depletion in poly-Si gate. Gate depletion Reduced Cox tox(electrical) increased EOT tox(phy sical) Gate Substrate Oxide (Buchanan and Lo, Proc. ECS Vol. PV 96-1, 1996) . High E - field due to a combination of higher supply voltage and thinner gate oxide causes band bending even in heavily doped poly-Si gate . This causes depletion in poly-Si gate, especially for boron doping . Effect of depletion is to increase effective tox and thus reduce Cox araswat tanford University 8 EE311 / Gate Dielectric 4 Combined Effects of Depletion and Quantization Si surface charge C = ε / EOT centroid few Å’s away ox ox from oxide interface EOT = Equivalent Oxide Thickness Poly-Si Gate VG poly depletion (band Depletion Region CD.R. bending) results from C nonzero conductivity Gate Dielectric G.D. p-well Q.M. Thickness CQ.M. gate charge centroid few Å’s away from Si Substrate oxide interface gate + n poly gate oxide EOTTOT = EOTD.R. + EOTG.D. + EOTQ.M. • Combined effect of depletion and quantization is to increase effective tox and thus reduce Cox • A reduced Cox implies reduction in gm and thus ID(on) araswat tanford University 9 EE311 / Gate Dielectric Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 10 EE311 / Gate Dielectric 5 Resistance Heated Furnace (or H20) Si + O2 = SiO2 Si + 2H2O = SiO2 + 2H2 • Batch processing ⇒ low cost • High thermal mass ⇒ long process times. • Ideal for growing thick oxides. • Multiprocessing for nitrided oxides not easy to do. araswat tanford University 11 EE311 / Gate Dielectric Lamp Heated Rapid Thermal Oxidation Control System Shroud Quartz Window Gas Wafer out Gas In Chamber TemAcousticperature Thermometersensor • Single wafer processing ⇒ real time measurement and control • Low thermal mass ⇒ short process times. • Ideal for growing ultrathin gate oxides. • Multiprocessing ideal for composite dielectrics, e.g., nitrided oxides. • Rapid thermal CVD of ultrathin Si3N4 araswat tanford University 12 EE311 / Gate Dielectric 6 Plasma CVD System RF ~ Plasma Chuck Primarily used in low temperature applications, e.g., TFTs for displays araswat tanford University 13 EE311 / Gate Dielectric Atomic layer CVD (ALCVD) Gas input 1) ZrCl4(g) Showerhead 2) ZrCl4(ad) Wafer 3) ZrCl4(ad) + 2H2O (g) →ZrO2 (ad) + 4HCl (g) Heated Pedestal (>400oC) 4) ZrO2(ad) •Deposition is done one monolayer at a time: excellent control •Being investigated for high-k dielectrics like ZrO2, HfO2 araswat tanford University 14 EE311 / Gate Dielectric 7 Microstructure of SiO2 Amorphous SiO Crystalline quartz 2 Tetrahedra O O Crystalline SiO consists of ordered networks of O 2 O O O Si corner-sharing SiO4 tetrahedra In the amorphous O O Si O SiO2, the basic structural unit is the SiO4 O O Si O O O tetrahedron with each Si atom surrounded by four Si O O Si O Si O atoms. The angle of O-Si-O bonds is fixed at O O Si O 109.5o. However, the Si-O-Si angle is rather O O Si O O O Si flexible. Each O atom bridges two neighboring O O Si O Si SiO4 tetrahedrons. The bond is relatively easy to O O Si O O bend, stretch or rotate. The Si-O-Si bonds are O Si Si O capable of accommodating large lattice distortion O O araswat tanford University 15 EE311 / Gate Dielectric MOS Gate Dielectrics Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 16 EE311 / Gate Dielectric 8 Ideal MOS Oxide 3.1 eV Si 1.1 eV Si + 3.8 eV + • The microstructure gives rise to a band structure with a large band gap of about 9 eV • Large barriers between Si and SiO2 araswat tanford University 17 EE311 / Gate Dielectric Conduction in Dielectrics: Tunneling Fowler-Nordheim Tunneling Direct Tunneling Oxides < 3 nm Oxides > 5 nm !b Vox !b e Vox n+ poly e n+ poly sub sub (a) (b) B $ V 3 ' " "B%1 " (1" ox ) 2 ( 2 Eox # J = AE e 2 & b ) ox J = AE ox exp Eox 3 3 q m 8" 2m # 2 m is the mass of electron in vacuum A = B = ox b mox is the average electron mass in the oxide 8"hmox#b 3hq araswat tanford University 18 EE311 / Gate Dielectric ! 9 ! ! ! Conduction in Dielectrics: Leakage Trap Assisted Tunneling Traps Traps • Trap assisted tunneling resulting in leakage at low gate voltage • An increase in traps will cause more leakage • Traps are present in as grown dielectric • Traps can be generated by electrical stress araswat tanford University 19 EE311 / Gate Dielectric Conduction in Thin Oxides THIN OXIDE Direct tunneling P.E. THICK OXIDE FN tunneling P.E. Ref: Gupta, et al., IEEE Electron Dev. Lett. Dec. 1997 Below ~35 Å direct tunneling causes excessive gate current araswat tanford University 20 EE311 / Gate Dielectric 10 Hot Carrier Generation due to High E-field Channel Source Drain • The E-field can be very high in the channel, especially near the drain • The free carriers passing through the high-field can gain sufficient energy araswat tanford University 21 EE311 / Gate Dielectric Hot Electrons and Holes • At high electric fields the carriers are accelerated to high velocities • These energetic carriers are termed as hot carriers araswat tanford University 22 EE311 / Gate Dielectric 11 Hot electron injection Fowler-Nordheim Tunneling Hot electron injection e e (a) (b) •Electrons being injected have to •Requires sufficient band be highly energetic to overcome bending for electrons to tunnel the barrier into the conduction band of the •Hot electrons can be produced oxide in drain depletion region •Hot holes behave similarly araswat tanford University 23 EE311 / Gate Dielectric Hot carrier effects in an MOS transistor • The free carriers passing through the high-field can gain sufficient energy to cause several hot-carrier effects. • This can cause many serious problems for the device operation, e.g. change in Vt, gm, leakage, junction breakdown araswat tanford University 24 EE311 / Gate Dielectric 12 Non Volatile Memories • Carrier injection is also used beneficially for making non volatile memories • Vt shift due to carrier trapping during program and erase functions araswat tanford University 25 EE311 / Gate Dielectric Dielectric Degradation Mechanisms • Degradation during device operation due to high E field causing current injection • Degradation during fabrication due to charging in plasma processing Electron energy at anode After DiMaria et al. (IBM) e (1) n(E) Cathode (3) 0 5 10 e E (eV) (5) (2) (6) (1) Electron injection h e (2) Energy released by hot electron (3) Anode (3) Bond breaking - trap generation (4) (4) Hot hole generation h (5) Energy released by hot hole - trap generation Oxide (6) Hydrogen release - trap generation Dielectric damage and breakdown is due to interface trap generation initiated by the energy loss of injected electrons and holes araswat tanford University 26 EE311 / Gate Dielectric 13 Intrinsic Dielectric Breakdown Damage Damage cluster Cathode SiO2 Anode Damage initiation Damage propagation Breakdown • Damage initiates at anode and cathode interfaces causing degradation.