Master Thesis DESIGN of a MULTI-LEVEL DRIVER for MEMRISTORS to BE USED in NEUROMORPHIC APPLICATIONS Amadeo De Gracia Herranz
UNIVERSIDAD POLITECNICA´ DE MADRID ESCUELA TECNICA´ SUPERIOR DE INGENIEROS DE TELECOMUNICACION´
Master Thesis
DESIGN OF A MULTI-LEVEL DRIVER FOR MEMRISTORS TO BE USED IN NEUROMORPHIC APPLICATIONS
Amadeo de Gracia Herranz 2019 Master Thesis
DESIGN OF A MULTI-LEVEL DRIVER FOR MEMRISTORS TO BE USED IN NEUROMORPHIC APPLICATIONS
Author: Amadeo de Gracia Herranz Graduado en Ingenier´ıay Servicios de Telecomunicaci´on
Advisor: Mar´ıaLuisa L´opez Vallejo Catedr´aticade Universidad
Departamento de Ingenier´ıa Electronica´ ESCUELA TECNICA´ SUPERIOR DE INGENIEROS DE TELECOMUNICACION´ UNIVERSIDAD POLITECNICA´ DE MADRID
2019 M´asterUniversitario en Ingenier´ıade Telecomunicaci´on
Title: Design of a multi-level driver for memristors to be used in neuromorphic applications
Author: Amadeo de Gracia Herranz
Advisor: Mar´ıaLuisa L´opez Vallejo
Tribunal:
President: ......
Vocal: ......
Secretary: ......
Substitute: ......
The members of the tribunal agree granting the qualification:
...... de ...... de 2019
Tribunal Secretary
Resumen
La memoria ha sido uno de los puntos principales de estudio desde los inicios de los sistemas electr´onicos. Actualmente las resistencias variables son una de las principales l´ıneasde investigaci´onen este campo. Algunas caracter´ısticascomo su no-volatilidad o su peque˜notama˜nodespiertan el inter´esde los profesionales del sector. El modelado, caracterizaci´ony dise˜node circuitos complementarios a estos dispositivos suponen los mayores retos.
Por otro lado, las redes neuronales forman parte de uno de los temas m´asactuales en el mundo de la tecnolog´ıa. Estas redes no son m´asque un modelo computacional basado en la simulaci´ondel comportamiento de un cerebro biol´ogico. Por el momento la mayor´ıade las neuronas que forman estos cerebros se simulan mediante conjuntos de n´umerosen los ordenadores. Las memorias multi-nivel podr´ıanabrir una ventana a la simulaci´onde estos cerebros a un nivel mas bajo funcionando de una manera m´asr´apida y eficiente.
Bajo todo este contexto, este Trabajo de Fin de Master se centrar´aen el estudio y caracterizaci´onde modelos de memristor as´ıcomo del dise˜node parte de la circuiter´ıa necesaria para su correcta lectura o escritura.
En las primeras p´aginasde este trabajo podremos leer una introducci´onsobre el potencial de las memorias basadas en memristores y se expondr´ancon los objetivos del proyecto. En los primeros cap´ıtulos se realizar´ala comparaci´onde dos modelos de memristor y la elecci´onde uno de ellos para su posterior caracterizaci´ondetallada. Se dedicar´aun cap´ıtuloal dise˜node la circuiter´ıade escritura multi-nivel y otro para la realizaci´onde pruebas sobre ´el.El trabajo terminar´acon una explicaci´onde las conclusiones alcanzadas despu´esde su realizaci´ony se propondr´analgunas l´ıneasde trabajo futuro que servir´ıan para complementar el trabajo.
i ii Abstract
Memory has been one of the main points of study since the beginning of electronic systems. Resistive switching technologies are one of the main lines of research in this field. Some characteristics such as its non-volatility or its small size wake up the interest of professionals in the sector. The modelling, characterisation and design of complementary circuits to these devices represent the greatest challenges.
On the other hand, neural networks are part of one of the most current topics in the world of technology. These networks are nothing more than a computational model based on the simulation of the behaviour of a biological brain. At the moment most of the neurons that make up these brains are simulated by sets of numbers in computers. Multi-level memories could open a window to the simulation of these brains at a lower level working in a faster and more efficient way.
Under all this context, this Master’s Thesis will focus on the study and characterisation of memristor models as well as the design of part of the reading/writing circuitry that would wrap it.
In the first pages of this work we can read an introduction on the potential of resistive memories together with the objectives of the project. In the first chapters the comparison of two models of memristor and the choice of one of them for its subsequent detailed characterisation will be carried out. One chapter will be devoted to the design of the multi-level writing circuitry and another one to carry out tests on it. The work will end with an explanation of the conclusions reached after its realisation and we will propose some lines of future work that would serve to complement the work.
iii iv Agradecimientos
Me gustar´ıaempezar estas l´ıneasagradeciendo a mi tutora, Mar´ıaLuisa L´opez Vallejo, la oportunidad que me ofreci´ode realizar este Trabajo de fin de M´astery todas las horas que me ha dedicado, as´ıcomo la posibilidad de continuar trabajando con ella por m´astiempo. Hace ya m´asde seis a˜nos,septiembre de 2012, cuando entraba por primera vez en esta escuela que se ha convertido en mi segunda casa, aunque muchas veces sea casi la primera. El tiempo que he pasado aqu´ı lo he invertido de muchas maneras, he ido a clase, algunos dir´anque menos de lo que deber´ıa,he hecho ex´amenes,he pasado horas en la biblioteca, pero sobre todo he pasado mucho tiempo entre las cuatro paredes que forman el local A-101.4L donde se encuentra la rama de estudiantes del IEEE. Cursos de electr´onica,clases de programaci´on,concursos de 24 horas sin dormir y muchas sobremesas y tardes de charlas hacen que tenga claro que dentro de ese local he aprendido tanto o m´ascomo en el resto de la escuela. Tendr´ıaa much´ısimagente a la que dar las gracias all´ı dentro y seguramente me olvidar´ıade alguien por miedo a ello creo que no debo escribir sus nombres, muchas gracias a todos. Considero importante agradecer a la escuela la posibilidad que me brind´ode realizar seis meses en la universidad de Link¨oping gracias al programa Erasmus+ y a toda la gente que all´ıme acogi´ocon los brazos abiertos. Cuando en el instituto me dijeron que los amigos de verdad los har´ıaen la universidad una parte de m´ıno se lo terminaba de creer. Unos a˜nosdespu´esde aquello, me he dado cuenta lo sabias que eran aquellas palabras en boca de alguien no mayor que yo ahora. No s´esi ser´apor las cosas que tenemos en com´un,por la cantidad de horas que hemos pasado juntos ya fuese sufriendo o celebrando nuestros aprobados o por alg´unotro motivo que no alcanzo a comprender, pero creo que debo dar las gracias a mis compa˜neros y amigos: Daniel, Paula, Fran y Miguel sin los cuales estos a˜noshabr´ıansido muy diferentes. Pese a todo esto a quien nunca dejar´eatr´ases a mi amiga Elena, con quien siempre puedo contar cuanto necesito descansar de teleco. Por ´ultimo,y casi seguro lo m´asimportante, quiero dar las gracias a mi familia, especialmente a mis padres y a mi hermano. Ellos siempre han aguantado mis malos d´ıas al llegar a casa y me han apoyado independientemente de mi situaci´ono mi decisi´ony a´un siguen haci´endolo.
Gracias a todos!
v vi Contents
Resumen i
Abstract iii
Agradecimientos v
List of Figures ix
List of Tables xi
1 Introduction 1 1.1 Introduction ...... 1 1.2 Framework and motivation ...... 2 1.3 Objectives ...... 2 1.4 Document structure ...... 3
2 Model analysis and selection 5 2.1 Model requirements ...... 5 2.2 Arizona model ...... 5 2.2.1 Import model ...... 6 2.2.2 Different SET values ...... 7 2.2.3 Read test ...... 8 2.3 Messaris model ...... 8 2.3.1 Import model ...... 9 2.3.2 Different SET values ...... 9 2.3.3 Read test ...... 10 2.4 Comparison and decision ...... 11
3 Multi-value storage with the ASU model 13 3.1 Mathematical analysis of multilevel system ...... 13
vii 3.2 Key-point ...... 14 3.3 Cloud of points ...... 16 3.4 Reading the saved values ...... 17 3.5 Conclusions and next step ...... 18
4 Multi-level Write Driver Design 23 4.1 Control signal generator ...... 23 4.1.1 Delay elements ...... 24 4.1.2 Digital counter ...... 25 4.1.3 Using counters to generate the control signals ...... 27 4.2 Pulse generation ...... 28
5 Multi-level Write Driver Characterisation 33 5.1 Parameters ...... 33 5.2 Test with nominal values ...... 33 5.3 Test V23=2.4V ...... 34 5.4 Test V23=2.35V ...... 34 5.5 Comparison between different V23 values...... 35 5.6 Power consumption ...... 35
6 Conclusions and future work 39 6.1 Conclusions ...... 39 6.2 Future Work ...... 39
A Resistance tables 41
B VerilogA to Symbol in Cadence 45
C Ethical, Economic, Social and Environmental impact 53 C.1 Ethical impact ...... 53 C.2 Economic impact ...... 53 C.3 Social impact ...... 54 C.4 Environmental impact ...... 54
D Cost of the system 55
Bibliography 57
viii List of Figures
2.1 Analysis circuit of Arizona model...... 6 2.2 Left: Developers simulation, Right: Our simulation...... 7 2.3 Set of SET from 1.8V to 3.6V step size 0.2V...... 8 2.4 Set of SET from 1.9V to 2.3V step size 0.05V...... 9 2.5 Set of possible read input values -1V to 1V...... 10 2.6 Set of SET from -1V to -3.6V step size 0.1V...... 11 2.7 Set of possible read values from -0.5V to 0.5V with 0.1V step size ...... 12
3.1 Comparison complexity m =5...... 14 3.2 Initial gap 1.7nm saturation...... 15 3.3 Finding new points from saturation...... 16 3.4 Finding new points from saturation2...... 17 3.5 Cloud of points...... 18 3.6 Pulse time vs internal resistance...... 19 3.7 Chain of read and write operations...... 21
4.1 Write driver as a black box...... 23 4.2 Shape of the signal...... 24 4.3 Chain of delay elements...... 24 4.4 Current controlled inverter...... 25 4.5 Pulse generator schematic...... 26 4.6 Chain of T flip-flops...... 26 4.7 T flip-flop based on D flip-flop...... 27 4.8 D flip-flop...... 27 4.9 Control signal generation...... 28 4.10 Simulation of control signal generator...... 29 4.11 Multiplexer based on three transistors...... 30 4.12 Level shifter...... 31
ix 4.13 Write driver...... 31
5.1 Test V23=2.3V V25=-V 25=2.5...... 34 5.2 Test V23=2.4V V25=-V 25=2.5V ...... 35 5.3 Test V23=2.35V V25=-V 25=2.5V ...... 36 5.4 Comparison of all simulated values...... 37
x List of Tables
2.1 Models comparison...... 12
3.1 Pulse time - internal resistance table...... 20
5.1 Power consumption comparison...... 36
A.1 Resistance comparison V23=2.3V...... 42 A.2 Resistance comparison V23=2.4V...... 43 A.3 Resistance comparison V23=2.35V...... 44
xi Chapter 1
Introduction
1.1 Introduction
More than forty-five years ago, in 1971, the electrical engineer and computer scientist Leon Ong Chua envisioned a device which defined a relationship between electric charge and magnetic flux linkage [1]. This device was named memristor and it should be non- linear, passive and should have two terminals. After thirty-seven years of this publication, in 2008, one team at HP Labs were working on the analysis of a thin film of titanium dioxide and they observed the behaviour of the component proposed by Chua. At present there are different research laboratories working on manufacturing memristors based on different types of materials with their associated differences in behaviour. These materials are usually placed as thin layers grown one on top of the other, and some of the materials used are Titanium, Platinum, Tantalum and their oxides [2][3]. We will try to explain in a simple way the behaviour of memristor to better understand where and how it could be used. The electrical resistance of the device depends on all the currents that had flowed through it but it does not depend on the present current and voltage. In other words, when we apply a current through it we change the internal resistance that it has but when we disconnect the current, the device keeps it resistance until we apply current again as a non-volatile property. The memristor keeps memory of its previous state, this is why it was named memristor, it is a ”memory-resistor”. The characterisation of the memristor is another of the research lines which has attracted significant attention in order to provide the foundations to work with this device. Its properties exhibit great potential and therefore a good understanding of the devices seems essential. The different materials, the manufacturing processes and the non-linear nature of the device make defining models that fit all of them a difficult task and that is why so many groups work on it. When we think about a changeable non-volatile property we usually think of memory. If we are able to write this device by applying a controlled current and after that we are able to read the saved value through the non-volatile property we will have a really good memory because it does not need anything to keep its value saved. It could offer a new technology which would share market with others like Flash or EPROM memories trying to collaborate in the fight against the well-known memory wall problem.
1 CHAPTER 1. INTRODUCTION
Memristors can be used as a multi-level memory also. The number of different levels that you can save is theoretically infinite, therefore the real limitation is how can you write and read the saved value. It seems difficult to be able to control the current in a sufficiently precise way to write any value that we want, and the same for the reading operation, so probably we will need to define steps. There is another research line associated to this problem derived from the requirement of being able to write and read from the device. There are many research groups trying to develop drivers to do that work in the best possible way. Both non-volatile memory and multi-level memory are really good properties for this device separately but if we think about both at the same time we could have a non-volatile- multi-level memory. That could be especially powerful and this is the reason why all the work of this Master Thesis will be in the multi-level part because the non-volatile part is intrinsic to the device. Neural networks are a hot topic at the moment and there are many people working and researching on it. Neuromorphic computing is a concept that tries to mimic the behaviour of the nervous system starting from the neuronal part using analog and digital circuits. The use of memristors in this field as multi-level memories has a great potential, becaus they can be both used to store the weights in the synapses and also to perform in-memory computing.
1.2 Framework and motivation
This project has been developed at the Integrated Systems Laboratory (LSI) of the Department of Electronics Engineering of the Technical University of Madrid. This research group has been working on a second stage of the project TOLERA, it is named TOLERA2. The main point of both stages of the project had been the study of variability and tolerance to PVT-variations and radiation in nanometric technologies. In the second stage of the project they propose the possibility of exploring the potential of emerging devices as memristors by applying their experience in working with device models. This Master Thesis is included in this last stage related to the study of memristors and their applications. The motivation of the project could be divided in two, the personal motivation of this project and the general motivation of this project. In the personal field I would like to find a topic for the Master Thesis in an emerging field with good expectations of the future. On the other hand the memory is one of the most important issues related with electronic systems. The memory wall is a well-known problem where there are a lot of people working on and that applies too to the neural networks and neuromorphic computing. The future of big data science is tied to the successful development on performance and power efficient neural networks. And memristive memory seems to be the key to reach such success.
1.3 Objectives
The main goal of this Master Thesis is to contribute to the use of memristors as multi- level memory cells in the context of neuromorphic computing. For this purpose it will
2 CHAPTER 1. INTRODUCTION be necessary first to carry out the characterisation of different memristor models and the comparison between them always considering their most significant properties when used as a multi-level memory device. Next, one model will be selected as the best candidate for our goals and the design of a write driver for such device with at least 16 different levels will be the following of the objective. Finally a last objective of this project will be the evaluation of the designed driver taking into account the power consumption. Although the manufacturing of the device is not considered as an objective, it must be taken into account at all times if the decision made during the design would make it feasible in the future. A long-term objective of this project is the use of memristors in neuromorphic applications as a multi-level memory devices.
1.4 Document structure
The document has been divided into chapters, they are listed below.
1. Chapter 1. We present here the motivation of the project, the objectives and the ecosystem where we work.
2. Chapter 2. We expose a couple of models developed by different research groups and we test them in order to select one.
3. Chapter 3. After making a decision we will test the selected model and characterise it in detail.
4. Chapter 4. In this part we will develop a write circuit according with the parameters that we have gotten in the previous chapter.
5. Chapter 5. After developing a writing driver we will try to test it and check if it works as expected.
6. Chapter 6. In the final chapter we will analyse if we have fulfilled the proposed objectives and we will comment some future lines of work related to this project.
3 CHAPTER 1. INTRODUCTION
4 Chapter 2
Model analysis and selection
When dealing with immature and highly non-linear devices, as is the case of memristors, the selection of a good model for their simulation plays a key role. This is the reason why in this chapter we explain the process of model selection that we have followed and the final decision we made. At the beginning we present the requirements and the behaviour that we are looking for. After that we will show the two models that we have studied and the first test that we have used to analyse them in depth. To finish the chapter we will compare them and explain our decision on which one we will continue working with.
2.1 Model requirements
In this section we explain the requirements and other properties that we should take care of in order to select the model that we will use.
1. Different resistance levels. We need to find a good number of distinguishable levels of resistance. The number of levels is not fixed but should be at least eight which means three bits memory.
2. Invariant voltage range. It is important to have a voltage range at the memristor’s terminals where the resistance does not change in order to use that in the read operation.
3. Response time. This part is not really critical but we should remember that a response time should be as small as possible. Therefore, an additional goal is the minimisation of the response time.
2.2 Arizona model
In this section we introduce the first model that we have analysed. It has been developed by Pai-Yu Chen and Shimeng Yu in Arizona State University [4] which is published in the article [5]. They present a compact model for metal-oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The model parameters and the device variations are calibrated from the experimental data of IMEC
5 CHAPTER 2. MODEL ANALYSIS AND SELECTION
Figure 2.1: Analysis circuit of Arizona model.
HfObased RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, they demonstrate the model’s applications on the programming scheme design of the 1-transistor-1-resistor array. This is one of the most widely used models by the research community.
2.2.1 Import model
In order to start working with the model, it is necessary to analyse the VerilogA model that they have developed and try to remake the same validation experiment as they propose with our own tools. It is not straight-forward to integrate a new model in Cadence. Thus, we have done an easy guide to show how to create a component from a VerilogA file and how to add it to a Cadence Library which can be found in appendix B. As we can see in the example [4], we have used a circuit based on a memristor and a CMOS transistor, which constitutes the conventional 1T1R RRAM cell. When we analysed it we have seen that the way to read the internal resistance of the component is by reading an internal variable, so we have done the same. It is important to note that in the proposed model the internal variable is shown as a voltage (V) but we should read it as a resistance (Ω). The proposed simulation example is based on carrying out a SET→RESET transition in pulse programming mode. The SET is made at 2V in BL point and the RESET is made at 1.9V in SL. We propose to use only the point BL and keep SL connected to ground therefore our RESET will be with -1.9V in BL. Since our transistor comes from a different technology it is possible that we will get a different SET or RESET speed. It is important to remember that the speed at that moment is not as important as the resistance value that we get. In the Figure 2.2 it is possible to see the simulation proposed by the developers of the model and ours. We have used only one voltage source between BL and GND and we have connected SL to GND. Their simulation and ours are really similar therefore our adaptation of the model can be considered valid.
6 CHAPTER 2. MODEL ANALYSIS AND SELECTION
Figure 2.2: Left: Developers simulation, Right: Our simulation.
2.2.2 Different SET values
As we have seen before one of the most important ideas of this work is to be able to change between different values of resistance. We have decided to start trying different SET values not only 2V as we have in the example. Our idea was that if we were able to apply different voltages we would get different resistance points. Before we start we need to define some parameters and fix them. We decided to fix the initial resistance, the time of rise and fall pulses and the pulse time of the SET pulse with the same values as the example. The Figure 2.3 shows the simulation with a voltage set from 1.8V to 3.6V and a step size of 0.2V. The initial gap is 1.367nm as in the example. After this simulation we can see that 1.8V is not enough to SET a value of resistance and after 2.4V all the voltages collapse at the same point 9.98KΩ. Between those values we can reach three different resistance values. We have done that simulation with 0.2V of step size. It means that it is not possible to get more values for the range changing the input voltage. Maybe it is possible to get different values in the range if we change the voltage input with a step size of 0.05V but that is not realistic because it is near to impossible to be able to swap between those values in the real world. Despite this we have performed a simulation with values between 1.9V and 2.3V with 0.05 of step size to analyse how sensitive a small variation of voltage would be. The difference between 1.9V and 1.95V is really big. It means that we will need to use accurate voltage references if we work in that range. It is important to remember that the selected value of initial gap distance is 1.367nm and that resistance results may change if we start in a different point.
7 CHAPTER 2. MODEL ANALYSIS AND SELECTION
1,8 4 2 2,2 2,4 3 2,6 2,8 2 3 3,2 3,4 BL (V) BL 1 3,6
0
0 10n 20n 1M )
100k Rout ( Rout
10k 0 5n 10n 15n 20n 25n time (s)
Figure 2.3: Set of SET from 1.8V to 3.6V step size 0.2V.
2.2.3 Read test
The target of that part is to be able to find a range of voltages that we could apply in BL without changing the resistance of the component. The read voltage proposed in the model [5] is 0.1V but we have tested values up to ±1V as shown in Figure 2.5. We have SET a value before applying the read pulses. As we can see all the values in the proposed range do not change the stored value. It means that all values in the chosen range are suitable to be used as read voltage.
2.3 Messaris model
In this section we will introduce the second model that we have analysed. It has been developed by two research groups which come from the University of Southampton and the Aristotle University of Thessaloniki [6] and it is published in the article [7]. They present a model where device current-voltage characteristics and resistive switching rate are expressed as a function of bias voltage and initial resistive state. The model versatility is a validated for both filamentary valence change memory and non-filamentary technologies. The proposed model embodies a window function which features a simple mathematical form. Its Verilog-A implementation captures the ReRAM memory effect making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.
8 CHAPTER 2. MODEL ANALYSIS AND SELECTION
1,9 2,5 1,95 2 2,0 2,05 2,1 1,5 2,15 1,0 2,2 2,25 BL (V) BL 0,5 2,3
0,0
0 5n 10n 15n 20n 25n 1M
800k )
600k
400k Rout ( Rout 200k
0
0 5n 10n 15n 20n 25n time (s)
Figure 2.4: Set of SET from 1.9V to 2.3V step size 0.05V.
2.3.1 Import model
As we have done with the other model 2.2 before starting working with the model we need to fit it in our own tools. There are two different models in [6] one named numerical and another one named analytical as we can read in [7] it is possible to get the same results with both of them. All the simulations that we have done with this model have been done with the analytical option. In this model we have not an example as we had in the previous model 2.2. We have based our simulations in the information available on [7]. The proposed model has four parameter sets in order to fit four different devices, two of them are developed by themselves and the other two sets fit devices developed by other companies. We have selected one of those developed by them, the one with the greatest range of resistance. The circuit is the same as the one we have used before, there is a memristor and a CMOS transistor placed as a 1T1R cell, as shown in Figure 2.1. It is important to note again that the resistance is shown as voltage (V) but we should read it as a resistance (Ω).
2.3.2 Different SET values
In order to find a set of different values when we apply different voltages we have done a similar simulation as the one in 2.2. In this case we have used the default parameters and a pulse time around 1ms because this is the proposed time in [7]. The voltage starts in
9 CHAPTER 2. MODEL ANALYSIS AND SELECTION
-1 -0,8 2,0 -0,6 -0,4 1,5 -0,2 0 1,0 0,2 0,5 0,4 0,6 0,8 BL (V) BL 0,0 1 -0,5 -1,0
0 20n 40n 60n 80n 100n 120n 140n 160n
1,5M
) 1,0M
500,0k Rout ( Rout
0,0
0 20n 40n 60n 80n 100n 120n 140n 160n time (s)
Figure 2.5: Set of possible read input values -1V to 1V.
-1V and it moves to -3.6V with a 0.1V of step size. It is possible to properly distinguish around 16 values, but after -2.5V all values collapse at the same. On the other hand all the values are approximately equily distributed in the range.
2.3.3 Read test
As we have seen before the idea of this part is to search the voltage range that we can use to read the stored resistance value. We should find a voltage range where the internal resistance is not disturbed. Before we apply the voltage range we have done a SET operation in order to write a previous resistance value. The read voltage set applied in this test vary in ±0.5V as we can see in the next Figure 2.7. In Figure 2.7 it is possible to see that the internal resistance changes when we apply the voltages in the proposed range. The variation is really small but it is not negligible because if we use the read operation a significant number of times we can change the internal resistance significantly. It is possible to solve this problem if we re-write after each read but it would take too much time and power.
10 CHAPTER 2. MODEL ANALYSIS AND SELECTION
-3,6 -3,5 0 -3,4 -3,3 -1 -3,2 -3,1 -3 -2 -2,9
BL (V) BL -2,8 -2,7 -3 -2,6 -2,5 -4 -2,4 -2,3 0,0 500,0µ 1,0m 1,5m 2,0m 2,5m 3,0m -2,2 -2,1 -2 15,0k -1,9 -1,8
) 10,0k -1,7
-1,6 -1,5 5,0k -1,4 -1,3 Rout ( Rout -1,2 0,0 -1,1 -1 0,0 500,0µ 1,0m 1,5m 2,0m 2,5m 3,0m time (s)
Figure 2.6: Set of SET from -1V to -3.6V step size 0.1V.
2.4 Comparison and decision
After the presentation of the models and the experiments carried out, we will compare them taking into account the requirements written before. Table 2.1 collects the key parameters that will be considered in this comparative study: resistance levels, invariant range and response time. We can see in the Table that when working with the Messaris model we can find several resistance points by applying different voltages. For the Arizona model it is not easy to find a significant number of different resistance levels if we only change the voltage, but we have seen that we could try to modify the pulse length and cut the curves at a previously selected resistance point. We did not find an invariant range when reading in the Messaris model, but we have a really good one in Arizona’s model. We said that the response time was not critical but it is notably better in one of the studied models. For all these reasons we have selected the Arizona model to continue our work on multi-level cells based on memristors for neuromorphic computing.
11 CHAPTER 2. MODEL ANALYSIS AND SELECTION
-0,5 -0,4 -0,3 0,5 -0,2 -0,1 0,0 0 0,1 -0,5 0,2 0,3 -1,0 0,4 BL (V) BL 0,5 -1,5
-2,0
18k 0,0 500,0µ 1,0m 1,5m 2,0m 2,5m 3,0m 16k 14k 12k ) 10k
Rout ( Rout 8k
6k 0,0 500,0µ 1,0m 1,5m 2,0m 2,5m 3,0m time (s)
Figure 2.7: Set of possible read values from -0.5V to 0.5V with 0.1V step size
Table 2.1: Models comparison.
Arizona Messaris Resistance levels Not possible with different Easy to find with different voltage values but should be voltages, equidistributed. possible with a soft curve and Small work range. time variation. Large work range. Invariant range Without problem in the range We have not found any range, of ±1V. there could be a range in <0.1V. A write operation should be used after each read operation in order to keep the saved value. Response time Tens of nanoseconds One-two microseconds
12 Chapter 3
Multi-value storage with the ASU model
In this chapter we study the ASU model more in depth in order to understand its behaviour better and look for a way to write and read from it. We will especially focus on using the memristor as a multi-valued storage element. We start the chapter with a little mathematical analysis about the path to change the value that we consider important to understand each of the following steps. After this analysis we will define the key-point, necessary for reading/writing a value and how we can reach it and work from there to access each of the values saved in the device. We finish the chapter with some ideas about what is the procedure that we will need to use this device in the way that we propose.
3.1 Mathematical analysis of multilevel system
As we have explained in Chapter 1 the internal resistance value of the memristor is important when we apply any voltage on it. It means that the voltage that we need to apply to write a value depends on the current flowing through the device. When we increase the number of different values that we can save on the device we increase the number of combinations between them. We have to remember that incrementing the number of values increases the memory too so it is a desirable point. m The number of different combinations of m elements taken n by n is known as n . We have to take care because we need to know the way to write valueX when the valueY is saved but we need to do the opposite also. The number of paths that we need if we have m possible values to be saved is: ! m m! 2 = 2 = m(m − 1) = m2 − m (3.1) 2 2!(m − 2)!
We think that this behaviour could be improved if we add a key-point, the key-point will be a midpoint where we go every time that we change the state. Now we do not need to know all the combinations we only need to know all the ways to go from each value to the key-point and from the key-point to each value. It means that the complexity of the problem is 2m where m is again the number of possible values to save. It is easy to
13 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
Figure 3.1: Comparison complexity m = 5. see that the only case where the first solution is better than the second one is when we have two possible values to save. In the next figure we can see one example with m = 5. Without key-point 20 transitions are needed but with it only 10.
3.2 Key-point
In order to find the key-point we will characterise the model behaviour against different pulsed voltages. It will consist in explore the behaviours when we change the pulse voltage and the length of it. We have fixed the voltage in the gate of the transistor to 1.1V because that is the nominal voltage of it. We have analysed the model for every initial gap point in the range (from 1nm to 1.7nm). Based on Figure 2.3 we search a voltage to collapse all the values in one. Our proposal is that the critical value will be the highest one therefore we find the voltage that collapses that and after that we check if all the other values collapse at the same point too. We have chosen a long pulse time to see the relation of this with the voltage. We expect that a higher voltage needs a shorter time to change the state of the device, if the voltage is higher the current flowing through it is higher too and the state should change faster. Figure 3.2 shows the behaviour of the ASU device when different voltages are applied to its terminals. As we can see, we need at least 2.4V to be able to collapse the value. With 2.4V we need a pulse of 6ns but with 2.5V only little more than 1ns is needed. We have checked if all the other values collapse as we thought and we observe that our proposal was correct and all the values collapse in the same resistance point. It is important to note that the worst case in terms of voltage needed is also the worst case in terms of pulse time needed. Now we have reached a possible key-point and the way to go from anywhere to it. The next step is to be able to reach different points from there in order to have a multilevel device. We have selected an initial gap of 1.367nm and a first pulse of 2.5V and 2ns to fix the study point from now. We find the set of levels applying voltages from -1.8V to -3V with a step size of 0.1V. As we can see in Figure 3.3 we do not have a set of available values for multilevel but we have found a couple of things that we have to analyse. First of all
14 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
1,8 1,9 2 3,0 2,1 2,5 2,2 2,0 2,3 1,5 2,4 1,0 2,5
BL (V) BL 0,5 2,6 0,0 2,7 2,8 1,2 0,0 10,0n 20,0n 30,0n 40,0n 50,0n 2,9 3 1,0 0,8 0,6 0,4
WL (V) WL 0,2 0,0 0,0 10,0n 20,0n 30,0n 40,0n 50,0n 3M )
2M 1M Rout ( Rout 0 0,0 10,0n 20,0n 30,0n 40,0n 50,0n time (s)
Figure 3.2: Initial gap 1.7nm saturation.
we got a new saturation point, that time with the highest internal resistance where we can go from the other saturation point with a pulse of 2.4V in less than 2ns. The other thing that we note is that we have a couple of soft curves in -2.3V and -2.2V. If we control the time of the applied pulse we could cut the curve in different points and get a set of distinguishable values. With the pulse in -2.3V we have a resistance range from 2.7MΩ to 3.24MΩ, 540KΩ to work. As we said before at that point we have two different paths to follow, we decided to explore the new saturation point. As we did we selected the initial gap (1.367nm) a first pulse of 2.5V and 2ns and a second one of -2.4V and 2ns too. That setup gives us the saturation point from which we applied a set of different pulsed voltages in order to find different levels or a soft curve to compare it with the other. We can see in Figure 3.4 that we have not multilevel points but we have a soft curve with the pulse of 2.3V. It is important to note that there are a really big different between the curves derived from 2.2V or 2.4V and the with the one that we selected. It means that means that a small variation could make us switch to a different curve. We could get a good number of values between 3.35MΩ and 2.3MΩ if we cut the pulse from 1ns or 2ns to 35ns. This new range is almost twice the range obtained from the first saturation point. Finally we selected as a key-point the saturation point after the second pulse. That point gives us an internal resistance of 3.35MΩ. We reach this point from any other point applying a sequence of two pulses, the first one has 2.5V of amplitude and 2ns of duration
15 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
3 -3 -2,9 2 -2,8 -2,7 1 -2,6 0 -2,5 -2,4 -1 -2,3 BL (V) BL -2,2 -2 -2,1 -2 -3 -1,9 -1,8 0,0 10,0n 20,0n 30,0n 40,0n 50,0n
3M )
2M
Rout ( Rout 1M
0
0,0 10,0n 20,0n 30,0n 40,0n 50,0n time (s)
Figure 3.3: Finding new points from saturation. and the second one -2.4V and 2ns. It is important to note that the amplitude and the duration are strongly related and if we increase the module of the amplitude we could decrease the duration.
3.3 Cloud of points
In this section we explain how we cut the soft curve and how we get the cloud of points that represents the multilevel memory. We apply from the initial point the two necessary pulses needed to reach the key-point. After seting up the memristor at the key-point we apply a pulse of 2.3V with different duration time from 1ns to 40ns with a step of 1ns. As we can see in Figure 3.5 we have cut the curve and we have obtained a good number of values. We have neglected the last values and we plot the internal resistance as a function of the pulse time in the next Figure 3.6 where we have added the trend line in order to compare it with a straight line. In Table 3.1 we can find the resistance values that we get and the difference between any of them and the previous one. We have obtained more than 30 achievable values with more than 9KΩ between them. We can see that the difference is increasing with the pulse time. It is not the same to have a difference of 1ns between 5ns and 6ns than between 20ns and 21ns. If we want to develop a system with, for example, eight values they will
16 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
1,8 1,9 2 3 2,1 2,2 2 2,3 2,4 1 2,5 2,6 0 2,7
BL (V) BL 2,8 -1 2,9 3 -2 -3 0,0 10,0n 20,0n 30,0n 40,0n 50,0n 60,0n 70,0n 80,0n
3M )
2M
Rout ( Rout 1M
0
0,0 10,0n 20,0n 30,0n 40,0n 50,0n 60,0n 70,0n 80,0n time (s)
Figure 3.4: Finding new points from saturation2. not be separated 4ns each, they probably will be separated more than this in the shortest pulses and less in the longest ones. As a little conclusion of this section we want to note that we have gotten a set of values (more than 30) among which we can choose according to our needs. If we need a system with 8 or 16 levels it will be more robust than if we want to use all the available values. At this point, the effects of variability will significantly affect the availability of a set of robust levels.
3.4 Reading the saved values
As we showed in section 2.2 in the Read test part we have a good range of voltages that we can use to read from the device. They do not modify the internal resistance when they are applied. We do not know how much time the reading circuit will need to read the internal value, so we have decided an order of magnitude similar to the writing of 20ns. We have developed a little tool in Python to be able to simulate any chain of write and read operations. The idea of this tool is to simulate some examples of behaviour by applying to the device successive operations with which to identify if its internal resistance varies in the expected way. The circuit is always the same but the input file changes for each stimulus that we want to simulate that is the reason to develop this simple tool to be able to generate the simulation files on a easy way.
17 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
3 2 1 0 -1 BL(V) -2 -3 0 20n 40n 60n 80n 100n 3M 2M 1M )
0 0 20n 40n 60n 80n 100n
Rout ( Rout 3,25M
3,00M
2,75M
2,50M 0 20n 40n 60n 80n 100n time (s)
Figure 3.5: Cloud of points.
We have added an example of the chained simulations. We have three write-read sequences. Shaded in a blue circle we can see how in each writing process we move to the key-point. After each of that a green circle show us the writing pulse which change according to the value that we want to save. We have added a couple reading pulse after each writing sequence to simulate better a read write process they are shaded in red. As we said before the duration of the reading pulse is 20ns but it could be bigger or smaller since this pulse does not affect the resistance of the device.
3.5 Conclusions and next step
As a conclusion of this chapter we can say that we got what we were looking for. We have the way to change the internal resistance of the device in a good range of values. The values are separated between them and can be reached in a simple way. At this point we have two possible ways to continue. On the one hand we know the way to write in the device, we need to apply a controlled pulse chain, but we do not know how to generate the chain of pulses. On the other hand we know that the saved value is not affected by pulses in a range but we do not know how we can read the value. We know the behaviour of the device but we do not know the electronic systems needed to read and write on it. We have decided to continue studying the write circuit and leave the read part as future work.
18 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
Rout 3,4M Fit Line
3,3M
3,2M
) 3,1M
Rout ( Rout 3,0M
2,9M
2,8M
0 5 10 15 20 25 30 PulseTime (ns)
Figure 3.6: Pulse time vs internal resistance.
19 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
Table 3.1: Pulse time - internal resistance table.
time (ns) resistance (MΩ diff (KΩ) 0 3.3546 - 1 3.3473 7.26 2 3.3386 8.73 3 3.3296 9.01 4 3.3203 9.29 5 3.3107 9.57 6 3.3008 9.89 7 3.2906 10.22 8 3.2800 10.58 9 3.2691 10.95 10 3.2577 11.37 11 3.2459 11.82 12 3.2336 12.3 13 3.2207 12.82 14 3.2074 13.39 15 3.1933 14.02 16 3.1786 14.71 17 3.1632 15.47 18 3.1468 16.31 19 3.1296 17.26 20 3.1113 18.32 21 3.0917 19.54 22 3.0708 20.91 23 3.0483 22.51 24 3.0239 24.38 25 2.9973 26.59 26 2.9681 29.25 27 2.9356 32.53 28 2.8989 36.64 29 2.8569 41.97 30 2.8078 49.16 31 2.7484 59.43 32 2.6709 77.45 33 2.5701 100.85 34 2.4047 165.37 35 1.9247 480.02 36 0.1400 1784.66
20 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
Figure 3.7: Chain of read and write operations.
21 CHAPTER 3. MULTI-VALUE STORAGE WITH THE ASU MODEL
22 Chapter 4
Multi-level Write Driver Design
In this chapter we present our write driver and we design the different circuits that form it. We have divided the chapter into two points, the first one is devoted to explain how we generate the control signals for the pulses in a synchronised way. The second part will explain the generation of the feeding pulse for the memristor using the control signals generated previously and merge them. If we understand our driver circuit as a black box we will have two input signals, the enable or trigger signal and the data that we want to save in the memory as a parallel array of bits sometimes called A. The output signal should be the chain of pulses necessary to make a correct writing on the device as we saw in Chapter 3. It is important to keep in mind the shape of the signal that our pulse should have. We show that in Figure 4.2. The time between the pulses could be less or even zero since it will not affect the behaviour of the memristor. We consider important to define the control signals S0, S1 and S2 that will be used to generate the three pulses that form the signal we want.
4.1 Control signal generator
In this section we study different ways to generate the control signals and select one of them. We need to generate and synchronise three different control signals. The length of the first two of them will be fixed and the last one should be configurable from 1 to 30 nanoseconds with a step of 1ns as we saw in Table 3.1. If we add all of that times we calculate the time of a write cycle and we get that it is less than 40ns if the time of each pulse in the setup part is less than 5ns. We have studied two different ways to generate the configurable pulse. The first of them is based on the propagation time of a chain of different delay elements and the second one is based on the use of a digital counter.
Figure 4.1: Write driver as a black box.
23 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.2: Shape of the signal.
Figure 4.3: Chain of delay elements.
4.1.1 Delay elements
The proposal of the chain of delay elements is based on the idea that every device has a propagation time. If we concatenate an adequate number of delay elements we could obtain the different necessary times from the chain. We decided to use inverters as the first example of delay element because they are the easiest structures with which we can work. As we show in the scheme of Figure 4.3 we would have our control signals that manage the initial pulse in the chain and the selection of the time signal. With the minimum size on each transistor (W=120n and L=40n) we get a propagation time little over 40ps per inverter. We decide to increase the length of them in order to make the associated capacity bigger and increase this time, because we need delay times in the order of nanoseconds. Despite increasing the length up to 10 times the propagation time was still too small for our problem and we would need a chain of hundreds of devices to achieve the proposed times. We decided to add a pair of additional transistors in each inverter in order to control the
24 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.4: Current controlled inverter. supply current (current starving). We apply a voltage slightly deviated from the optimal point to obtain a lower current. We show this idea in Figure 4.4. We simulate some examples with different deviated values up to 15%. The times that we obtained were not very different from the ones we had without these additional transistors. With this procedure the signal was deformed which could be fixed with a fast buffer at the end of the chain if it was needed. It is important to note that we need to have a bank of voltage references to bring about this idea and the corresponding wiring. The cost of that is really high if we think in electronic resources.
After testing the two previous ideas we conclude that the simplicity of an inverter is not enough to get the times that we were looking for. We decided to find new designs and we studied some of them based on one paper that analyses different delay elements [8]. After an in depth study of them we note that they were not able to provide a significantly larger delay because they were actually similar to the delay elements previously studied. Thus, we decided not to use them and we explore a new way to generate the configurable pulse.
4.1.2 Digital counter
After we set aside the delay elements we decided to study the possibility of designing the configurable pulse generator based on a digital counter. This idea is based on the fact that the precision is not in the order of the picoseconds and therefore a bigger clock next to a digital counter could be a good solution. This line forces us to have a clock signal as an additional input in our black box Figure 4.1. We do not consider that adding the clock is a real problem since in most electronic systems there is one or several of these to work in a synchronised way. As we said we need a configurable pulse nanosecond to nanosecond. We have assumed that the frequency of the clock is 500MHz, we have selected that to simplify the development of each part and be able to test it. With this clock frequency there is a big
25 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.5: Pulse generator schematic.
Figure 4.6: Chain of T flip-flops. correlation between the data value that we want to save and the length of the configurable pulse. The length associated with a value of A = X is Xns. If the clock frequency were an integer multiple of 500MHz we could add a clock divider with which we can obtain the 500MHz with which we propose to work. If it were not possible to add this clock divider it would be necessary to change the system in such a way that there would not be such a simple correlation between the input data and the value of the configurable pulse.
We are going to start from the most external part of the architecture and we will go digging on it. The main parts of our device are a counter and a comparator. The way to generate the configurable pulse is to keep the device counting until we reach the selected number that corresponds with a time. We show the schematic of that in Figure 4.5. While the enable signal is not active the counter is being continuously reset. When the enable signal goes to an active value the counter starts to count until it reaches the value A. The counter has been developed as a chain of T flip-flops Figure 4.6 where we have removed the inverted output. The output of each flip-flop gives us a different bit of the output. The number of flip-flops needed depends on the maximum value that we want to have. Our chain has five flip-flops because we only need to count until 30.
26 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.7: T flip-flop based on D flip-flop.
Figure 4.8: D flip-flop.
The T flip-flop is based on a D flip-flop with the addition of an xor gate Figure 4.7. One of the inputs of the gate is the T signal while the other is the feedback of the output D flip-flop. The behaviour of a T flip-flop is easy to understand when it detects a rising clock edge it will keep the output if the input is 0 and it will change the output if the input is 1. Our design of D flip-flop is based on section 7.3.4 of the book [9] that we show in Figure 4.8. With this design we could both obtain the configurable pulse control signal as well as the pulses corresponding to the set up.
4.1.3 Using counters to generate the control signals
As we have seen before, it is possible to generate all the control based on digital counters. In the design that we can see in Figure 4.9 we note that we concatenate three modules to generate the three different signals. That is our way to synchronise all of them to generate one after the other. We use the output signal from the comparator as the input in the next stage. The input that represents the time of each of the two first pulses T 0 and T 1 will be fixed in values that correspond to times between 2ns and 5ns as we see in Chapter 3 while the signal A corresponds to the value that we want to write and save. In the Figure 4.10 we have an example of the behaviour of the generator with T 0 = T 1 = 2 and A = 18. When the enable signal is triggered the system generates the three control signals synchronised with the length that we define.
27 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.9: Control signal generation.
4.2 Pulse generation
As we showed in Chapter 3 the pulse that we need to get is a chain of three different voltages, the first one 2.5V the second one -2.5V and a third one 2.3V. Our idea is to have a multiplexer to generate the desired signal at its output while it is controlled by the signals of the previous section. It is important that the multiplexer supplies the necessary current to the memristor therefore when we simulate that part we have done it with a memristor placed at the output. The multiplexer is based on a three pass transistors where the control signals are connected to their gate in order to cut them. The fact of working with these three voltage levels plus another one required to make a reference at 0V is not trivial. In digital electronics, when we work with only two voltage levels (high and low) it does not really matter where they are because there are only two. When we are working with different low levels (0V and -2.5V) and different high levels (2.3V ans 2.5V) the connection of the body of each transistor is really important and it is not as easy as connecting all the P transistors to the highest level and all the N transistor to the lowest level. We need to remember that in the previous section we were working with
28 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
1,1
clk(V) 0,0 0 10n 20n 30n 40n 50n 60n 70n 80n 1,1
0,0 enable(V) 0 10n 20n 30n 40n 50n 60n 70n 80n 1,8
S0 (V) S0 0,0
0 10n 20n 30n 40n 50n 60n 70n 80n 1,8
S1 (V) S1 0,0
0 10n 20n 30n 40n 50n 60n 70n 80n 1,8
S2 (V) S2 0,0
0 10n 20n 30n 40n 50n 60n 70n 80n time (s)
Figure 4.10: Simulation of control signal generator. conventional digital levels like 0V and 1.8V to generate the control signals. When it comes to thinking about manufacturing it is important to keep in mind that for this design a strong requirement is that the technology must allow islands in order to place the body of the N-type transistors at different voltage levels. We can see how we design the multiplexer in Figure 4.11. If we have a look we can see that the first and the third transistors will be cut when the signal C0 or C2 are 2.5V and they will be on with 0V or lower voltages; the second transistor will be cut when the signal C1 is -2.5V and it will be on with 0V or lower voltages. The three signals that we have in the previous section are active at high level at 1.8V therefore we need to condition the signals to feed the transistors properly. In case of S0 and S2 that feed C0 and C2 we have added a inverter with voltages between 0 and 2.5. In the case of the S1 signal that feeds C1 we first add an inverter as in the previous case to have our signal between 0 and 2.5 volts and then we pass it through a level shifter like the one shown in Figure 4.12. The desired behaviour for the level shifter would be to obtain an output of 2.5V when the input is 2.5V and an output of -2.5V for an input of 0V. This level shifter design works as follows. When the input signal is 0V M1 is cut off unlike M0 that is on and put hight voltage in the base of M3 witch means that it is on and the output voltage will be -2.5V. When the input signal is 2.5V we have the dual case and the output will be 2.5V. With that configuration of level shifter there could be some fights between signals. To avoid them we must increase the size of M0 and M1 three times compared to M2 and M3.
29 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.11: Multiplexer based on three transistors.
In Figure 4.13 we can find the schematic that shows how we have connected the control signal generator with the multiplexer.
30 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
Figure 4.12: Level shifter.
Figure 4.13: Write driver.
31 CHAPTER 4. MULTI-LEVEL WRITE DRIVER DESIGN
32 Chapter 5
Multi-level Write Driver Characterisation
In this chapter we characterise the driver designed in the previous chapter and we compare the writing results with those obtained in Chapter 3. We tune the design parameters in order to improve the results and we analyse it in terms of power consumption and temperature variation.
5.1 Parameters
The first step is to show the list of parameters of the driver that we have considered with their proposed value.
1. V25 and V 25. We named like that the two different voltages needed in the setup pulse. Their nominal values are 2.5V and -2.5V respectively. 2. V23. We named like that the write voltage, the voltage that we apply in the variable pulse. Its nominal value was selected in Chapter 3 and corresponds to 2.3V.
There are other parameters like the initial gap of the memristor or the clock and enable voltage but we do not consider them because they should not affect these test cases. We fix the size of the transistors: the lengths in 150nm, the widths of p-transistors to 700nm and the width of the n-transistor to 360nm.
5.2 Test with nominal values
Figure 5.1 depicts the simulation results we obtain when the nominal values are applied (V23=2.3V V25=-V 25=2.5). We can observe that the chain of voltages is not exactly what we expect. The set up pulses are a little shorter than they should be but nevertheless they reach the key-point. The write pulse should be 2.3V according to Chapter 3 but, after the implementation it only reaches 2.26V. Remembering the Chapter 3 if the voltage is lower the curve where we are moving has less slope and therefore the values are greater than the nominal ones of Table 3.1.
33 CHAPTER 5. MULTI-LEVEL WRITE DRIVER CHARACTERISATION
3 2,32 2,26 2 1 0 -1 BL (V) BL -2 -2,47 -3 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 1,1
WL (V) WL 0,0
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 3M 3,267M 2M 1M Rout (V) Rout 0 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n t (s)
Figure 5.1: Test V23=2.3V V25=-V 25=2.5.
5.3 Test V23=2.4V
From the results of the previous section we can conclude that the write pulse should be slightly bigger to provide the desired resistance values. We decided to change the V23 from 2.3V to 2.4V and we can see the results of that correction in Figure 5.2. As we expected, the voltage in the write pulse has increased up to 2.35V. That increase means that we are little bit above, we expect to have lower resistance than shown in the table 3.1 and it is possible that we go to really low resistance values as in Figure 5.2.
5.4 Test V23=2.35V
The target value for the write pulse is 2.3V and we have seen how when we have V23=2.3V we do not reach it and when we have V23=2.4V we above it. We have tried to fix it with V23=2.35V in order to find something in the middle despise knowing that this voltage is really difficult to have. As we can see in Figure 5.3, the write pulse we obtain in this case is 2.31V.
34 CHAPTER 5. MULTI-LEVEL WRITE DRIVER CHARACTERISATION
3 2,32 2,36 2 1 0 -1 BL (V) BL -2 -2,47 -3 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 1,1
WL (V) WL 0,0
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 3M 2M 1M Rout (V) Rout 0 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n t (s)
Figure 5.2: Test V23=2.4V V25=-V 25=2.5V
5.5 Comparison between different V23 values.
In the previous sections we have exposed different simulations by changing the value of V23 and analysing the impact of these variations on their behaviour. In this section we are going to compare all of them together in Figure 5.4. We can find more details about the values shown in Appendix A. It is important to note that there may be cases in which the best curve is not the first (blue) despite being the closest to the nominal (red). If we are looking for 30 different values there are no doubt about what is the best option but if we want to use the system with only four or eight different values it might be better to choose another curve in which the values could be better separated.
5.6 Power consumption
In this section we show the results of power consumption in each of the previously exposed situations. We have analysed the static power consumption and the dynamic power consumption. To calculate the static one we have simulated the circuit without variation in the stimulus signals. For the dynamic analysis we have simulated the circuit with two complete writing cycles. For the dynamic test we selected the last value (A = 30) to save because it corresponds to the longest write pulse and the worst study case.
35 CHAPTER 5. MULTI-LEVEL WRITE DRIVER CHARACTERISATION
3 2,32 2,31 2 1 0 -1 BL (V) BL -2 -2,47 -3 0,0 10,0n 20,0n 30,0n 40,0n 50,0n 60,0n 70,0n 80,0n 90,0n 100,0n 1,1
WL (V) WL 0,0
0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 3M 3,080M 2M 1M Rout (V) Rout 0 -10n 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 110n t (s)
Figure 5.3: Test V23=2.35V V25=-V 25=2.5V
Table 5.1: Power consumption comparison.
Test Static Power (nW) Dynamic Power (µW) V23=2.3V V25=2.5V 119.2 559.7 V23=2.4V V25=2.5V 119.2 584.3 V23=2.35V V25=2.5V 119.2 565.2
36 CHAPTER 5. MULTI-LEVEL WRITE DRIVER CHARACTERISATION
3,5 3,0 2,5
) 2,0
R(theoretical) 1,5 R(2,3-2,5)
R (MR 1,0 R(2,4-2,5) R(2,35-2,5) 0,5 0,0 0 5 10 15 20 25 30 3,4
3,2 )
3,0
R (MR 2,8
2,6
0 5 10 15 20 25 30 time (nS)
Figure 5.4: Comparison of all simulated values.
37 CHAPTER 5. MULTI-LEVEL WRITE DRIVER CHARACTERISATION
38 Chapter 6
Conclusions and future work
In this last chapter we explain the conclusions that we have reached. We remember the objectives proposed and we try to value if they have been reached. After that we propose some future work that could complement and expand this work.
6.1 Conclusions
The main objectives of this project were the characterisation of different memristor models and the design of a write driver for use as a multi-level memory device. We can conclude that the project has fulfilled what was asked of it. We have defined the requirements or features that we would take into account and we analysed and compared two different models [5][7]. We selected one of them and we characterised it more in depth to define the needs of the writing driver. We define around 30 different levels more than the 16 that we proposed at the beginning. We studied different ways to develop the driver and we selected one of them. We tested our driver with the model selected before and we calculated the power consumption. As we expected the memristor is a really sensitive and non-linear device. The characterisation of the models that we have done verify that. A really small variation from the ideal chain of pulses that we should apply to save a value could lead to another value.
6.2 Future Work
Once the project is finished, we consider that some points of this project could be improved and we propose others in which we could continue working.
• Redesign of Pulse Generation. As we have seen in Chapter 5 we do not reach the desired value of voltage if we do not tune the supply voltages. We think that if we were able to fix the pulse voltages better we could obtain the curves that we propose in Chapter 3. • Temperature and manufacturing variations. We know that we have a sensitive device and could be a good idea to analyse it against temperature variations
39 CHAPTER 6. CONCLUSIONS AND FUTURE WORK
and manufacturing variations. Some times the memristor models have not this possibilities but at least it could be a good idea to analyse the write driver to see how the pulse generation changes and find the ranges where the driver may be considered reliable.
• Design of a read driver. The read driver seems like a necessary one but it could strongly depend on the application we are thinking about.
• Memory crossbar. Throughout the project we have treated the system as a single memristor but we would have to think of a set where with a single writing driver it could write in several memristor cells. A first idea that we could consider would be a common BL terminal and a control using the WL transistor but other ideas could be explored.
40 Appendix A
Resistance tables
In this appendix we use some acronym that we explain in the next list to better understand the tables:
1. P time → Pulse time. It corresponds with the time that the writing pulse is active.
2. Rnom → Nominal resistance simulated in Chapter 3.
3. Rsim → Simulated resistance using the write driver developed in Chapter 4.
4. Rdif → The difference calculated as Rth − Rsim.
5. Rdev → The deviation calculated as 100 ∗ Rdif /Rth.
41 APPENDIX A. RESISTANCE TABLES
Table A.1: Resistance comparison V23=2.3V.
P time(ns) Rnom(MΩ) Rsim(MΩ) Rdif (KΩ) Rdev 0 3.35455 - - 1 3.34729 3.349 -1.71 -0.05% 2 3.33856 3.344 -5.44 -0.16% 3 3.32955 3.339 -9.45 -0.28% 4 3.32026 3.334 -13.74 -0.41% 5 3.31069 3.329 -18.31 -0.55% 6 3.3008 3.324 -23.2 -0.70% 7 3.29058 3.318 -27.42 -0.83% 8 3.28 3.313 -33 -1.01% 9 3.26905 3.308 -38.95 -1.19% 10 3.25768 3.302 -44.32 -1.36% 11 3.24586 3.297 -51.14 -1.58% 12 3.23356 3.291 -57.44 -1.78% 13 3.22074 3.285 -64.26 -2.00% 14 3.20735 3.279 -71.65 -2.23% 15 3.19333 3.273 -79.67 -2.49% 16 3.17862 3.267 -88.38 -2.78% 17 3.16315 3.261 -97.85 -3.09% 18 3.14684 3.254 -107.16 -3.41% 19 3.12958 3.248 -118.42 -3.78% 20 3.11126 3.241 -129.74 -4.17% 21 3.09172 3.235 -143.28 -4.63% 22 3.07081 3.228 -157.19 -5.12% 23 3.0483 3.221 -172.7 -5.67% 24 3.02392 3.213 -189.08 -6.25% 25 2.99733 3.206 -208.67 -6.96% 26 2.96808 3.198 -229.92 -7.75% 27 2.93555 3.191 -255.45 -8.70% 28 2.89891 3.182 -283.09 -9.77% 29 2.85694 3.174 -317.06 -11.10% 30 2.80778 3.166 -358.22 -12.76%
42 APPENDIX A. RESISTANCE TABLES
Table A.2: Resistance comparison V23=2.4V.
P time(ns) Rnom(MΩ) Rsim(MΩ) Rdif (KΩ) Rdev 0 3.35455 - - 1 3.34729 3.324 23.29 0.70% 2 3.33856 3.292 46.56 1.39% 3 3.32955 3.259 70.55 2.12% 4 3.32026 3.218 102.26 3.08% 5 3.31069 3.176 134.69 4.07% 6 3.3008 3.123 177.8 5.39% 7 3.29058 3.063 227.58 6.92% 8 3.28 2.981 299 9.12% 9 3.26905 2.885 384.05 11.75% 10 3.25768 2.731 526.68 16.17% 11 3.24586 2.426 819.86 25.26% 12 3.23356 0.1703 3063.26 94.73% 13 3.22074 0.133 3087.74 95.87% 14 3.20735 0.1221 3085.25 96.19% 15 3.19333 0.1163 3077.03 96.36% 16 3.17862 0.1123 3066.32 96.47% 17 3.16315 0.1093 3053.85 96.54% 18 3.14684 0.1068 3040.04 96.61% 19 3.12958 0.1049 3024.68 96.65% 20 3.11126 0.1032 3008.06 96.68% 21 3.09172 0.1018 2989.92 96.71% 22 3.07081 0.1005 2970.31 96.73% 23 3.0483 0.09938 2948.92 96.74% 24 3.02392 0.09833 2925.59 96.75% 25 2.99733 0.09743 2899.9 96.75% 26 2.96808 0.09657 2871.51 96.75% 27 2.93555 0.0958 2839.75 96.74% 28 2.89891 0.09505 2803.86 96.72% 29 2.85694 0.0944 2762.54 96.70% 30 2.80778 0.09376 2714.02 96.66%
43 APPENDIX A. RESISTANCE TABLES
Table A.3: Resistance comparison V23=2.35V.
P time(ns) Rnom(MΩ) Rsim(MΩ) Rdif (KΩ) Rdev 0 3.35455 - - 1 3.34729 3.341 6.29 0.19% 2 3.33856 3.329 9.56 0.29% 3 3.32955 3.317 12.55 0.38% 4 3.32026 3.303 17.26 0.52% 5 3.31069 3.29 20.69 0.62% 6 3.3008 3.275 25.8 0.78% 7 3.29058 3.26 30.58 0.93% 8 3.28 3.244 36 1.10% 9 3.26905 3.229 40.05 1.23% 10 3.25768 3.211 46.68 1.43% 11 3.24586 3.193 52.86 1.63% 12 3.23356 3.172 61.56 1.90% 13 3.22074 3.152 68.74 2.13% 14 3.20735 3.13 77.35 2.41% 15 3.19333 3.106 87.33 2.73% 16 3.17862 3.081 97.62 3.07% 17 3.16315 3.052 111.15 3.51% 18 3.14684 3.02 126.84 4.03% 19 3.12958 2.986 143.58 4.59% 20 3.11126 2.945 166.26 5.34% 21 3.09172 2.902 189.72 6.14% 22 3.07081 2.849 221.81 7.22% 23 3.0483 2.787 261.3 8.57% 24 3.02392 2.703 320.92 10.61% 25 2.99733 2.599 398.33 13.29% 26 2.96808 2.426 542.08 18.26% 27 2.93555 2.018 917.55 31.26% 28 2.89891 0.1596 2739.31 94.49% 29 2.85694 0.134 2722.94 95.31% 30 2.80778 0.1242 2683.58 95.58%
44 Appendix B
VerilogA to Symbol in Cadence
45 Verilog-A to Symbol Cadence tutorial
Amadeo de Gracia Herranz February 2018
1 1 Abstract
The idea of this tutorial is to be able to generate a symbol from Verilog-A file. In the tutorial we are going to create a symbol from one simple component. The chosen component is a resistance.
2 New Cell
First of all we need to create the new cell. File →New →Cellview. Now we need to select the Library, write the name of the cell and write ”veriloga” in the view box and press ok.
Figure 1: New Cell
2 Figure 2: myVaResistor
3 Verilog-A editor
The text editor view will be open. Now we write or copy here the code and save the file.
Figure 3: Verilog-A editor view
3 The code can be copied from the following lines. //created by Amadeo de Gracia Herranz 02/2018 //based on https://www.simetrix.co.uk/
‘include ”constants .vams” ‘include ”disciplines .vams” module myVaResistor(p,n) ; inout p , n ; electrical p, n ;
parameter real res = 1000.0 from (0.0:inf] ;
analog begin I (p , n) <+ V(p,n)/res ; end endmodule
4 Symbol generator
After close the editor view a message will ask us if we want to create a symbol. We answer yes and the symbol generator options will appear. In that view we select the position of each pin and press ok.
Figure 4: Symbol generation options
4 Figure 5: Generated symbol
5 Adding symbol as an instance
Now we have the symbol linked with the Verilog-A file and we can use it in our designs. To be able to access to the parameters we should select ”veriloga” in the ”CDF Parameter of view” box.
5 Figure 6: Symbol generation options
Figure 7: Generated symbol
6 APPENDIX B. VERILOGA TO SYMBOL IN CADENCE
52 Appendix C
Ethical, Economic, Social and Environmental impact
In this appendix we discuss the possible impacts that the project will have in different fields.
C.1 Ethical impact
The project tries to make contributions in the field of neural networks and their implementations in the future. Neural networks are usually trained under a set of data given by the team of programmers. These teams have the responsibility to offer truthful datasets. Another problem related to automatic learning will come from the possibility of the machine having discriminatory behaviours as racist or sexist and it might not be clear who is responsible for this type of behaviours. Another of the most relevant problems related to neural networks and with all the technologies in general is the derivative of the elimination of jobs. When we develop a system which is able to perform a task that before was performed by a person for less money, with fewer errors and typically being able to work more time continuously we are in a hard situation because some people could lose their job.
C.2 Economic impact
The direct economic impact of this work is not too high since we are working with an immature device and even something far from being able to give money but its potential is very high. When we think on the field of memories that multilevel memory device could complement the other types of memories that we know and which we usually work. In the future we could have hard disk or memory stiks based on memristors and that could revolutionise the world of these elements, because they will be extremely compact and power efficient. As we said this project tries to contribute to neural networks. Currently some of
53 APPENDIX C. ETHICAL, ECONOMIC, SOCIAL AND ENVIRONMENTAL IMPACT the applications that try to take advantage of neural networks need to send the data to supercomputers since they are not able to perform the necessary calculations near the place where the data is collected. This need for movement of data is a great cost in terms of money and time. We think that a future neural network developed at a lower level (edge computing) using a crossbar of memristors could accelerate and miniaturise the hardware bringing it closer to the source of data and reducing the costs derived to the data transport.
C.3 Social impact
As we have seen in the Ethical impact the elimination of jobs would directly affect the society in which we live. Neural networks are being used in a lot of different fields of knowledge and they have a big impact in our society. Some of the main lines of work in neural networks are the language and image recognition, the robotics world, medical diagnostic and the predictions of different types of failures and behaviours. The reduction of size and cost and the increase of features could get even closer some topics like the self-driving cars, the voice assistants, the weather forecast or the detection of diseases in early stages of maturity.
C.4 Environmental impact
The development of technology usually has a high impact on the environment. The extraction and refinement for later use in circuits of minerals such as silicon or coltan or the use of electrical energy have a high impact on the environment. It is difficult to evaluate the environmental impact of this project. We propose to reduce the amount of some of those materials reducing the size of the circuits and that should be good in terms of environmental hazards. On the other hand we promote the use of memristors made by different types of oxides of titanium and tantalum and the manufacturing processes associated with these components are not well known at the moment. What is easy to evaluate in terms of environmental impact would be the foreseeable reduction in energy consumption that we would obtain with the use of these devices.
54 Appendix D
Cost of the system
In this appendix we expose our assessment of the costs associated with this project, knowing how to differentiate between material and software costs and personal costs.
• Materials and software. For the realisation of the project we have used a computer with a purchase cost of e2,000. To realise all the simulations and the test that we have exposed we have used the software tools Cadence and Matlab. The access to these tools has been made through the university or the research department but the cost of their licensed are around e2,500 per year.
• Human resources. The Master’s Thesis project has associated 30 ECTS (European Credit Transfer and Accumulation System) and each of this ECTS are equivalent to 30 hours of work. All of that means a 900 hours of work.
55 APPENDIX D. COST OF THE SYSTEM
56 Bibliography
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