Design of a Memristor-Based Digital to Analog Converter (DAC)

electronics

Article Design of a Memristor-Based Digital to Analog Converter (DAC)

Ghazal A. Fahmy * and Mohamed Zorkany

Electronics Department, National Telecommunication Institute, Cairo 11768, Egypt; [email protected] * Correspondence: [email protected]

Abstract: A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor- based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The ﬁgure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.

Keywords: memristor; DAC; ADC; sneak path

Citation: Fahmy, G.A.; Zorkany, M. Design of a Memristor-Based Digital 1. Introduction to Analog Converter (DAC). Electronics 2021, 10, 622. https:// Chua has discovered the existence of a passive two-terminal fundamental element, doi.org/10.3390/electronics10050622 which is called a memristor [1]. This element is characterized by the relationship between R t R t charge flux–linkage φ(t) and charge q(t), where φ(t) = −∞ v(t)dt and q(t) = −∞ i(t)dt Academic Editor: Kris Campbell respectively. This element has been presented as a fourth fundamental element. However, since that time, no physical element with f (φ, q) = 0 characteristics had been yet discovered. Received: 29 January 2021 Finally, in 2008, the Hewlett–Packard (HP) team proved the practical existence of the Accepted: 26 February 2021 memristor [2]. Since 2008, the memristor has become an interesting research topic and Published: 7 March 2021 attracted many scientists to conduct research on memristors in terms of several fields (such as modeling, fabrication, and characterization) and employ it towards different Publisher’s Note: MDPI stays neutral applications. with regard to jurisdictional claims in The change of flux–linkage φ(t) due to the change of charge q(t) is known as mem- published maps and institutional affil- ristive change (M), expressed as Wb/c or Ω, where M = dφ/dq. The memristor has a iations. characteristic behavior proposed by Chua [1] and modeled by at least 15 transistors and some passive components to emulate the behavior of a single memristor. Figure1 shows the relationship between the basic two-terminal elements: resistor, capacitor, inductor, and memristor. Copyright: © 2021 by the authors. Nowadays, memristor technology has entered different and important domains. It can Licensee MDPI, Basel, Switzerland. be used to build neuromorphic biological systems, artificial neural networks (ANN) (based This article is an open access article on its good ability to retain digital memory), and logic circuits. These features also enable it distributed under the terms and to play a role in new digital computer technology. It is very efficient to use in smart remote conditions of the Creative Commons sensing and Internet of Thing (IoT) applications, as it has a very low power consumption. Attribution (CC BY) license (https:// Due to these features of memristors, they have an efficient and effective way to store digital creativecommons.org/licenses/by/ data (as well as analog data) with power-efficient criteria [3]. 4.0/).

Electronics 2021, 10, 622. https://doi.org/10.3390/electronics10050622 https://www.mdpi.com/journal/electronics ElectronicsElectronics 20212021, 10, 10, x, 622FOR PEER REVIEW 2 of 17 2 of 16

FigureFigure 1. The1. The relationship relationship between between the basic the two-terminal basic two-terminal elements (resistor, elements capacitor, (resistor, inductor, capacitor, inductor, andand memristor). memristor).

TheNowadays, memristor has memristor been used intechnology non-linear analog has entere circuitd designs different (such and as oscillators important domains. It and digital to analog converters), since it has a lower area and is faster than the conventional CMOScan be circuit. used The to memristorbuild neuromor is a naturalphic counterpart biological to the systems, fundamental artificial digital neural to analog networks (ANN) relationship,(based on asits the good memristance ability to value retain changes digital according memory), to the and applied logic voltage. circuits. Along These features also withenable this, it the to memristor’s play a role current in new state digital depends computer on its previous technology. state, so itIt was is very recently efficient to use in usedsmart to design remote a digital sensing to analog and Internet converter of (DAC). Thing Since (IoT) the DACapplications, is the main as component it has a very low power of all data-driven acquisition circuits, it is the link between the analog signals of the real worldconsumption. and the digital Due signal to processingthese features field. So of much memristors, of the applied they research have is an conducted efficient and effective toway overcome to store the designdigital challenges data (as ofwell DAC as circuits, analog such data) as its with low areapower-efficient and low power criteria [4]. [3]. One ofThe the newest memristor ways to has overcome been used these in challenges non-linear is to analog use memristor circuit technology designs (such [5]. as oscillators Therefore,and digital there to are analog a few different converters), research since directions it has for a lower the use area of memristors and is faster in DAC than the conven- designs. For example, L. Danial et al. were able to calibrate a DAC design configuration tional CMOS circuit. The memristor is a natural counterpart to the fundamental digital to using neural networks as an artificial intelligence technique [6]. Another kind of research implementedanalog relationship, hybrid DAC as and the ADC memristance with a hybrid circuitvalue using changes memristors. according As L. Gaoto the et al. applied voltage. demonstrated,Along with DAC this, and the Hopfield-network memristor’s current ADC circuits state are depends able to utilize on post-fabricationits previous state, so it was resistancerecently tuning used featuresto design [7]. a Additionally, digital to analog F. Cai et converter al. designed (DAC). an integrated Since CMOSthe DAC is the main re-programmablecomponent of memristor all data-driven system based acquisition on DAC andcircui ADCts, for it theis the efficient link multiplicationbetween the analog signals of accumulated operations, and they subsequently used that design to implement a multi- layerof the neural real network world [and8]. the digital signal processing field. So much of the applied research is conductedA 2 bit hybrid to memristor overcome and the a CMOS design technology-based challenges of DACDAC were circuits, presented such in as [9], its low area and usinglow apower non-overlapped [4]. One signalof the to newest achieve ways the basic to cellovercome for DAC. these In this challenges model, the DAC is to use memristor areatechnology does not significantly[5]. Therefore, reduce there due to are the usea few of five different transistors, research one resistor, directions and a for the use of buffer circuit, all of which affect the total area of DAC. Moreover, the author did not memristors in DAC designs. For example, L. Danial et al. were able to calibrate a DAC declare how to extend his proposed 2 bit DAC to n bit DAC. In this work, we proposed adesign 2 bit memristor configuration DAC without using an neural included networks resistor element,as an artificial transistors, intelligence or buffer that technique [6]. An- willother reduce kind the of DAC research area significantly. implemented Moreover, hybrid the nDAC bit DAC and has ADC been with addressed a hybrid in circuit using thismemristors. work and has As been L. Gao verified et al. by demonstrated, two case studies. DAC There and are severalHopfield-network designs using aADC circuits are memristorable to utilize to develop post-fabrication an analog to digital resistance converter tuning (ADC) features [10,11]. For [7]. example, Additionally, a hybrid F. Cai et al. de- CMOS–memristor logic gate (known as memristor-ratioed logic (MRL)) has been deployed insigned the digital an integrated blocks of the CMOS pipeline re-programmable ADC to decrease the memristor clock delay further system and based increase on DAC and ADC thefor logic the density efficient [12, 13multiplication]. A memristor-based of accumulated flash ADC was operations, also provided and in [ 14they]. In thissubsequently used work,that adesign successive to implement approximation a multi-layer register analog neural to digital network converter [8]. (SAR-ADC) using the proposedA 2 bit memristor hybrid memristor DAC has been and provided a CMOS to achievetechnology-based low area and lowDAC power, were as presented in [9], will be explained in Section5. usingIn this a non-overlapped work, a basic cell for signal DAC thatto achieve uses a memristor the basic element cell for has DAC. been proposed.In this model, the DAC Thearea proposed does not DAC significantly cell was used reduce to design due a thermometerto the use codeof five to analogtransistors, and study one resistor, and a thebuffer characteristics circuit, all of DAC. of which The binary-weighted affect the total DAC area cell of based DAC. on Moreover, two memristors the was author did not de- proposedclare how with to a sneakextend path his solution. proposed 2 bit DAC to n bit DAC. In this work, we proposed a 2 bit memristor DAC without an included resistor element, transistors, or buffer that will reduce the DAC area significantly. Moreover, the n bit DAC has been addressed in this work and has been verified by two case studies. There are several designs using a memristor to develop an analog to digital converter (ADC) [10,11]. For example, a hybrid CMOS– memristor logic gate (known as memristor-ratioed logic (MRL)) has been deployed in the digital blocks of the pipeline ADC to decrease the clock delay further and increase the logic density [12,13]. A memristor-based flash ADC was also provided in [14]. In this work, a successive approximation register analog to digital converter (SAR-ADC) using

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The design of memristor-based circuits still faces some challenges and problems. One of the main challenges at the architecture and circuit level is the sneak path current problem [15]. Some solutions to this problem established a sophisticated classiﬁcation, like the one diode–one memristor model (1D1M), the one transistor–one memristor model (1T1M), and the one selector–one memristor model (1S1M). Some other solutions depend on self-rectifying and self-selective memristors [16]. More research is still urgently needed to overcome this problem. This paper is organized as follows: Section2 presents the memristor element characteristics. Section3 focuses on the ratioed logic (MRL logic) of how the circuit operates. Section4 proposes a DAC cell based on memristors, with accompanying simulations. There are four subsections that cover the thermometer DAC and binary DAC, with a case study conducted on each of them. Section 4.1 includes the proposed 2 bit DAC cell and its simulation, while Section 4.2 explains how to use the proposed DAC cell to design a thermometer code to analog conversion. Section 4.3 explains the proposed binary-weighted memristor DAC cell and then explains how to extend it to n bit DAC, while Section 4.4 studies the sneak path issues and employs one of the derived solutions in the proposed design. Section5 covers the case study for the memristor DAC and its use in the SAR-ADC by replacing the conventional capacitor DAC with the proposed memristor DAC. The last section explains the conclusion of this work, followed by the references.

2. Memristive Element Characteristics There are numerous mathematical models developed by researchers to describe the behavior of memristors. The linear ion drift model, the non-linear ion drift model, the Sim- mons tunnel barrier model, the threshold adaptive memristor (TEAM) model, Yakopcic’s model, and the voltage threshold adaptive memristor (VTEAM) are some of the widely accepted models in the literature. The VTEAM model is used in this work due to its ability to ﬁt most of the switching characteristics exhibited by memristor devices. Moreover, it is an accurate model to represent non-linear memristor behaviors. In order to study the characteristics of the memristor element of the VTEAM model, the relationship between voltage and current in the memristor element is expressed in the following mathematical model [9]:

W(t) W(t) v(t) = [R + R (1 − )]i(t) (1) on D o f f D

 v(t) αo f f  ko f f ( − 1) fo f f (w), 0 < Vo f f < v  Vo f f dw(t)  = 0, Von < v < Vo f f (2) dt   ( ) αon  k ( v t − 1) f (w), v < V < 0 on Von on on where v(t) is the voltage across the memristor terminals, i(t) is the current passing through the memristor, and αo f f , αon, ko f f , and kon are ﬁtting parameters. Von and Vo f f are threshold voltages. fon(w) and fo f f (w) are window functions used to limit w to have a value between 0 and 1. This state variable represents the state of the memristor. In Equation (1), v(t) can be written as time varying resistance (Rm(t)), which can multiply the memristor by i(t) as follows:

v(t) = Rm(t)i(t) (3)

where Rm(t) will be written as

W(t) W(t) R (t) = R + R (1 − ) (4) m on D o f f D

where Ron is on-state resistance (with a high dopant concentration) and Ro f f is off-state resistance (with a low dopant concentration). A non-linear relationship between voltage and current in Equation (1) results in the relationship exhibiting pinched hysteresis loop Electronics 2021, 10, x FOR PEER REVIEW 4 of 16

where () will be written as () () () = + (1 − ) (4) Electronics 2021, 10, 622 4 of 17 where is on-state resistance (with a high dopant concentration) and is off-state resistance (with a low dopant concentration). A non-linear relationship between voltage and current in Equation (1) results in the relationship exhibiting pinched hysteresis loop I–VI–V characteristics. characteristics. Several Several models models have have been been proposedproposed forfor memristors, memristors, some some of of which which did didnot not include include a thresholda threshold voltage voltage or or a currenta current parameter. parameter. Other Other models models have have included included the thethreshold threshold current current parameters parameters (such (such as the as TEAMthe TEAM model). model). However, However, the experiment the experiment proved provedthe existence the existence of threshold of threshold voltage. voltage. The VTEAM The VTEAM Model Model has included has included the threshold the threshold voltage voltagethat satisfied that satisfied these experimental these experimental results andresults has and presented has presented sufficient sufficient accuracy accuracy compared comparedto that of to the that existing of the existing model. model. Figure Figu2 showsre 2 shows the ideal the ideal memristor memristor I–V curveI–V curve with with two twodifferent different setups. setups. The The difference difference between between the the setup setup circuits circuits of of Figure Figure2a,b 2a,b is theis the flipping flip- pingof theof the memristor memristor direction. direction. Consequently, Consequently, the the I–V I–V curve curve illustrates illustrates the the opposite opposite state state of a ofmemristor. a memristor. In setupIn setup (a), (a), the the memristor memristor element element changes changes from from off-state off-state to on-state to on-state when +V whenthe appliedthe applied voltage voltage is greater is greater than than th+. However,. However, in setupin setup (b), (b), the the memristor memristor element ele- changes from off-state to on-state when the applied voltage is less than −V . ment changes from off-state to on-state when the applied voltage is less thanth −.

(a) (b)

FigureFigure 2. 2.TheThe ideal ideal curve curve of of current–voltage current–voltage characteristics characteristics when (a) thethe positivepositive terminal terminal is is connected connected to the supply and the negative terminal is connected to the ground and (b) the negative to the supply and the negative terminal is connected to the ground and (b) the negative terminal is terminal is connected to the supply and the positive terminal is connected to the ground. connected to the supply and the positive terminal is connected to the ground. Memristor Setup and Characteristic Memristor Setup and Characteristic The VTEAM model has been employed to test the characteristics of the memristor The VTEAM model has been employed to test the characteristics of the memristor device [17]. Figure 3 shows the characteristic setup circuit. The VTEAM model’s parame- device [17]. Figure3 shows the characteristic setup circuit. The VTEAM model’s parameters ters included in this setup are = −0.2 , = 0.02 , =50 Ω (for on-re- included in this setup are Von = −0.2 V, Vo f f = 0.02 V, Ron = 50 Ω (for on-resistance), sistance), and = 1000 Ω (for off-resistance), with delta-time () set to be 10 for and R = 1000 Ω (for off-resistance), with delta-time (dt) set to be 10−12 for simulation simulationo f f purposes and the input signal is a sine-wave with a frequency of 1 and purposes and the input signal is a sine-wave with a frequency of 1 MHz and a peak voltage Electronics 2021, 10, x FOR PEER REVIEWa peak voltage of 1 . A cadence tool has been used to simulate the VTEAM verilog-A5 of 16 of 1 V. A cadence tool has been used to simulate the VTEAM verilog-A model. The VTEAM model. The VTEAM model parameters used in the setup simulation are as follows in Table model parameters used in the setup simulation are as follows in Table1. 1.

Table 1. The VTEAM model parameter used in setup circuit for simulation

3 [Ω] 1000 1 [Ω] 50 −9 [] −0.2 [] 3 × 10 [] 0.02 [] 3 × 10−9 −4 [/] 5 × 10 [] 0 [/] −10 [] 0

Figure 3. 3. SetupSetup circuit circuit for forthe simulation the simulation memristo memristorr voltage voltage threshold threshold adaptive adaptive memristor memristor

(VTEAM)(VTEAM) model.model.

Figure 4 shows the characteristics of the memristor device with the previous parameters instated. The I–V relation curve illustrates the pinched-off circuit at the zero crossing and has voltage thresholds at = −0.2 and =0.3 , which prove that the memristor device has two-threshold voltages, as presented in [17].

Figure 4. The I–V simulation curve of setup 3.

3. Memristor Ratioed Logic (MRL) Many approaches have been proposed to implement logic gate circuits employing only memristor elements in [18,19], while in other approaches, hybrid memristor elements and CMOS structures are used to implement logic gates [20]. Basic logic gates (such as AND- and OR-gates) have been provided using two memristors combined with the appropriate polarities [20]. This approach has been simulated and illustrated in this work to deeply understand the connection between two memristors and how it works as follows: Figure 5a shows an AND-gate where the and are connected to a negative memristor sign and the positive memristor sign it is connected to gathers the output voltage . The is expressed as follows:

∗ + ∗ = (5) +

where and are the memristor resistances (which will be on-resistance () or off-resistance () according to the applied voltage on the corresponding memristor). Table 2 illustrates the different states of each memristor according to the applied voltage. This topology functions as an AND-gate. Figure 5b shows an OR-gate where and

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Table 1. The VTEAM model parameter used in setup circuit for simulation.

aoff 3 Roff [Ω] 1000

aon 1 Ron [Ω] 50 −9 Von [V] −0.2 D [nm] 3 × 10 −9 Voff [V] 0.02 woff [nm] 3 × 10 Figure 3. Setup circuit for the simulation memristor voltage threshold adaptive memristor −4 (VTEAM) model.koff [m/s] 5 × 10 won [nm] 0

kon [m/s] −10 winit [nm] 0 Figure 4 shows the characteristics of the memristor device with the previous parameters instated.Figure The4 shows I–V relation the characteristics curve illustrates of the the memristor pinched-off device circuit with at the zero previous crossing parame- and hasters instated.voltage thresholds The I–V relation at curve= −0.2 illustrates and the pinched-off=0.3 , which circuit prove at the zerothat crossingthe memristorand has device voltage has two-threshold thresholds at Vvoltages,th1 = − as0.2 presentedV and V thin2 [17].= 0.3 V, which prove that the memristor device has two-threshold voltages, as presented in [17].

FigureFigure 4. The 4. I–VThe simulation I–V simulation curve curveof setup of setup3. 3.

3. Memristor3. Memristor Ratioed Ratioed Logic Logic (MRL) (MRL) ManyMany approaches approaches have have been been proposed proposed to toimplement implement logic logic gate gate circuits circuits employing employing only only memristor elements in [18,19], [18,19], while while in in other other approaches, approaches, hybrid hybrid memristor memristor elements elements and and CMOSCMOS structures structures are used to implementimplement logiclogic gatesgates [20[20].]. BasicBasic logic logic gates gates (such (such as as AND- AND-and and OR-gates) OR-gates) have have been been provided provided using using two two memristors memristors combined combined with with the the appropriate ap- propriatepolarities polarities [20]. [20]. This This approach approach has has been been simulated simulated and and illustrated illustrated in thisin this work work to to deeply deeplyunderstand understand the the connection connection between between two two memristors memristors and and how how it works it works as follows: as follows:Figure 5a V V Figureshows 5a shows an AND-gate an AND-gate where thewherein 1theand in2 andare connected are connected to a negative to a memristor negative sign memristorand the sign positive and the memristor positive memristor sign it is connected sign it is connected to gathers to the gathers output the voltage outputVo 1volt-. The Vo1 is expressed as follows: age . The is expressed as follows: R ∗ V + R ∗ V V = m1 in2 m2 in1 (5) o1 ∗R++R∗ = m1 m2 (5) + where Rm1 and Rm2 are the memristor resistances (which will be on-resistance (Ron) or whereoff-resistance and (R o are f f ) the according memristor to the resistances applied voltage(which onwill the be correspondingon-resistance ( memristor).) or off-resistanceTable2 illustrates () according the different to the states applied of each voltage memristor on the according corresponding to the memristor). applied voltage. TableThis 2 illustrates topology the functions different as states an AND-gate. of each memristor Figure5b showsaccording an OR-gate to the applied where voltage.Vin1 and Vin2 This aretopology applied functions to a positive as an memristor AND-gate. sign Figure and 5b the shows negative an memristorOR-gate where sign it is connected and to gathers the output voltage Vo1 and is expressed in Equation (5). Table3 explains the functionality of the OR-Gate and the status of each memristor element.

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are applied to a positive memristor sign and the negative memristor sign it is con- Electronics 2021, 10, 622 nected to gathers the output voltage and is expressed in Equation (5). Table 3 explains6 of 17 the functionality of the OR-Gate and the status of each memristor element.

(a) (b)

Figure 5. Two memristors connected as (a) an AND-gate and (b) an OR-gate. Figure 5. Two memristors connected as (a) an AND-gate and (b) an OR-gate. Table 2. The different states of each memristor for Figure5a. Table 2. The different states of each memristor for Figure 5a. Vin1 Vin2 Rm2 Rm1 Vo1 High High Ro f f R o f f High High Low Ron Ro f f Low Low High Ro f f Ron Low Low Low Ro f f Ro f f Low Table 3. The different states of each memristor for Figure 5b.

Table 3. The different states of each memristor for Figure5b. V V R R V in1 in2 m2 m1 o1 High High Ron Ron High High Low Ro f f Ron High 4. ProposedLow DAC Cell Based High on Memristor Technology Ron Ro f f High The mostLow two common Lowtypes of DAC architecture Ro f f are a thermometerRo f f DACLow and a binary-weighted DAC. In this work, a basic cell for DAC architecture will be proposed based4. on Proposed memristor DAC technology Cell Based for on both Memristor types of TechnologyDAC. Moreover, two case studies using the proposedThe mostDAC two architecture common will types be of provided. DAC architecture The first case are astudy thermometer concerns DAC a ther- and a mometerbinary-weighted code to analog DAC. converter-based In this work, 2 a bi basict memristor-based cell for DAC architecture DAC. However, will be the proposed second basedcase onstudy memristor concerns technology a memristor for both DAC- typesbased of DAC. successive Moreover, approximation two case studies register using the (SAR-ADC).proposed As DAC the architecturedesign of memristor-based will be provided. circuits The first faces case sneak study path concerns current a problems, thermometer we willcode propose to analog a solution converter-based to overcome 2 bit this memristor-based problem based on DAC. a low However, power amplifier. the second The case followingstudy subsections concerns a memristorexplain the DAC-based proposal in successivedetail. approximation register (SAR-ADC). As the design of memristor-based circuits faces sneak path current problems, we will 4.1. proposeDAC Cell a Based solution on toa Memristor overcome Device this problem based on a low power amplifier. The following subsectionsThe basic structure explain the of proposala thermometer-co in detail. ded DAC has an equal resistor (current– source segment) for each output value of DAC. Designing the thermometer DAC cell us- 4.1. DAC Cell Based on a Memristor Device ing memristor technology will add all of the advantages of memristors to DAC, such as a good efficientThe basic way structureto store digital of a thermometer-coded and analog data with DAC power-efficient has an equal resistor criteria. (current–source The pro- posedsegment) thermometer for each DAC output cell depends value of on DAC. the use Designing of two memristors the thermometer connected DAC with cell an using oppositememristor sign. technologyFigure 6a,b will show add a all basic of the DAC advantages cell using of memristors a memristor, to DAC, where such the as two a good efficient way to store digital and analog data with power-efficient criteria. The proposed memristors are structured in opposite signs. The is applied on the negative side of thermometer DAC cell depends on the use of two memristors connected with an opposite and the is applied on the positive side of . The positive and negative sides sign. Figure6a,b show a basic DAC cell using a memristor, where the two memristors of and , respectively, are connected to the output node . could be on- are structured in opposite signs. The Vin1 is applied on the negative side of Rm1 and the state or off-state, according to the direction of the memristor at certain values of . The Vin2 is applied on the positive side of Rm2. The positive and negative sides of Rm1 and Rm2, respectively, are connected to the output node Vo1. Rm could be on-state or off-state, according to the direction of the memristor at certain values of Vth. The two memristors

have the same value for off-resistor (Ro f f = 1000 Ω) and on-resistor (Ron = 50 Ω). In this work, the input voltage will be 0 V or 1 V. When the applied voltage Vin1 is 1 V and Vin2 is Electronics 2021, 10, x FOR PEER REVIEW 7 of 16 Electronics 2021, 10, x FOR PEER REVIEW 7 of 16

two memristors have the same value for off-resistor ( = 1000 Ω) and on-resistor two memristors have the same value for off-resistor ( = 1000 Ω) and on-resistor ( = 50 Ω). In this work, the input voltage will be 0 or 1 . When the applied voltage = 50 Ω 0 1 Electronics 2021, 10, 622 ( ). In this work, the input voltage will be or . When the applied voltage7 of 17 is 1 and is 0 , the current will flow from to . Consequently, is 1 and is 0 , the current will flow from to . Consequently, and will change to , and the will be 0.5 . On the other hand, when the ap- and will change to , and the will be 0.5 . On the other hand, when the applied voltage is 1 and is 0 , the current will flow from to . Conse- plied voltage is 1 and is 0 , the current will flow from to . Conse- quently,0 V, the current and will flow will from changeVin1 to V into2. Consequently,, and the Rm1 andwillR mbe2 will0.5 change as well. to Ro fIn f , these quently, and will change to , and the will be 0.5 as well. In these twoand cases, the V othe1 will output be 0.5 voltageV. On the is otherthe same hand, but when the thecurrent applied of the voltage secondVin2 caseis 1 V is and muchVin 1greater two cases, the output voltage is the same but the current of the second case is much greater thanis 0 thatV, the of current the first will case flow due from to Vin2 to beingVin1. Consequently,much less thanR m1 and. FigureRm2 will 7 changeshows tothe sim- than that of the first case due to being much less than . Figure 7 shows the sim- Ron, and the Vo1 will be 0.5 V as well. In these two cases, the output voltage is the same ulation of the third topology with the following sequence of inputs for (,): (0,0), ulationbut of thethe currentthird topology of the second with case the isfollowing much greater sequence than that of inputs of the firstfor case( due, to): (0,0),R (0,1), (1,1), (0,1), and (0,0). The output voltage and memristor current are shown inon Figure (0,1), (1,1),being (0,1), much and less (0,0). than TheR output. Figure 7voltage shows theand simulation memristor of current the third are topology shown with in Figure the 7. The output voltage willo f f be three levels (according to this sequence of inputs), while the 7. The followingoutput voltage sequence will of be inputs three for levels (Vin1 (according,Vin2): (0,0), to (0,1), this (1,1), sequence (0,1), and of inputs), (0,0). The while output the current will be either 0 or 10 mA. If the sequence of inputs has been replaced with (0,0), currentvoltage will be and either memristor 0 or 10 current mA. If are the shown sequen ince Figure of inputs7. The has output been voltage replaced will with be three (0,0), (1,0), (1,1), (1,0), and (0,0), the output voltage will be the same while the current will be (1,0), (1,1),levels (1,0), (according and (0,0), to this the sequence output ofvoltage inputs), will while be thethe currentsame while will be the either current 0 or 10 will mA. be reducedIf the sequence significantly of inputs due has to been entering replaced the with off- (0,0),state (1,0), of the (1,1), memristor, (1,0), and (0,0), which the outputhas high re- reduced significantly due to entering the off-state of the memristor, which has high re- sistancevoltage ( will be) as the shown same in while Figure the current8. This topology will be reduced will function significantly as the due basic to entering cell for struc- sistance () as shown in Figure 8. This topology will function as the basic cell for struc- turingthe off-state the digital of the to memristor, analog converter which has to high convert resistance the thermometer (Ro f f ) as shown code in to Figure an analog8. This signal. turing topologythe digital will to functionanalog converter as the basic to cellconvert for structuring the thermometer the digital code to analogto an analog converter signal. to convert the thermometer code to an analog signal.

(a) (b) (a) (b) Figure 6. The proposed digital to analog converter (DAC) cell, with two memristors connected Figure 6.Figure The proposed 6. The proposed digital digital to analog to analog converter converter (DAC) (DAC) cell, cell, with with two two memristors connected connected with with an opposite sign. (a) When . (b) When . with anan opposite opposite sign. sign. ( (aa)) When When Vin1 >Vin2.(. b()b When) WhenVin 2 > Vin1..

FigureFigure 7. 7. SimulationSimulation of the proposedproposed DAC DAC cell cell with with the the following following sequence sequence of inputs of inputs for (Vin for1,V in2): Figure 7. Simulation of the proposed DAC cell with the following sequence of inputs for ((0,0),, (0,1),): (0,0), (1,1), (0,1), (0,1), and(1,1), (0,0). (0,1), and (0,0). (,): (0,0), (0,1), (1,1), (0,1), and (0,0).

Electronics 2021, 10, x FOR PEER REVIEW 8 of 16 Electronics 2021, 10, 622 8 of 17

FigureFigure 8. 8. SimulationSimulation ofof thethe proposed proposed DAC DAC cell cell with with the followingthe following sequence sequence of inputs of inputs for (Vin 1for,Vin 2): (0,0), (1,0), (1,1), (1,0), and (0,0). (,): (0,0), (1,0), (1,1), (1,0), and (0,0). 4.2. Design of the Thermometer Code to Analog Converter Based on Memristor 4.2. Design of the Thermometer Code to Analog Converter Based on Memristor A thermometer code to analog signal is a type of digital to analog converter (DAC). It is requiredA thermometer to convert a thermometercode to analog code signal to an analogis a type signal. of digital It can useto analog the conventional converter re- (DAC). Itsistance is required string to or convert a capacitor a thermometer array, which requires code to much an analog more area signal. to implement. It can use By the using conven- tionalthe memristor, resistance however, string or it a can capacitor be realized array, in a which small area requires with lowmuch power more consumption. area to implement. By usingAn eightthe memristor, level thermometer however, code it was can used be realized to construct in thea small memristor area with DAC, low as shown power consumption.in Figure9 , which contains three stages. Stage one is an input stage for the binary data D , D , while stage three is the output stage, containing one DAC cell. Each DAC cell 0 An7 eight level thermometer code was used to construct the memristor DAC, as includes two connected memristors in the opposite sign. In order to extend the DAC input shownfrom 8 in to Figure 16, the input9, which of the contains DAC cell three should stages. double. Stage The one following is an input equation stage describes for the binary datathe total, number, while of stage DAC three cells required is the output for n number stage, containing of inputs: one DAC cell. Each DAC cell includes two connected memristors in the opposite sign. In order to extend the DAC input from 8 to 16, the input of the DAC cellCt =shouldbn − 1 double. The following equation describes (6) the total number of DAC cells required for n number of inputs: where bn is the number of inputs and Ct is the total number of DAC cells required to achieve the DAC circuit. The total amount of memristors required for DAC is 2(b − 1). = −1 n (6) Figure 10 shows the simulation for the DAC circuit in Figure 11. whereThe integralis the number non-linearity of inputs (INL) and is one of is the the DAC total speciﬁcations number of DAC used tocells measure required to achievethe deviation the DAC between circuit. the The ideal total output amount value andof memristors the actual output required value. for This DAC deviation is 2( −1). Figureshould 10 be shows less than the± simulation0.5 least signiﬁcant for the DAC bit (LSB). circuit The in LSB Figure value 11. is 100 mV in this case. The INL simulation has been illustrated in Figure 11. It demonstrates that INL is 8 mV when time is greater than 1 µs, but at the starting time, the maximum INL value of 33 mV was recorded. The INL achieved less than ± 0.5 LSB.

Figure 9. An eight level input memristor-based DAC circuit.

Electronics 2021, 10, x FOR PEER REVIEW 8 of 16

Figure 8. Simulation of the proposed DAC cell with the following sequence of inputs for (,): (0,0), (1,0), (1,1), (1,0), and (0,0).

4.2. Design of the Thermometer Code to Analog Converter Based on Memristor A thermometer code to analog signal is a type of digital to analog converter (DAC). It is required to convert a thermometer code to an analog signal. It can use the conventional resistance string or a capacitor array, which requires much more area to implement. By using the memristor, however, it can be realized in a small area with low power consumption. An eight level thermometer code was used to construct the memristor DAC, as shown in Figure 9, which contains three stages. Stage one is an input stage for the binary data ,, while stage three is the output stage, containing one DAC cell. Each DAC cell includes two connected memristors in the opposite sign. In order to extend the DAC input from 8 to 16, the input of the DAC cell should double. The following equation describes the total number of DAC cells required for n number of inputs:

= −1 (6)

Electronics 2021, 10, 622 where is the number of inputs and is the total number of DAC cells required9 of 17to achieve the DAC circuit. The total amount of memristors required for DAC is 2( −1). Figure 10 shows the simulation for the DAC circuit in Figure 11.

Electronics 2021, 10, x FOR PEER REVIEW 9 of 16

FigureFigure 9. 9.An An eighteight level level input input memristor-based memristor-based DAC DAC circuit. circuit.

Figure 10. Simulation of an eight level input memristor-based DAC circuit. Figure 10. Simulation of an eight level input memristor-based DAC circuit. Figure 10. Simulation of an eight level input memristor-based DAC circuit.

FigureFigure 11. 11. IntegralIntegral non-linearity non-linearity (INL) (INL) simulation simulation forfor anan eighteight level level input input memristor-based memristor-based DAC DAC circuit. Figurecircuit. 11. Integral non-linearity (INL) simulation for an eight level input memristor-based DAC circuit. The integral non-linearity (INL) is one of the DAC specifications used to measure the deviationThe integral between non-linearity the ideal (INL)output is valueone of andthe DACthe actual specifications output vausedlue. to This measure deviation the deviationshould be between less than the ± ideal0.5 least output significant value andbit (LSB). the actual The LSB output value va islue. 100 ThismV indeviation this case. shouldThe INL be lesssimulation than ± has0.5 leastbeen significantillustrated bitin (LSB).Figure The 11. LSBIt demonstrates value is 100 thatmV inINL this is case.8 mV Thewhen INL time simulation is greater has than been 1 illustrated, but at inthe Fi startinggure 11. time, It demonstrates the maximum that INL INL value is 8 mVof 33 whenmV wastime recorded. is greater The than INL 1 achieved, but at less the than starting ± 0.5 time, LSB. the maximum INL value of 33 mV was recorded. The INL achieved less than ± 0.5 LSB. 4.3. Binary-Weighted DAC Cell-Based on Memristor 4.3. Binary-WeightedPlenty of binary-weighted DAC Cell-Based DAC on architecturesMemristor are used to convert digital word bits to analogPlenty signals. of binary-weighted Some DAC are DAC quite architectures simple, using are few used switches to convert and resistors.digital word Other bits DAC to analogarchitectures signals. dependSome DAC on arethe quitecapacitor simple, network using fewor the switches source and of resistors.the transistor Other current. DAC architecturesHowever, these depend DAC on architectures the capacitor have network limitations or the in source terms ofof thearea, transistor speed, resolution, current. However,and mismatch these error.DAC architecturesThis section explainshave limitations the modification in terms thatof area, has beenspeed, applied resolution, to the andproposed mismatch thermometer error. This DACsection cell explains in the previousthe modification section inthat order has forbeen it appliedto be used to theas a proposedbinary DAC thermometer cell. DAC cell in the previous section in order for it to be used as a binary DAC cell.

Electronics 2021, 10, 622 10 of 17

4.3. Binary-Weighted DAC Cell-Based on Memristor Plenty of binary-weighted DAC architectures are used to convert digital word bits to analog signals. Some DAC are quite simple, using few switches and resistors. Other DAC architectures depend on the capacitor network or the source of the transistor current. Electronics 2021, 10, x FORElectronics PEER REVIEW 2021, 10, x FOR PEER REVIEW 10 of 16 10 of 16 However, these DAC architectures have limitations in terms of area, speed, resolution, and mismatch error. This section explains the modification that has been applied to the proposed thermometer DAC cell in the previous section in order for it to be used as a binary DAC cell. In the thermometerIn DACthe thermometer cell, it is assumed DAC cell,that itthe is assumed (which that is the or (which ac- is or according to the statecording of theIn thememristor) to thermometerthe state ofof boththe DAC memristor) memristors cell, it is assumed of is both equal. that memristors theHowever,Rm (which is in equal. istheR onbinary- However,or Ro f f according in the binary- to the state of the memristor) of both memristors is equal. However, in the binary-weighted weighted DAC cell,weighted is doubleDAC cell, the value is of double , asthe shown value inof Figure, as 12a. shown Where in Figure D0 is 12a. Where D0 is DAC cell, Rm1 is double the value of Rm2, as shown in Figure 12a. Where D0 is a less a less significant bit,a less D1 significantis most significant bit, D1 is bit, most and significant is the bit, output and voltage. is the Figure output 13 voltage. Figure 13 significant bit, D1 is most significant bit, and Vout is the output voltage. Figure 13 shows shows that the simulationshowsthat the that simulation of thethe 2simulation bit of thebinary 2 bit of binaryDAC the within2 DAC bit binary within input inputDAC voltage voltage within for for bothinput both D0 voltage D0 and and D1 for are both 1 V, D0 and D1 are 1 V, and theD1and output are the 1 output V,voltage and voltage the varies output varies from from voltage 0 0V V to tovaries 1 1 V. V. EachEach from step step 0 V level levelto is1 0.33V.is 0.33Each V. The V. step inputThe level frequency is 0.33 V. The input frequency ofinputof the the binary binaryfrequency data data ofis 11the MHz.MHz. binary data is 1 MHz.

(a) (a) (b) (b)

Figure Figure12. A binary-weighted 12. A binary-weightedFigure 12. DAC A binary-weighted DAC cell. cell. (a) A (a )2 A bit 2 bitDACDAC DAC cell.cell cell circuit.(a circuit.) A 2 bit(b (b) ) DACA A 4 4 bit cell DACDAC circuit. cellcell circuit. (circuit.b) A 4 bit DAC cell circuit.

Figure 13. SimulationFigure of a 2 13.13. bitSimulation Simulationbinary-weighted of of a 2a bit2 bitDAC binary-weighted binary-weighted cell. DAC DAC cell. cell. Four bit binary data have been constructed, as shown in Figure 12b, where the values Four bit binary dataFour have bit been binary constructed, data have asbeen shown constructed, in Figure as 12b, shown where in Figurethe values 12b, where the values of Rm0, Rm2, and Rm3 are double those of Rm1, Rm3, and Rm5, respectively. Figure 14 of , , and ofshows are the, double simulation, and those of 4 ofare bit binary double, DAC those, and compared of , withrespectively., the, and ideal DACFigure, torespectively. study14 the INL, Figure 14 shows the simulationshowsas shown of 4 the bit in simulationbinary Figure 15DAC. The of compared 4 voltage bit binary step with DAC for 4the bit compared ideal DAC DAC is 10.5 with to mV, study the while ideal the the INL,DAC maximum to study INL the INL, as shown in Figureas 15. shown The voltage in Figure step 15. for The 4 bit voltage DAC stepis 10.5 for mV, 4 bit while DAC the is 10.5 maximum mV, while INL the maximum INL is 3 mV, which is lessis 3 than mV, thewhich 50% is theless value than theof LSB. 50% During the value an alysisof LSB. of During a 4 bit DAC analysis based of a 4 bit DAC based on memristor technology,on memristor a sneak technology, path problem a sneak was path noticed, problem which was will noticed, be explained which inwill be explained in the following section.the following section.

Electronics 2021, 10, 622 11 of 17

ElectronicsElectronics 20212021,, 1010,, xx FORFOR PEERPEER REVIEWREVIEWis 3 mV, which is less than the 50% the value of LSB. During analysis of a 4 bit DAC based 1111 ofof 1616 on memristor technology, a sneak path problem was noticed, which will be explained in the following section.

FigureFigure 14. 14.14.Simulation SimulationSimulation of ofof a 4 aa bit 44 bitbit binary-weighted binary-weightedbinary-weighted DAC DACDAC cell. cell.cell.

FigureFigure 15. 15.15.INL INLINL simulation simulationsimulation for forfor a 4 aa bit 44 bit inputbit inputinput memristor-based memrismemristor-basedtor-based binary-weighted binary-weibinary-wei DACghtedghted circuit. DACDAC circuit.circuit. 4.4. Sneak Path Problem in a Binary-Weighted DAC-Based Memristor 4.4. Sneak Path Problem in a Binary-Weighted DAC-Based Memristor 4.4. SneakOne of Path the crucialProblem obstacles in a Binary-Weighted for an efﬁcient DAC-Based memristor crossbar Memristor array and a cascaded memristorOneOne ofof is thethe the crucialcrucial so-called obstaclesobstacles sneak path forfor currentanan efficientefficient problem. memristormemristor Some generalcrossbarcrossbar reviews arrayarray andand [21– 25aa cascaded]cascaded memristordealingmemristor with isis the thethe fundamental so-calledso-called sneaksneak mechanisms, pathpath currentcurrent materials, problem.problem. and SomeSome architectures generalgeneral ofreviewsreviews memristors [21–25][21–25] deal-deal- inghaveing withwith partially thethe fundamentalfundamental addressed the mechanisms,mechanisms, sneak path current materials,materials, problem andand and architecturesarchitectures its solutions. ofofFigure memristorsmemristors 16a havehave partiallyshowspartially the addressedaddressed crossbar array thethe thatsneaksneak includes pathpath current sneakcurrent path prproblemoblem issues, and whereasand itsits solutions.solutions. Figure 16b FigureFigure shows the16a16a showsshows equivalent circuit for this issue. Generally speaking, there are several recent types of thethe crossbarcrossbar arrayarray thatthat includesincludes sneaksneak pathpath issues,issues, whereaswhereas FigureFigure 16b16b showsshows thethe equiva-equiva- research that have proposed many solutions for this issue, such as the one transistor–one lent circuit for this issue. Generally speaking, there are several recent types of research memristorlent circuit model for this (1T1M) issue. (as Generally shown in Figurespeaking 17),, thethere one are diode–one several memristorrecent types model of research that(1D1M)that havehave (as proposedproposed shown in Figure manymany 18 solutionssolutions), and the forfor one thisthis selector–one issue,issue, suchsuch memristor asas thethe oneone model transistor–onetransistor–one (1S1M). In our memris-memris- torproposedtor modelmodel approach, (1T1M)(1T1M) (as(as the shownshown sneak path inin FigureFigure can occur 17),17), when thethe oneone these diode–onediode–one cells connected memristormemristor together modelmodel in a (1D1M)(1D1M) (ascascade(as shownshown to achieve inin FigureFigure DAC. 18),18), andand thethe oneone selector–oneselector–one memristormemristor modelmodel (1S1M).(1S1M). InIn ourour pro-pro- posedposed approach,approach, thethe sneaksneak pathpath cancan occuroccur whenwhen thesethese cellscells connectedconnected togethertogether inin aa cascadecascade toto achieveachieve DAC.DAC.

((aa)) ((bb)) FigureFigure 16.16. MemristorsMemristors structurestructure anandd equivalentequivalent circuitcircuit ((aa)) AA memristormemristor crossbarcrossbar array.array. ((bb)) TheThe sneaksneak pathpath problemproblem inin circuit.circuit.

Electronics 2021, 10, x FOR PEER REVIEW 11 of 16

Figure 14. Simulation of a 4 bit binary-weighted DAC cell.

Figure 15. INL simulation for a 4 bit input memristor-based binary-weighted DAC circuit.

4.4. Sneak Path Problem in a Binary-Weighted DAC-Based Memristor One of the crucial obstacles for an efficient memristor crossbar array and a cascaded memristor is the so-called sneak path current problem. Some general reviews [21–25] deal- ing with the fundamental mechanisms, materials, and architectures of memristors have partially addressed the sneak path current problem and its solutions. Figure 16a shows the crossbar array that includes sneak path issues, whereas Figure 16b shows the equivalent circuit for this issue. Generally speaking, there are several recent types of research that have proposed many solutions for this issue, such as the one transistor–one memristor model (1T1M) (as shown in Figure 17), the one diode–one memristor model (1D1M) Electronics 2021, 10, 622 (as shown in Figure 18), and the one selector–one memristor model (1S1M). In our pro-12 of 17 posed approach, the sneak path can occur when these cells connected together in a cascade to achieve DAC.

Electronics 2021, 10, x FOR PEER REVIEW 12 of 16

(a) (b) Electronics 2021, 10, x FOR PEER REVIEW 12 of 16 Electronics 2021, 10, x FOR PEERFigure REVIEW Figure16. Memristors 16. Memristors structure structure and equivalent and equivalent circuit circuit(a) A memristor (a) A memristor crossbar crossbar array. array.(b) The (b ) The12 sneak of 16

sneak pathpath problem problem in in circuit. circuit.

Figure 17. A schematic diagram of a one transistor–one memristor (1T1M) crossbar.

FigureFigure 17. A schematic 17. A schematic diagram diagram of a one of transistor–one a one transistor–one memristor memristor (1T1M) (1T1M) crossbar. crossbar. Figure 17. A schematic diagram of a one transistor–one memristor (1T1M) crossbar.

(a) (b) (a) (b) Figure 18. Memristors structure and equivalent(a) circuit with 1D1M solution (a) A structure(b) diagram of a oneFigure diode–oneFigure 18. Memristors memristor 18. Memristors structure (1D1M) structure and model equivalent and and equivalent (b circuit) the circuit equivalentwith 1D1M with1D1M circuitsolution solution 1D1M (a) A structure (solution.a) A structure dia- diagram gram ofFigure a one 18.diode–one Memristors memristor structure (1D1M) and equivalent model and circuit (b) the with equivalent 1D1M solution circuit 1D1M (a) A solution.structure dia- ofgram a one of diode–onea one diode–one memristor memristor (1D1M) (1D1M) model model and (b )and the ( equivalentb) the equivalent circuit 1D1Mcircuit solution.1D1M solution. In order to study a sneak path problem (as illustrated in Figure 19), the following In order to study a sneak path problem (as illustrated in Figure 19), the following binary pattern (1001) Inis applied. order to studyIt was a noticed sneak path that problem the current (as illustrated passes from in Figure 19to), the following binary patternIn order (1001) to is study applied. a sneak It was path noticed problem that the(as illustratedcurrent passes in Figure from 19), theto following binary pattern (1001) is applied. It was noticed that the current passes fromRm0 to Rm1 and and from to binary (which pattern are (1001) the rightis applied. direction It was of noticedthe current) that the affect current the functionalitypasses from to and fromfrom R toto R (which (which are are the theright right directiondirection of of thethe current)current)affect affect the the functionalityfunctionality of the and fromm3 m 2to (which are the right direction of the current) affect the functionality of the DAC. ofHowever, theDAC. DAC. However,the However, most thecritical the most most path critical critical (as path pathshown (as (as shown inshown Figure in in Figure Figure19a) 19 is a)19a) the is theisred the red path. red path. path. In In orderIn to of the DAC. However, the most critical path (as shown in Figure 19a) is the red path. In order to preventorder prevent theto prevent sneak the path sneakthe sneak from path path fromoccurring, from occurring, occurring, a switch a switch a hasswitch has been been has added addedbeen added betweenbetween between each each cell each of DAC, order to prevent the sneak path from occurring, a switch has been added between each cell of DAC, cellas illustrated ofas DAC, illustrated as inillustrated Figure in Figure 19b.in 19Figure b. 19b. cell of DAC, as illustrated in Figure 19b.

(a) (b) (a) (a) (b) (b) Figure 19. The sneak path issue and its solution in a memristor DAC. (a) A memristor DAC with a Figure 19. The sneak path issue and its solution in a memristor DAC. (a) A memristor DAC with a FigureFigure 19. The 19. sneak The pathsneak sneak issue path path and problem; issue its solution and (b) Aitsin memristor solution a memristor inDAC a DAC. memristor using (a )the A memristorsneak DAC. path (a) DAC solutionA memristor with (1D1M). a sneak DAC path with problem; a (b) sneak path problem; (b) A memristor DAC using the sneak path solution (1D1M). A memristorsneak DACpath usingproblem; the sneak (b) A path memristor solution DAC (1D1M). using the sneak path solution (1D1M). 5. Memristor DAC-Based Successive Approximation Register (SAR)-ADC 5. Memristor DAC-Based Successive Approximation Register (SAR)-ADC 5. Memristor DAC-BasedSuccessive Successiveapproximation Approximation register (SAR) is Register one of several (SAR)-ADC analog to digital converters Successive approximation register (SAR) is one of several analog to digital converters Successive(ADCs). approximation It is suitable registerfor medium-to-high-resolution (SAR) is one of several applications analog to anddigital provides converters low power dissipation.(ADCs). It requires It is suitable several for comparisonmedium-to-high-resolution cycles to complete applications one conversion, and provides and it there- low power (ADCs). It is suitable for medium-to-high-resolution applications and provides low power fore hasdissipation. limited operational It requires speed.several SAR comparison architectures cycles are to completeextensively one used conversion, in low power and it there- dissipation. Itand requires lowfore speed hasseveral limited applications. comparison operational Most cy speed.ofcles the to poweSAR complete archr dissipationitectures one conversion, areis due extensively to theand digital itused there- incontrol low power fore has limitedcircuit, operationaland the lowcapacitive speed speed. referenceapplications. SAR archDAC Mostitectures network, of the areand powe extensively ther comparator.dissipation used isIn in duerecent low to CMOSthepower digital tech- control and low speednology, applications.circuit, the digital the capacitive controlMost of circuits referencethe powe consume DACr dissipation lessnetwork, power andis [26]. due the In comparator.to SAR-ADC, the digital thereIn recentcontrol is no CMOS com- tech- circuit, the capacitiveponentnology, that reference consumes the digital DAC static control network, power circuits (except and consume the fo rcomparator. the less pre-amplifier, power In[26]. recent Inwhich SAR-ADC, CMOS can be tech- there replaced is no com- nology, the digitalby chargingponent control the that circuits steering consumes consume amplifier static lessto power cancel power (except this [26]. type fo In rof theSAR-ADC, power pre-amplifier, dissipation) there which is [27]. no com- canThe becom- replaced ponent that consumesby charging static powerthe steering (except amplifier for the to cancelpre-amplifier, this type ofwhich power can dissipation) be replaced [27]. The com- by charging the steering amplifier to cancel this type of power dissipation) [27]. The com-

Electronics 2021, 10, 622 13 of 17

5. Memristor DAC-Based Successive Approximation Register (SAR)-ADC Successive approximation register (SAR) is one of several analog to digital converters (ADCs). It is suitable for medium-to-high-resolution applications and provides low power dissipation. It requires several comparison cycles to complete one conversion, and it Electronics 2021, 10, x FOR PEER REVIEWtherefore has limited operational speed. SAR architectures are extensively used in low 13 of 16 power and low speed applications. Most of the power dissipation is due to the digital control circuit, the capacitive reference DAC network, and the comparator. In recent CMOS technology, the digital control circuits consume less power [26]. In SAR-ADC, there is noparator component and thatcapacitor consumes network static powerare the (except SAR-AD for theC components pre-ampliﬁer, whichthat consume can be the most dy- replaced by charging the steering ampliﬁer to cancel this type of power dissipation) [27]. Thenamic comparator power. and Several capacitor methods network have are the been SAR-ADC proposed components in recent that research consume theto tackle this issue mostby reducing dynamic power. the switching Several methods energy have beenby more proposed than in recent50% research. Figure to 20 tackle shows this the proposed issuememristor-based by reducing the successive switching energy approximation by more than regi 50%.ster. Figure The 20 capacitor-switchingshows the proposed network has memristor-basedbeen replaced successiveby a memristor approximation DAC register.network The to capacitor-switching reduce the area networkand the hasswitching energy. been replaced by a memristor DAC network to reduce the area and the switching energy. Figure 21 shows the memristor DAC deployed in the proposed SAR-ADC. This proposed Figure 21 shows the memristor DAC deployed in the proposed SAR-ADC. This proposed designdesign also also deployed deployed a sneak a sneak path solution. path solution.

FigureFigure 20. 20.The The proposed proposed successive successive approximation approximation register (SAR)-analog register (SAR)-analog to digital converter to (ADC)digital converter using(ADC) memeristor using memeristor DAC. DAC.

Figure 21. Proposed memristor DAC for the successive approximation register (SAR)-ADC.

Electronics 2021, 10, x FOR PEER REVIEW 13 of 16

parator and capacitor network are the SAR-ADC components that consume the most dynamic power. Several methods have been proposed in recent research to tackle this issue by reducing the switching energy by more than 50%. Figure 20 shows the proposed memristor-based successive approximation register. The capacitor-switching network has been replaced by a memristor DAC network to reduce the area and the switching energy. Figure 21 shows the memristor DAC deployed in the proposed SAR-ADC. This proposed design also deployed a sneak path solution.

Electronics 2021, 10, 622 14 of 17 Figure 20. The proposed successive approximation register (SAR)-analog to digital converter (ADC) using memeristor DAC.

FigureFigure 21.21.Proposed Proposedmemristor memristor DACDAC forfor thethe successivesuccessive approximationapproximation register register (SAR)-ADC. (SAR)-ADC.

Performance of the Proposed SAR-ADC Memristor-Based Circuit The proposed design has been simulated using a 65 nm CMOS process and a memristor model using the cadence EDA tool. The input signal for ADC was selected to be 2 kHz, with an input range of 1.2 V peak to peak, a common mode voltage of 0.6V, and a sampling frequency of 1 MHz. To compare the proposed design performance with other ADCs, we used a ﬁgure of merit (FoM) expression as follows:

Power = FoM ENOB (7) Fs.2

where Fs is the sampling frequencyand ENOB is the effective number of bits (which is SNDR−1.76 ( 6.02 )). This figure of merit focuses on three vital metrics in ADC: power, Fs, and ENOB, with the lowest FoM signaling a better performance. Figure 22 shows the fast Fourier transform FFT of the proposed SAR-ADC model that achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB. Table4 shows the performance of ADC using a power supply of 1.2 V. This design has dissipated by 21 µW, which is a very low level of power consumption. Moreover, it achieves a low figure of merit (87.9 fJ/Conv.-step). The power consumption is, significantly, very low due to the low power consumption of memristors. Electronics 2021, 10, x FOR PEER REVIEW 14 of 16

Performance of the Proposed SAR-ADC Memristor-Based Circuit The proposed design has been simulated using a 65 nm CMOS process and a memristor model using the cadence EDA tool. The input signal for ADC was selected to be 2 kHz, with an input range of 1.2 V peak to peak, a common mode voltage of 0.6V, and a sampling frequency of 1 MHz. To compare the proposed design performance with other ADCs, we used a figure of merit (FoM) expression as follows: = (7) .2

where is the sampling frequencyand ENOB is the effective number of bits (which is . ( )). This figure of merit focuses on three vital metrics in ADC: power, , and . ENOB, with the lowest FoM signaling a better performance. Figure 22 shows the fast Fou- rier transform FFT of the proposed SAR-ADC model that achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB. Table 4 shows the performance of ADC using a power supply of 1.2 V. This design has dissipated by 21 µW, which is a very low level of power consumption. Moreover, it achieves a low figure of merit (87.9 fJ/Conv.-step). The power consumption is, significantly, very low due to the low power consumption of memristors.

Table 4. Performance summary and comparison with state-of-the-art SAR-ADCs.

Reference JSSC’11 [28] VSLI’13 [29] CASI’16 [30] IEEEAccsss’20 [31] IEEETrans.’15 [32] This Work Technology 130 nm 90 nm 180 nm 90 nm 130 nm 65 nm Supply Voltage (V) 1.2 1 1.8 1.2 1.2 1.2 Sampling Frequency (MHz) 40 30 10 50 0.072 1 SNDR (dB) 50.6 56.8 66.9 57.6 82.9 49.3 SFDR (dB) — 68.6 75.8 68.8 96.8 61 ENOB (bit) 8.26 9.16 10.82 9.26 13.5 7.9 ElectronicsPower2021, 10 (uW), 622 550 980 820 664 130 2115 of 17 FoM (fJ/Conv.-step) 50 57 44.2 21.68 156 89

FigureFigure 22. 22. TheThe fast fast Fourier Fourier transform (FFT) (FFT) of of the the proposed proposed SAR-ADC. SAR-ADC.

Table 4. Performance summary and comparison with state-of-the-art SAR-ADCs.

Reference JSSC’11 [28] VSLI’13 [29] CASI’16 [30] IEEEAccsss’20 [31] IEEETrans.’15 [32] This Work Technology 130 nm 90 nm 180 nm 90 nm 130 nm 65 nm Supply Voltage (V) 1.2 1 1.8 1.2 1.2 1.2 Sampling 40 30 10 50 0.072 1 Frequency (MHz) SNDR (dB) 50.6 56.8 66.9 57.6 82.9 49.3 SFDR (dB) — 68.6 75.8 68.8 96.8 61 ENOB (bit) 8.26 9.16 10.82 9.26 13.5 7.9 Power (uW) 550 980 820 664 130 21 FoM 50 57 44.2 21.68 156 89 (fJ/Conv.-step)

6. Proposed Memristor DAC Comparison There are few papers have been published on the binary-weighted memristor DAC. Consequently, the parameter for comparison among these proposed memristor DACs is area, in terms of the number of memristors used to achieve the specific DAC. Most of this research focuses on the binary-weighted resistor design technique (which requires a larger number of memristor elements to achieve; in other words, it is difficult to extend to high-resolution DAC due to the limitation of the memristor’s properties in implementing a larger memristor element). In this work, the proposed memristor binary-weighted DAC reduced the memristor element required, as shown in Table5. Moreover, it can be extended to high-resolution DAC without being limited by the memristor’s properties. It is clear from Table5 that the proposed DAC in [ 5] and [6] used a larger number of memristors and is limited in terms of extended resolutions, while the proposed DAC in [13] has the flexibility to increase DAC resolution. However, it required more transistors (at least one transistor for each extra bit (since the transistor area is larger than the memristor area)). Consequently, the proposed DAC has reduced the area by 40%, as shown in Table5. Moreover, it can be extended to the n bit of DAC. Electronics 2021, 10, 622 16 of 17

Table 5. Comparison between the proposed binary-weighted memristor DAC and the results of recent research.

Item IEEE 2017 [5] IEEE 2013/ACM [6] IEEE 2016/ICMM [9] This Work Binary-weighted Binary-weighted Current steering Cascaded Cascaded Topology memristor memristor memristor memristor memristor DAC Resolutions 4 bit 6 bit 2 bit 4 bit 8 bit Number of 15 63 2 * 9 21 memristors used Flexibility to increase DAC Limited Limited Flexible Flexible Flexible Resolution * Two memristors have been used alongside ﬁve transistors, one resistor, and one buffer.

7. Conclusions In this paper, 4 bit and 8 bit memristor DACs were proposed using two memristor- based DAC cells. The VTEAM memristor model was employed (with optimized parameters) to simulate the proposed DAC. The sneak path problem in 4 bit and 8 bit DAC has been resolved through use of the 1D1M solution. The proposed DAC achieved 3 mV, which is less than 50% of LSB and the area was reduced by 40% as compared to recent memristor DAC architectures. Moreover, a SAR-ADC model was designed based on the proposed 8 bit memristor DAC. It achieved SNDR 49.3 dB and SFDR 61 dB, with a power supply of 1.2 V and a dissipation of 21 µW. The SAR-ADC realized a ﬁgure of merit (FoM) of 87.9 fJ/Conv.-step. The comparison between proposed 4 bit and 8 bit DAC and others memristor DAC [5,6,9] showed that highlighted low area and high resolution were achieved.

Author Contributions: All authors have equally participated in contributions to this research article, either in terms of the concept, methodology or validation phases of the proposed protocol. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Chua, L. Memristor-The missing circuit element. IEEE Trans. Circuit Theory 1971, 18, 507–519. [CrossRef] 2. Strukov, D.B.; Snider, G.S.; Stewart, D.R.; Williams, R.S. The missing memristor found. Nature 2008, 453, 80–83. [CrossRef] [PubMed] 3. Marani, R.; Gelao, G.; Perri, A.G. A review on memristor applications. arXiv 2015, arXiv:1506.06899. 4. van de Plassche, R.J. CMOS Integrated Analog-to-Digital and Digital to—Analog Converters; Springer Science and Business Media: Berlin/Heidelberg, Germany, 2013. 5. Khalid, M. Review on Various Memristor Models, Characteristics, Potential Applications, and Future Works. Trans. Electr. Electron. Mater. 2019, 20, 289–298. [CrossRef] 6. Danial, L.; Wainstein, N.; Kraus, S.; Kvatinsky, S. DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors. IEEE J. Emerg. Sel. Top. Circuits Syst. 2017, 8, 146–158. [CrossRef] 7. Gao, L.; Merrikh-Bayat, F.; Alibart, F.; Guo, X.; Hoskins, B.D.; Cheng, K.-T.; Strukov, D.B. Digital-to- Analog and Analog-to-Digital Conversion with Metal Oxide Memristors for Ultra-Low Power Computing. In Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Brooklyn, NY, USA, 15–17 July 2013. 8. Cai, F.; Correll, J.M.; Lee, S.H.; Lim, Y.; Bothra, V.; Zhang, Z.; Flynn, M.P.; Lu, W.D. A fully integrated reprogrammable memristor–CMOS system for efﬁcient multiply–accumulate operations. Nat. Electron. 2019, 2, 290–299. [CrossRef] 9. Dakheel, M.M.; Hassanein, A.M.; Fouad, R.A.; Radwan, A.G. Memristor-based data converter circuits. In Proceedings of the 2016 28th International Conference on Microelectronics (ICM), Giza, Egypt, 17–20 December 2016. 10. Du, L.; Li, Y. A/D converter architectures for energy-efﬁcient vision processor. arXiv 2017, arXiv:1703.01681. 11. Mirzaie, N.; Alzahmi, A.; Shamsi, H.; Byun, G.Y. Three-Dimensional Pipeline ADC Utilizing TSV/Design Optimization and Memristor Ratioed Logic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 26, 2619–2627. [CrossRef] 12. Kvatinsky, S.; Satat, G.; Wald, N.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. Memristor-based material implication (IMPLY) logic:Design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2014, 22, 2054–2066. [CrossRef] Electronics 2021, 10, 622 17 of 17

13. Saremi, M. Modeling and Simulation of the Programmable Metallizationcells (PMCs) and Diamond-Based Power Devices. Ph.D. Thesis, Arizona State University, Tempe, AZ, USA, 2017. 14. Humood1, K.; Mohammad1, B.; Abunahla1, H.; Azzam, A. On-chip tunable Memristor-based flash-ADC converter forartificial intelligence applications. IET Circuits Devices Syst. 2019, 14, 107–114. [CrossRef] 15. Zidana, M.A.; Fahmyb, H.A.H.; Hussaina, M.M.; Salamaa, K.N. Memristor-based Memory: The Sneak Paths Problem and Solutions. Microelectron. J. 2013, 44, 176–183. [CrossRef] 16. Gül, F. Addressing the sneak-path problem in crossbar RRAM devices using memristor-based one Schottky diode-one resistor array. Results Phys. 2019, 12, 1091–1096. [CrossRef] 17. Kvatinsky, S.; Ramadan, M.; Friedman, E.G.; Kolodny, A. VTEAM: A General Model for Voltage-Controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 786–790. [CrossRef] 18. Lehtonen, E.; Laiho, M. Stateful Implication Logic with Memristors. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, San Francisco, CA, USA, 30–31 July 2009; pp. 33–36. 19. Kvatinsky, S.; Belousov, D.; Liman, S.; Satat, G.; Wald, N.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. MAGIC–memristor aided LoGIC. IEEE Trans. Circuits Syst. II Express Briefs 2014, 61, 895–899. [CrossRef] 20. Kvatinsky, S.; Wald, N.; Satat, G.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. MRL-Memristor Ratioed Logic. In Proceedings of the 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, Turin, Italy, 29–31 August 2012; pp. 1–6. 21. Hudec, B.; Hsu, C.W.; Wang, I.T.; Lai, W.L.; Chang, C.C.; Wang, T.; Fröhlich, K.; Ho, C.-H.; Lin, C.-H.; Hou, T.-H. 3D resistive RAM cell design for high-density storage class memory—A review. Sci. China Inf. Sci. 2016, 59, 061403. [CrossRef] 22. Gi, S.; Yeo, I.; Chu, M.; Kim, S.; Lee, B. Fundamental issues of implementing hardware neural networks using memristor. In Proceedings of the 2015 International SoC Design Conference (ISOCC), Gyeongju, Korea, 2–5 November 2015. 23. Pan, F.; Gao, S.; Chen, C.; Song, C.; Zeng, F. Recent progress in resistive random access memories: Materials, switching mechanisms, and performance. Mater. Sci. Eng. R Rep. 2014, 83, 1–59. [CrossRef] 24. Seok, J.Y.; Song, S.J.; Yoon, J.H.; Yoon, K.J.; Park, T.H.; Kwon, D.E.; Lim, H.; Kim, G.H.; Jeong, D.S.; Hwang, C.S. A review of three-dimensional resistive switching cross-bar array memories from the integration and materials property points of view. Adv. Funct. Mater. 2014, 24, 5316–5339. [CrossRef] 25. Shi, L.; Zheng, G.; Tian, B.; Dkhil, B.; Duan, C. Research progress on solutions to the sneak path issue in memristor crossbar arrays. Nanoscale Adv. 2020, 2, 1811–1827. [CrossRef] 26. Liu, C.; Chang, S.; Huang, G.; Lin, Y. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE J. Solid-State Circuits 2010, 45, 731–740. [CrossRef] 27. Fahmy, G.A. A 6.25GHz, 2.7_w at 0.5V, double-tail comparator using charge-steering approach. In Proceedings of the 2018 35th National Radio Science Conference (NRSC), Cairo, Egypt, 20–22 March 2018; pp. 377–384. 28. ChoS, H.; Lee, C.K.; Kwon, J.K.A. A 550µW 10b 40MS/s SAR ADC with multistep additiononly digital error correction. In Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 1 November 2010; pp. 1–4. 29. Huang, G.; Chang, S.; Liu, C.; Lin, Y. 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2013, 21, 584–588. [CrossRef] 30. Liu, S.; Shen, Y.; Zhu, Z. A 12-Bit 10 MS/s SAR ADC with High Linearity and Energy-Efficient Switching. IEEE Trans. Circuits Syst. I Regul. Pap. 2016, 63, 1616–1627. [CrossRef] 31. Lu, C.; Huang, D. A 10-Bits 50-MS/s SAR ADC Based on Area- Efficient and Low-Energy Switching Scheme. IEEE Access 2020, 8, 28257–28266. [CrossRef] 32. Fateh, S.; Schonle, P.; Bettini, L.; Rovere, G.; Benini, L.; Huang, Q. A reconfigurable 5-to-14 bit SAR ADC for battery-powered medical instrumentation. IEEE Trans. Circuits Syst. I Regul. Pap. 2015, 62, 2685–2694. [CrossRef]