A RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications

Total Page:16

File Type:pdf, Size:1020Kb

A RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications micromachines Article A RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications Xiaoyong Xue 1, Chenzedai Wang 1, Wenjun Liu 1,*, Hangbing Lv 2,*, Mingyu Wang 1,* and Xiaoyang Zeng 1 1 State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China 2 Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China * Correspondence: [email protected] (W.L.); [email protected] (H.L.); [email protected] (M.W.); Tel.: +86-021-51355200-987 (W.L.) Received: 31 May 2019; Accepted: 16 August 2019; Published: 16 August 2019 Abstract: Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes a RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, a RISC-V processor with area-efficient memristor-based IMC was developed based on an open-source core for IoT applications, Hummingbird E200. The general compiling policy with the data allocation method is also disclosed for the IMC implementation of the Keccak hash algorithm. An evaluation shows that >70% improvements in both performance and energy saving were achieved with limited area overhead after introducing IMC in the RISC-V processor. Keywords: in-memory computing; memristor; RISC-V; Internet of things; blockchain 1. Introduction Internet of things (IoT) refers to the network of different physical devices, which enables them to collect and exchange data [1,2]. With the development of telecommunication, computers, and integrated circuits, IoT is being increasingly applied in commercial fields such as modern agriculture, driverless vehicles, smart cities, etc., which promise to become vital parts of global economics [3]. However, as billions of IoT devices are connected to the continuously growing networks, security appears to be a major concern. IoT devices collect a great amount of private information, which is vulnerable to attacks if not well protected. Moreover, most of the devices are resource-constrained and, thus, heavy cryptographic approaches are difficult to implement. Recently, a trend emerged to exploit the blockchain technology in IoT devices for information security and data integrity [4]. The blockchain is a peer-to-peer (P2P) ledger which was first used in the Bitcoin cryptocurrency for economic transactions [5]. Bitcoin users that are known by a changeable public key generate and broadcast transactions to the network to transfer money. These transactions are pushed into a block by users. Once a block is full, the block is appended to the blockchain by performing a mining process. To mine a block, some specific nodes known as miners try to solve a cryptographic puzzle named proof of work (POW), and the node that solves the puzzle first mines the new block to the blockchain, as shown in Figure1. Because of its distributed, secure, and private nature, the blockchain can enable secure messaging between devices in an IoT network. In this approach, the Micromachines 2019, 10, 541; doi:10.3390/mi10080541 www.mdpi.com/journal/micromachines Micromachines 2019,, 10,, 541x FOR PEER REVIEW 22 of of 1615 and private nature, the blockchain can enable secure messaging between devices in an IoT network. blockchainIn this approach, treats messagethe blockchain exchanges treat betweens message devices exchanges similar between to financial devices transactions similar to in afinancial Bitcoin network.transactions To enablein a Bitcoin message network exchanges,. To enable devices message leverage exchanges, smart contracts devices which leverage model smart the agreement contracts betweenwhich model two the parties. agreement The distributed between two datasets parties maintained. The distributed by blockchain datasets technologymaintained alsoby blockchain allow the datatechnology to be safely also allow stored the by data different to be peers, safely and stored people by different are not required peers, and to entrustpeople are IoT not data required produced to byentrust their IoT devices data toproduced centralized by their companies devices [6 to]. Moreover,centralized the companies blockchain [6]. technology Moreover, lowersthe blockchain the cost oftechnology the deployment lowers the of the cost IoT of devicesthe deployment and makes of the it safe IoT anddevices easy and for usersmakes to it paysafefor and the easy data for on users IoT devicesto pay for [7 ].the data on IoT devices [7]. Take hash of Verify Bundle previous block transactions are transactions in a and insert it into valid block new block When solution is Propagate Solve proof of found, add new blockchain to work block to network blockchain Figure 1. BitcoinBitcoin mining mining process using blockchain technology technology.. However, the the hardware hardware for for mining mining in IoT in IoTdevices devices has to has be tolightweight, be lightweight, low-cost low-cost,, and energy and- energy-eefficient toffi cientadapt to the adapt block thechain blockchain technology technology.. IoT devices IoT are devices often deployed are often in deployed nonhuman in nonhuman conditions conditionsto a great extent to a great and extentare powered and are through powered batteries, through call batteries,ing for extremely calling for low extremely cost and low low cost energy and lowconsumption energy consumption [8]. However, [8]. when However, using when a general using processor a general, processor,i.e., central i.e., processing central processing unit (CPU unit) or (CPU)graphics or processing graphics processing unit (GPU) unit, to implement (GPU), to implementthe blockchain, the it blockchain, is likely to consume it is likely too to much consume energy, too muchresulting energy, in frequent resulting recharging in frequent orrecharging a short battery or a shortlifetime. battery Resorting lifetime. to a Resorting conventional to a conventional application- application-specificspecific integrated circuit integrated (ASIC circuit) or coprocessor (ASIC) or can coprocessor help to reduce can help energy to reduce consumption energy consumptionand improve andspeed, improve but will speed, induce but considerable will induce considerablearea cost [9]. area cost [9]. In-memoryIn-memory computing (IMC) provides a promising alternative. In a general processor, the data transfer on the bus between the central processing unit (CPU) and the memory leads to large power consumption and limited performance,performance, i.e.,i.e., memory bottleneck.bottleneck. To address this issue, IMC modifiesmodifies the memory to be able to perform some regular logic operations such as AND, OR,OR, and exclusive or (XOR)(XOR) [[9].9]. Especially for data vectors with l largearge bit width, IMC can accomplish the ANDAND/OR/XOR/OR/XOR operation inin oneone read read access, access, saving saving both both execution execution time time and and power power consumption. consumption. Static Static random-access random- memoryaccess memor (SRAM)y (SRAM) can be employedcan be employed in IMC, butin IMC, its cell but size its iscell too size large is withtoo large 6–10 transistorswith 6–10 transistors and it also needsand it also constant needs power constant to hold power the to data, hold incurring the data, incurring considerable considerable area cost andarea standby cost and power standby [10 power]. [10]. Emerging memory technologies, especially memristors, feature a simple cell structure, highEmerging density, memory three-dimensional technologies, (3D) especially stackability, memristor goods, compatibilityfeature a simple with cell complementarystructure, high metal–oxide–semiconductordensity, three-dimensional (3D (CMOS)) stackability, processes, good and compatibility non-volatility with [11 complementary]. Recently, memristors metal–oxide were– investigatedsemiconductor to (CMOS realize) IMCprocess usinges, and a one-transistor-one-memristor non-volatility [11]. Recently, memristor (1T1R) arrays were accompanied investigated byto modifiedrealize IMC peripheral using a one circuits-transistor [12].- However,one-memristor it is still (1T1R) diffi cultarray to accompanied rely on memristor-based by modified IMCperipheral alone tocircuits implement [12]. However, the hash it algorithm is still difficult in blockchain to rely on technology. memristor- Abased processor IMC alone is still to requiredimplement to performthe hash thealgorithm data allocation, in blockchain as well technology. as other complexed A processor logic is operations.still required For to resource-limited perform the data IoT allocation devices,, the as processorwell as other should complexed be flexible logic to supportoperations memory. For resource computation-limited instructions IoT devices, while the incurring processor small should power be consumptionflexible to support and area memory cost. Thankscomputation to its simplicity,instructions scalability, while incurring fast speed, small and power low power,consumption the RISC-V and processorarea cost. isThanks believed to its to besimplicity, competent scalability, for the abovementioned
Recommended publications
  • Memristor-The Future of Artificial Intelligence L.Kavinmathi, C.Gayathri, K.Kumutha Priya
    International Journal of Scientific & Engineering Research, Volume 5, Issue 4, April-2014 358 ISSN 2229-5518 Memristor-The Future of Artificial Intelligence L.kavinmathi, C.Gayathri, K.Kumutha priya Abstract- Due to increasing demand on miniaturization and low power consumption, Memristor came into existence. Our design exploration is Reconfigurable Threshold Logic Gates based Programmable Analog Circuits using Memristor. Thus a variety of linearly separable and non- linearly separable logic functions such as AND, OR, NAND, NOR, XOR, XNOR have been realized using Threshold logic gate using Memristor. The functionality can be changed between these operations just by varying the resistance of the Memristor. Based on this Reconfigurable TLG, various Programmable Analog circuits can be built using Memristor. As an example of our approach, we have built Programmable analog Gain amplifier demonstrating Memristor-based programming of Threshold, Gain and Frequency. As our idea consisting of Programmable circuit design, in which low voltages are applied to Memristor during their operation as analog circuit element and high voltages are used to program the Memristor’s states. In these circuits the role of memristor is played by Memristor Emulator developed by us using FPGA. Reconfigurable is the option we are providing with the present system, so that the resistance ranges are varied by preprogram too. Index Terms— Memristor, TLG-threshold logic gates, Programmable Analog Circuits, FPGA-field programmable gate array, MTL- memristor threshold logic, CTL-capacitor Threshold logic, LUT- look up table. —————————— ( —————————— 1 INTRODUCTION CCORDING to Chua’s [founder of Memristor] definition, 9444163588. E-mail: [email protected] the internal state of an ideal Memristor depends on the • L.kavinmathi is currently pursuing bachelors degree program in electronics A and communication engineering in tagore engineering college under Anna integral of the voltage or current over time.
    [Show full text]
  • Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL †
    electronics Article Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL † Khaled Alhaj Ali 1,* , Mostafa Rizk 1,2,3 , Amer Baghdadi 1 , Jean-Philippe Diguet 4 and Jalal Jomaah 3 1 IMT Atlantique, Lab-STICC CNRS, UMR, 29238 Brest, France; [email protected] (M.R.); [email protected] (A.B.) 2 Lebanese International University, School of Engineering, Block F 146404 Mazraa, Beirut 146404, Lebanon 3 Faculty of Sciences, Lebanese University, Beirut 6573, Lebanon; [email protected] 4 IRL CROSSING CNRS, Adelaide 5005, Australia; [email protected] * Correspondence: [email protected] † This paper is an extended version of our paper published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 27–29 November 2019, as Ali, K.A.; Rizk, M.; Baghdadi, A.; Diguet, J.P.; Jomaah, J. “MRL Crossbar-Based Full Adder Design”. Abstract: A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder.
    [Show full text]
  • The Memristor: Anew Bond Graph Element D
    Paper No. n-Aut·N J The Society shall not be responsible for statements or opinions :<;111 pnp~,r~ or, in'Ldisao~slofl at me~,~in~s~f t~~ <~~,~iety, o,~, ot ,.its (I',~l)o'isjons:"or S,ecti ons;) lor- prlrU9d;:)ln tts j:~obllcaJLors. G. F.OSTER The Memristor: ANew Bond Graph Element D. M. AUSLANDER Mechanical Engineering Department. The "mcmris[.or," first deft ned by L. Clma for electrical drwits, 1·$ proposed as a new University of California, Berkeley, bond gra,ph clemel/t, on (1.11- equul footiug with R, L, & C, and having some unique Calif. modelling capubilities for nontinear systems. The Missing Constitutive Relation circuit thcory; howevcr, if wc look beyond the electrical doma.in it is not hard 1.0 find systems whose characteristics are con­ Ix HIS original lecture notes int.roducing the bond veniently represented by a memristor modcl. graph technique, Paynter drew a 1I1ctrahedron of state," (Fig. I) which sumnHlrir.cd j.he relationship between the sl.ate vl~riables Properties (c, I, p, q) [I, 2].1 There are G binary relationships possible be­ tween these 4 state variableii, Two of these are definitions: the The constitutive relation for a I-port memristor is a curve in the q-p ph~ne, Fig. 2. [n this context, we do not necessarily in_ displacement., q(t) = q(O) + f(t)clJ, and the qU:l.utit,y pet) = J:' terpret the quant.it,y p(l) = p(O) + ]:' e(t)dt as momentum, magneti(~ p(O) + }:' c(l)dt, which is interpreted ns momentum, flux, or pressure-momentum (2), buti merely as t.he integrated etTol't ("impulse!».
    [Show full text]
  • Memristor Nanodevice for Unconventional Computing:Review and Applications Mahyar Shahsavari, Pierre Boulet
    Memristor nanodevice for unconventional computing:review and applications Mahyar Shahsavari, Pierre Boulet To cite this version: Mahyar Shahsavari, Pierre Boulet. Memristor nanodevice for unconventional computing:review and applications . [Research Report] Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189. 2016. hal-01480614 HAL Id: hal-01480614 https://hal.archives-ouvertes.fr/hal-01480614 Submitted on 1 Mar 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Memristor nanodevice for unconventional computing: review and applications Mahyar Shahsavari, Pierre Boulet Univ. Lille, CNRS, Centrale Lille, UMR 9189 - CRIStAL Centre de Recherche en Informatique Signal et Automatique de Lille, F-59000 Lille, France. Abstract A memristor is a two-terminal nanodevice that its properties attract a wide community of re- searchers from various domains such as physics, chemistry, electronics, computer and neuroscience. The simple structure for manufacturing, small scalability, nonvolatility and potential of using in low power platforms are outstanding characteristics of this emerging nanodevice. In this report, we review a brief literature of memristor from mathematic model to the physical realization. We discuss different classes of memristors based on the material used for its manufacturing. The potential applications of memristor are presented and a wide domain of applications are explained and classified.
    [Show full text]
  • The Roadmap to Realize Memristive Three- Dimensional Neuromorphic Computing System
    We are IntechOpen, the world’s leading publisher of Open Access books Built by scientists, for scientists 4,800 122,000 135M Open access books available International authors and editors Downloads Our authors are among the 154 TOP 1% 12.2% Countries delivered to most cited scientists Contributors from top 500 universities Selection of our books indexed in the Book Citation Index in Web of Science™ Core Collection (BKCI) Interested in publishing with us? Contact [email protected] Numbers displayed above are based on latest data collected. For more information visit www.intechopen.com Chapter 2 The Roadmap to Realize Memristive Three- Dimensional Neuromorphic Computing System HongyuHongyu An, An, KangjunKangjun Bai Bai and Yang YiYang Yi Additional information is available at the end of the chapter http://dx.doi.org/10.5772/intechopen.78986 Abstract Neuromorphic computing, an emerging non-von Neumann computing mimicking the physical structure and signal processing technique of mammalian brains, potentially achieves the same level of computing and power efficiencies of mammalian brains. This chapter will discuss the state-of-the-art research trend on neuromorphic computing with memristors as electronic synapses. Furthermore, a novel three-dimensional (3D) neuro- morphic computing architecture combining memristor and monolithic 3D integration technology would be introduced; such computing architecture has capabilities to reduce the system power consumption, provide high connectivity, resolve the routing congestion issues, and offer the massively parallel data processing. Moreover, the design methodology of applying the capacitance formed by the through-silicon vias (TSVs) to generate a mem- brane potential in 3D neuromorphic computing system would be discussed in this chapter.
    [Show full text]
  • Memristor Devices: Fabrication, Characterization, Simulation
    MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Thesis Submitted to The School of Engineering of the UNIVERSITY OF DAYTON In Partial Fulfillment of the Requirements for The Degree of Master of Science in Electrical Engineering By Chris Yakopcic Dayton, Ohio August, 2011 MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Name: Yakopcic, Chris APPROVED BY: _________________________________ _________________________________ Tarek M. Taha, Ph.D. Guru Subramanyam, Ph.D. Advisory Committee Chairman Committee Member Associate Professor Chair and Professor Electrical and Computer Engineering Electrical and Computer Engineering _________________________________ Andrew Sarangan, Ph.D. Committee Member Associate Professor Electro-Optics _________________________________ _________________________________ John G. Weber, Ph.D. Tony E. Saliba, Ph.D. Associate Dean Dean, School of Engineering School of Engineering & Wilke Distinguished Professor ii ©Copyright by Chris Yakopcic All Rights Reserved 2011 iii ABSTRACT MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Name: Yakopcic, Chris University of Dayton Advisor: Dr. Tarek M. Taha Significant interest has been placed on developing systems based on memristors since the initial fabrication by HP Labs in 2008 [1]. The memristor is a nanoscale device with dynamic resistance that is able to retain the last programmed resistance value after power is removed from the device. This property shows that the memristor can be used as a non-volatile memory component, and has potential to enhance many types of systems, such as high density memory, and neuromorphic computing architectures. This thesis presents the fabrication and characterization results obtained based memristor devices developed at the University of Dayton. In addition, a comparison between the existing memristor device models was completed to show how the memristor can be used in a multistate operation.
    [Show full text]
  • CMOS and Memristor Technologies for Neuromorphic Computing Applications
    CMOS and Memristor Technologies for Neuromorphic Computing Applications Jeff Sun Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2015-219 http://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-219.html December 1, 2015 Copyright © 2015, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. CMOS and Memristor Technologies for Neuromorphic Computing Applications by Jeff K.Y. Sun Research Project Submitted to the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, in partial satisfaction of the requirements for the degree of Master of Science, Plan II. Approval for the Report and Comprehensive Examination: Committee: Professor Tsu-Jae King Liu Research Advisor (Date) * * * * * * * Professor Vladimir Stojanovic Second Reader (Date) Abstract In this work, I present a CMOS implementation of a neuromorphic system that aims to mimic the behavior of biological neurons and synapses in the human brain. The synapse is modeled with a memristor-resistor voltage divider, while the neuron-emulating circuit (“CMOS Neuron”) comprises transistors and capacitors. The input aggregation and output firing characteristics of a CMOS Neuron are based on observations from studies in neuroscience, and achieved using both analog and digital circuit design principles.
    [Show full text]
  • Synaptic Iontronic Devices for Brain-Mimicking Functions: Fundamentals and Applications ∥ ∥ Changwei Li, Tianyi Xiong, Ping Yu,* Junjie Fei,* and Lanqun Mao
    www.acsabm.org Review Synaptic Iontronic Devices for Brain-Mimicking Functions: Fundamentals and Applications ∥ ∥ Changwei Li, Tianyi Xiong, Ping Yu,* Junjie Fei,* and Lanqun Mao Cite This: ACS Appl. Bio Mater. 2021, 4, 71−84 Read Online ACCESS Metrics & More Article Recommendations ABSTRACT: Inspired by the information transmission mechanism in the central nervous systems of life, synapse-mimicking devices have been designed and fabricated for the purpose of breaking the bottleneck of von Neumann architecture and realizing the construction of effective hardware-based artificial intelligence. In this case, synaptic iontronic devices, dealing with current information with ions instead of electrons, have attracted enormous scientific interests owing to their unique characteristics provided by ions, such as the designability of charge carriers and the diversity of chemical regulation. Herein, the basic conception, working mechanism, performance metrics, and advanced applications of synaptic iontronic devices based on three-terminal transistors and two-terminal memristors are systematically reviewed and comprehensively discussed. This Review provides a prospect on how to realize artificial synaptic functions based on the regulation of ions and raises a series of further challenges unsolved in this area. KEYWORDS: iontronics, memristor, transistor, artificial synapse, neuromorphic device 1. INTRODUCTION numerous regulation strategies including charge transport,21 22 ff Inspired by the synapse structure in the nervous system noncovalent interactions, and so on. (3) The di erent carrying almost all intelligent characteristics of life in a tiny structure of ions provided them diversity in valencies, sizes, 1 and polarizabilities, and as a result, ion current carries more volume with low energy consumption, research attention has 23 been paid to the fabrication of synapse-mimicking devices for information when compared with electronic current.
    [Show full text]
  • Hybrid Memristor-CMOS Neurons for in Situ Learning in Fully Hardware Memristive Spiking Neural Networks
    Hybrid memristor-CMOS neurons for in situ learning in fully hardware memristive spiking neural networks Xumeng Zhang Fudan University Jian Lu Institute of Microelectronics of the Chinese Academy of Science Rui Wang Chinese Academy of Sciences Jinsong Wei Institute of Microelectronics of the Chinese Academy of Science Tuo Shi Chinese Academy of Sciences Chunmeng Dou Institute of Microelectronics of the Chinese Academy of Science zuheng Wu Institute of Microelectronics Dashan Shang Chinese Academy of Sciences https://orcid.org/0000-0003-3573-8390 Guozhong Xing Institute of Microelectronics of the Chinese Academy of Science Qi Liu Fudan University Ming Liu ( [email protected] ) Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Science Article Keywords: Spiking neural network, memristor-based neurons, hybrid memristor-CMOS neurons Posted Date: July 27th, 2020 DOI: https://doi.org/10.21203/rs.3.rs-43977/v1 License: This work is licensed under a Creative Commons Attribution 4.0 International License. Read Full License Version of Record: A version of this preprint was published at Science Bulletin on April 1st, 2021. See the published version at https://doi.org/10.1016/j.scib.2021.04.014. Hybrid memristor-CMOS neurons for in situ learning in fully hardware memristive spiking neural networks Xumeng Zhang#1,2,3, Jian Lu#2, Rui Wang2,3, Jinsong Wei2, Tuo Shi2,4, Chunmeng Dou2,3, Zuheng Wu2,3, Dashan Shang2,3, Guozhong Xing2,3, Qi Liu*1,2, and Ming Liu1,2 1Frontier Institute of Chip and System, Fudan University, Shanghai 200433, China, 2Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China, 3University of Chinese Academy of Sciences, Beijing 100049, China, 4Zhejiang Laboratory, Hangzhou 311122, China.
    [Show full text]
  • Memristors: Hardware Implemented Learning Circuits
    Memristors: Hardware Implemented Learning Circuits Memristance for Memristance for Project Description Team Members: Voltage Applied C = 1, L = 2 C = 2, L = 2 • The memristor was proposed in 1971 by v Leon Chua [1] on the basis of symmetry Troy Comi using the classical relationships describing Aaron Gibson resistance, capacitance, inductance, charge, i q Joseph Padilla current, voltage, and magnetic flux. Theoretical circuit used for emulating learning Frequency matching • Strukov et al. [2] reported the first physical responses in P. polycephalum . The inductor and C=1, L =2 ϕ realization of a memristor and a simple capacitor simulate biological oscillations, the model accounting for its behavior. resistor attenuates the response and the memristor alters the reaction from the RLC circuit. The input Symmetry argument for the and output voltages represent the stimuli and the • Since this report, several applications of existence of a memristor as a basic response respectively. Taken from [3]. memristors have been described including circuit element. Modeled after [2] light emitting memristors [5], memristor Methodology Frequency matching logic boards [4] and a circuit for modeling C=2, L =2 learning in primitive organisms [3]. 1. The above circuit was modeled assuming an ideal voltage source as described by [3]. The output voltage was • The modeling of a memristive learning measured across the capacitor and memristor. Note circuit is of particular interest due to the memristance is a function of voltage resulting in an inherently potential creation of hardware-based nonlinear equation. Combination of first artificial intelligence. two frequencies 2. Kirchhoff’s voltage and current laws are used to determine the Hybrid memristor/transistor logic The above figures demonstrate the training of two memory circuits in parallel following relationships: Scientific Challenges board as shown in [4].
    [Show full text]
  • Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices
    Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices Aidana Irmanova, Grant A.Ellis, Alex Pappachen James Department of Electrical and Computer Engineering Nazarbayev University Astana, Kazakhstan Email: faidana.irmanova,grant.ellis,[email protected] Abstract—The memristor can be used as non volatile memory The aim of this paper is to analyse the impact of memris- (NVM) and for emulating neuron behavior. It has the ability to tance variability and packaging on memristive devices. The switch between low resistance Ron and high resistance values parameters of equivalent circuit (R, L, C values) of packaged Roff , and exhibit the synaptic dynamic behaviour such as potentiation and depression. This paper presents a study on memristor used in this work were selected to model bond wires potentiation and depression of memristors in Quad Flat Pack. A used in Quad Flat packs or Ball grid arrays which are of the comparison is drawn between the memristors with and without interest for the low cost solution. Despite the speed limitation the impact of parasitics of packaging, using measured data and of Quad Flat Packs, its design can still be modified to provide equivalent circuit models. The parameters in memristor and higher speed of operation as in [3] packaging models for the SPICE simulations were determined using measured data to reflect the memristor parasitics in Quad The remaining of the paper is organized as follows: Section Flat Packs. II presents the details on the experimental setup of mem- Index Terms—Memristors, IC package, Quad Flat Pack, ristance measurements and memristor model modification.
    [Show full text]
  • Hybrid CMOS/Memristor Circuits
    Hybrid CMOS/Memristor Circuits D. B. Strukov D. R. Stewart J. Borghetti, X. Li, M. Pickett, G. Medeiros Department of Electrical and National Research Ribeiro, W. Robinett, G. Snider, J.P. Strachan, Computer Engineering Council of Canada W. Wu, Q. Xia, J. Joshua Yang, R.S.Williams* UC Santa Barbara 100 Sussex Dr, Ottawa, ON, Information and Quantum Science Laboratory Santa Barbara, CA 93106 USA K1A 0R6, Canada Hewlett Packard Laboratories [email protected] [email protected] Palo Alto, CA 94304 USA *[email protected] Abstract — This is a brief review of recent work on the film of titanium dioxide where resistance change is due to prospective hybrid CMOS/memristor circuits. Such hybrids electric field assisted modulation of oxygen vacancies profile combine the flexibility, reliability and high functionality of the [7]. Titanium dioxide by itself is wide band semiconductor, CMOS subsystem with very high density of nanoscale thin film i.e. insulating, but even the slightest oxygen nonstochiometry resistance switching devices operating on different physical turns it into very good conductor since oxygen vacancy acts as principles. Simulation and initial experimental results shallow donor. The device shown on the Figure 1 was demonstrate that performance of CMOS/memristor circuits for intentionally fabricated with the excess of oxygen vacancies several important applications is well beyond scaling limits of near the bottom electrode so that application of negative conventional VLSI paradigm. voltage to the top electrode forces positively charged vacancies to drift to the top electrode thus increasing the I. INTRODUCTION conductance of the device. The prospects to continue the Moore Law with current VLSI paradigm, based on a combination of lithographic patterning, CMOS circuits, and Boolean logic, beyond the 10 nm frontier are at best uncertain [1, 2].
    [Show full text]