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Future of Nano CMOS Technology

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Future of Nano CMOS Technology September 9, 2013, EDS Mini Colloquium – by Student Chapter at UNICAMP, Campinas, Brazil UNICAMP: Universidate Estadual de Campenus FutureFuture ofof NanoNano CMOSCMOS TechnologyTechnology Hiroshi Iwai Frontier Research Center Tokyo Institute of Technology 1 1. Back ground for nano-electronics 2 1900 “Electronics” started. Device: Vacuum tube Device feature size: 10 cm Major Appl.: Amplifier (Radio, TV, Wireless etc.) ÆTechnology Revolution 1970 “Micro-Electronics” started. Device: Si MOS integrated circuits Device feature size: 10 µm Major Appl.: Digital (Computer, PC, etc.) ÆTechnology Revolution 3 2000 “Nano-Electronics” started. Device: Still, Si CMOS integrated circuits Device feature size: 100 nm Major Appl.: Digital (µ-processor, cell phone, etc.) ÆTechnology Revolution?? Maybe, just evolution or innovation! But very important so many innovations! 4 Now, 2013 “Nano-Electronics” continued. Device: Still, Si CMOS integrated circuits Device feature size: near 10 nm Major Appl.: Still Digital (µ-processor, cell phone, etc.) Still evolution and innovation.. But, so many important emerging applications for smart society. 5 Questions for future Future, “Nano-Electronics” still continued? Device: Still, Si CMOS integrated circuits? Device feature size: ? nm, what is the limit? Application: New application? ÆAny Technology Revolution? 6 What is special or new for Nano-Electronics? In 1990’s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects. However, no fancy new operational principle was found. At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS. Of course, I do not deny the importance of Beyond CMOS technology development. It is becoming very important as CMOS approach its limit. 7 Ballistic conduction will not happen Ballistic transport will never even decreasing channel lengh. happen for MOSFET because L of back scattering at drain source drain λ ：Mean free path L >> λ Diffusive transport With decreasing channel length, L~λ Drain current increase continue. Quasi-Ballistic R transport M L < λ Ballistic transport Back scattering from drain Also, 1D quantum conduction, or ballistic conduction will not happen. 8 (1D quantum conduction: 77.8µS regardless of the length and material). 2. Importance of nano-electronics as integrated circuits 9 First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament Æ dreamed of replacing vacuum tube with solid‐state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 10 by D.1960 Kahng and M. Atalla Top : First MOSFET View Si Source Al Gate Drain Si Al SiO Si/SiO2 extraordinarily Si 2 Interface goodis 11 1970,71: 1st generation of LSIs DRAM Intel 1103 MPU Intel 4004 12 In 2012 Most Recent SD Card 128GB (Bite) = 128G X 8bit = 1T(Tera)bit 1T = 1012 = １Trillion World Population：7 Billion Brain Cell：10～100 Billion Stars in Galaxy：100 Billion 13 128 GB = 1Tbit 2.4cm X 3.2cm X 0.21cm Volume：1. 6cm³ Weight：2g Voltage：2.7 - 3.6V Old Vacuum Tube： 5cm X 5cm X 10cm, 100g, 50W What are volume, weight, power consumption for 1Tbit 14 Old Vacuum Tube： 1Tbit = 10,000 X 10,000 X 10,000 bit 5cm X 5cm X 10cm Volume = (5cm X 10,000) X (5cm X 10,000) X (10cm X 10,000) = 0.5km X 0.5km X 1km Burji Khalifa 500 m Dubai, UAE Pingan Intenational Indian Tower (Year 2010) Finance Center Mumbai, India Shanghai, China (Year 2016) (Year 2016) 1,000 m 828 m 700 m 700 m 1Tbit 15 Old Vacuum Tube： 1Tbit = 1012bit 100W Power = 0.05kWX1012=50 TW Nuclear Power Generator 1MkW=1BW We need 50,000 Nuclear Power Plant for just one 128 GB memory In Japan we have only 54 Nuclear Power Generator Last summer Tokyo Electric Power Company (TEPCO) can supply only 55BW. We need 1000 TEPCO just one 128 GB memory Imagine how many memories are used in the world! 16 So progress of integrated circuits is extremely important for power saving 17 Brain: Integrated Circuits Ear, Eye：Sensor Mouth：RF/Opto device Stomach：PV device Hands, Legs：Power device 18 Near future smart-society has to treat huge data. Demand to high-performance and low power CMOS become much more stronger. 19 Semiconductor Device Market will grow 5 times in 12 years, even though, it is very matured market!! 2011 2025 300B USD 1,500B USD Gartner: By K. Kim, CSTIC 2012 20 2. Current status of Si-CMOS device technologies 21 Downsizing Important for Decreasing cost, power Increasing performance 22 Feature Size / Technology Node (1970) 10 μm Æ 8 μm Æ 6 μm Æ 4 μm Æ 3 μm Æ 2 μm Æ 1.2 μmÆ 0.8 μm Æ 0.5 μm Æ 0.35 μm Æ 0.25 μm Æ 180 nm Æ 130 nm Æ 90 nm Æ 65 nm Æ 45 nm Æ 32 nm Æ (28 nm Æ) 22 nm(2012) From 1970 to 2013 (This year) 43 years 1 generation 18 generations 2.5 years Line width: 1/450 Line width: 1/1.43 = 0.70 Area: 1/200,000 Area: 1/2 = 0.5 23 Problem for downsizing Region governed Region governed DL touch with S by gate bias 0V By drain bias Region (DL) 0V Gate metal V Large IOFF dd 1V 1V 0V Gate oxide No tox. Vdd 0V Source Drain thinning 0V 0V < Vdep＜1V 0V < Vdep＜1V Channel Large IOFF (Electron current) 0V t O X , V 0V Substrate 0V d V Depletion d th dd in 0V ni 0.5V Region (DL) ng by Drain Bias 0V tox and Vdd have to be decreased for better channel potential control Æ IOFF Suppression 24 LLgategate andand ttoxox(EOT)(EOT) scalingscaling trendtrend A. Toriumi (Tokyo Univ), IEDM 2006, Short Course ( ( ox t 25 OurOur WorkWork atat TIT:TIT: HighHigh--kk EOT=0.40nm 140 120 L/W = 5/20µm Vg= 1.0V /Vsec] T = 300K 2 100 × 16 -3 Vg= 0.8V Nsub = 3 10 cm 80 EOT = 0.40nm Vg= 0.6V 60 L/W = 5/20µm 40 T = 300K Vg= 0.4V × 16 -3 Drain Current (mA) 20 Nsub = 3 10 cm Electron Mobility [cm Mobility Electron 0.2 0.4 0.6 0.8 1.0 Vg= 0.2V 0 Vg= 0 V 00.511.522.5 0 0.2 0.4 0.6 0.8 1.0 Eeff [MV/cm] Drain Voltage (V) 26 What would be the limit of downsizing! 3 nm Tunneling distance Direct‐tunnel current for Electron Energy or Potential Channel Source Drain 27 Subtheshold leakage current of MOSFET Id Subthreshold Current Ion Is OK at Single Tr. level OFF ON But not OK For Billions of Trs. Subthreshould Leakage Current Ioff Vg Vg=0V Subthreshold Vth region (Threshold Voltage) 28 Subthreshold leakage current will limit the downsizing Id (A/µm) Ion Electron Energy 10-5 Boltzmann statics Exp (qV/kT) Vd 10-7 0.5 V 1.0 V 10-9 Vth Ioff 0.15 V 0.3 V 10-11 00.51 Vg (V) 29 The limit is deferent depending on application 100 e) 10 1 Operation Frequency (a.u.) Subthreshold Leakage (A/µm) 30 Source: 2007 ITRS Winter Public Conf. How far can we go for production? Past 0.7 times per 2.5 years 10µm Æ 8µm Æ 6µm Æ 4µm Æ 3µm Æ 2µm Æ 1.2µm Æ 0.8µm Æ 0.5µm Æ 0.35µm Æ 0.25µm Æ 180nm Æ 130nm Æ 90nm Æ 65nm Æ 45nm Æ 32nm Limit depending Fundamental on applications limit Subthreshold Direct-tunnel Drain bias induced Now Future (28nm) Æ 22nm Æ 16nm Æ 11.5 nm Æ 8nm Æ 5.5nm? Æ 4nm? Æ 2.9 nm? Æ Intermediate ・At least 4,5 generations to 8 ~ 5 nm node 31 Extremely Thin SOI Drain bias 0V 0V induced depletion G 0V 0V G 1V 1V Extremely thin Si SD0V S SiO2 0V ＜V＜1V SiG 0V 0V Planar Extremely Thin SOI 32 Suppression of subthreshold leakage by surrounding gate structure 0V 0V Drain bias induced depletion 0V 1V G G 0V 1V Si fin or nanowire S SD0V 0V ＜V＜1V G 0V 0V Planar Multi gate 33 Because of off-leakage control, 0V SD Planar Æ ＦｉｎÆ Nanowire 0V G G 0V 1 0V SD 1V Wdep Leakage current Gate Source Drain Planar FET Fin FET Nanowire FET34 Nanowire structures in a wide meaning GGG G G G Fin Tri-gate Tri-gate Ω-gate All-around (Variation) 35 OurOur workwork atat TIT:TIT: ΩΩ--gategate SiSi NanowireNanowire S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) Lg=65nm 101.E-03-3 1.E-04-4 Vd=-1V Vd=1V Poly-Si 10 SiO 12 nm 2 101.E-05-5 NW 1.E-06-6 10 Vd=50mV Vd=-50mV 101.E-07-7 SiN SiN pFET nFET 19 nm 101.E-08-8 SiO 2 101.E-09-9 101.E-10-10 1.E-11-11 DrainDrain Current Current (A) (A) 10 101.E-12-12 -1.5 -1.0 -0.5 0.0 0.5 1.0 Gate Voltage (V) ・Conventional CMOS process ・High drive current (1.32 mA/µm @ IOFF=117 nA/µm) Lg=65nm 00.511.52・DIBL of 62mV/V and SS of 70mV/dec 36 ION (mA/µm) for nFET MoreMore MooreMoore toto MoreMore MoreMore MooreMoore Technology node Now Future 65nm 45nm 32nm 22nm 15nm, 11nm, 8nm, 5nm, 3nm Lg 35nm Lg 30nm (Fin,Tri, Nanowire) Planar Tri-Gate Si Si channel (ETSOI) 28nm ET: Extremely Thin Si is still main stream for future !! M.
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