APPLICATION
Flexport : a remotely reconfigurable interface based on FPGA
Jean Conter
ENSEEIHT-IRIT 2, rue Charles Camichel 31071 Toulouse cedex [email protected]
ABSTRACT. FPGAs are the key technology for improving computer architecture. These devices are generally used for computing purposes - so called virtual computing - but can also be employed to perform communication tasks. In this paper, we present an implementation of a remotely reconfigurable interfacing unit (RIU) based on the Xilinx SRAM FPGA technology. This generic approach can be seen as an effective alternative to classical USARTs and, by extending the reconfiguration process to the whole computer architecture, provides a solution for heterogeneous machine communication.
RESUME. Le développement des FPGA engendre de nouvelles solutions dans le domaine de l'architecture des ordinateurs. Ces circuits sont en général employés pour réaliser des fonctions de calcul et de supervision- on parle alors de processeurs virtuels- mais ils peuvent également être utilisés dans des fonctions de communication; nous présentons dans cet article une expérience de réalisation d’interface reconfigurable à distance basée sur la technologie FPGA SRAM de Xilinx. Ce nouveau concept d’interface flexible peut se substituer avantageusement aux USART classiques et, en étendant la notion de reconfiguration à l’ensemble des parties constitutives de l’ordinateur, fournit une solution ouverte à la communication entre machines hétérogènes.
KEY WORDS : flexible interface, generic serial I/Os, reconfigurable interfacing unit, universal serial link, FPGA remote configuration
MOTS-CLES : interface flexible, entrées/sorties séries génériques, unité d’interfaçage reconfigurable, liaison série universelle, configuration de FPGA à distance.
This article was originally published (in French) in Techniques et Sciences Informatiques. Volume 18 - n° 10/1999 Page Flexport num 1. Introduction
FPGA's (Field Programmable Gate Arrays) have been commercially introduced by Xilinx in 1985. These circuits differ from PLD's (Programmable Logic Devices) by their internal architecture (Cf. figure 1), their density and their programming mode. In fact, as PLDs are essentially based on a two level of logic model (sum of products), FPGAs are more alike Gates Arrays, arrays of logic cells surrounded by IO cells. In a classical ASIC, the intra and inter cell links determine the circuit's functionality and this one is done at production time. In a FPGA, all cells and most of the links remain programmable after production : this post-programmation is called configuration. According to the technology, the user can configure the FPGA once (fuse, antifuse) or as many times as necessary (eeprom, sram). Configuration is done in parallel or serially from a configuration file called bitstream. In this article, we are particularly interested in SRAM technology, in which the bitstream is loaded into a static RAM (every bit determines the on/off status of each internal connection of the FPGA). No specialized device is needed to configure the FPGA with this technology. The debugging is also simpler due to the readback facility which enable to know the state of every internal node at a given moment. This technology is certainly the most flexible as the circuit's functionality can be changed as often as wanted, including when the FPGA is operating (dynamic reconfiguration). The advantages of this later concept is known for a long time [GRA 89] but rarely used in industrialized products. Nevertheless, the technology is confident and enables efficient solutions in various domains such as artificial vision [KEA 97]. For example, a camera with a build-in FPGA [CON 97] can identify shapes at a high rate while enabling, by a simple reconfiguration, various improvements (algorithmic change) without any physical modification on site : obsolescence of material is therefore avoided. The recent achievement of partially reconfigurable FPGA's (a part of the circuit can be modified without disruption of the whole circuit, which can be seen as hardware overlay) enforces the power of this concept. RPUs (Reconfigurable Processing Units) belong to this kind of FPGAs : combining power of processing and ease of use, they are perfectly adapted to experiments on evolutionist material [CON 98]. The design of a FPGA based system requires powerful CAD tools [LUD 97], yesterday mainly based on graphical description (schematic entry) making use of huge primitives libraries. More and more, dedicated logical description languages are used instead of the former graphical approach (VHDL [AST 96], JHDL [BEL 98], LOLA [WIR 96], MDL [CON 93]). Indeed, these languages offer better capabilities in terms of exchange, documentation, modification, modeling, verification, simulation and test. Flexport : a flexible interface on FPGA Pag e
I2 I1 I0 I2 I1 I0 fixed OR prog. OR array array 6 8
programmable fixed AND AND array array (Ix represent optional FlipFlop O2 O1 O0 addresses) O2 O1 O0
PAL (GAL) architecture PROM architecture
I2 I1 I0 prog OR array
programmable AND array. I/O blocks Logic Block (CLB) (IOBs) interconnection Link O2 O1 O0 NB : IOB, CLB and Links are programmable
PLA (FPLA) architecture FPGA architecture
Figure 1. Simplified architectures of PLDs (PAL, PROM, PLA) and FPGAs Page Flexport num 2. A real world FPGA application
When reconfigurable architectures are more and more involved for computing purposes [DEH 96, VUI 96] - 90 references in [GUC 99] - , they have been far less used in generic interfacing units. Beside solutions targeting parallel communication buses (PCI [XIL 95], PCMCIA or VME [HAU 95]), FPGAs can interestingly be used in simple serial links. Indeed, a vast majority of computers are equipped with asynchronous serial links, born at the beginning of computer ages. This mode of communication is simple and robust and, nevertheless exotic implementations (especially at the connector level), a 3 order of magnitude improvement in the data rate enables this standard to be compatible with the best analog modems at the time. Communication thru non guided Infrared links, available on most portable computers, telephones and data assistants, is in the direct continuation of the former serial links (newly available UARTs support at least the SIR protocol of the IRDA standard [TAJ 95]). However, in order to use more and more complex serial interfacing components, specific drivers are needed and make the programmer and final user task difficult (not less than 25 registers on the venerable Z8530). Furthermore, these asynchronous serial links have poor performances to fulfill the communication needs. More recently, fast serial links have been introduced : USB and IEEE 1394. These links offer real advantage compared to the former ones (more speed, hot-plug capability, multiple addressing, power thru the link,...) but also suffer some defaults (short distance, dedicated connectors, fixed communication protocol, durability : is USB necessary compared to IEEE 1394 ? ). FPGA components are a key solution for a more rational and efficient method : a true universal interface and its universal driver.
REMARK. — We only consider here serial communication links between two points and will focus on Flexport, an experimental experiment for a virtual interface. .
2.1. Main advantages of a reconfigurable interface
2.1.1. Universality
A reconfigurable circuit can not only fit to all existing physical protocols but also to experimental ones, to-morrow standards : a simple configuration file gives the generic interface a new functionality. It is then possible to retrieve and process information coming from a remote control, a portable telephone (with an IR link) or from a PDA without needing to invest in a costly specific interface. Flexport : a flexible interface on FPGA Pag e 2.1.2. Flexibility
In order to get a real flexibility of the material, its modification (by reconfiguration) must be possible not only from the host system but also from a distant one; thus, only one system is responsible for choosing the communication parameters (format, speed, mode, physical protocol). Therefore, a de facto compatibility can exist between heterogeneous equipments.
2.1.3. Simplicity
Having a solution for the configuration process, there is no more need to know the details of the physical implementation in order to program the application : a single control/status register and a data register are only necessary to handle the transfer. If the allocation of each status bit is well defined, writing an universal driver is greatly simplified (for both a polling method or under interrupts). In the present implementation of Flexport, the restriction to 8 bits (with or without parity) addresses the problem of the eventual byte swap for larger busses. This restriction is not definitive.
2.1.4. Confidentiality
If only one machine imposes its operating mode, specific coding schemes can be used in order to hinder every line interception (external protection) but also decyphering tentatives on the distant computer (internal protection). In fact, using always the same program or the same hardware to cypher/decypher data can be tampered (FPGA producers claim that it is impossible to disassemble a bitstream : that is not true, even if it requires a lot of effort). Using new and often changed cyphering methods, silently downloaded on the distant host, can certainly add more confidence for each transaction (Cf. figure 2).
link interception can be possible
non secured side interception can be possible secured side on distant computer
secure computer (with access control) distant computer
Figure 2. Confidentiality and communication security Page Flexport num 2.1.5. Performance
The signals being processed by programmable logic, fast data rates could be obtained. Even short pulse signaling can be handled as well. It is also possible to define auto-synchronized transfers, with no loss of data independently of each machine speed. The best data rate is obviously limited by the slower site.
2.1.6. Security
Flexport boards are equipped with optical tranceivers : one for input and one for output ; a duplex plastic fiber enables to connect two equipments without any short risk and with a full galvanic isolation. Therefore, it is possible to hot-plug two powered units without any precise chronology; that is especially interesting for prototypes.
2.1.7. Cooperation
A virtual interface must be able to protect itself against every no previously accepted reconfiguration ; this is necessary because a bad configuration could even destroy the FPGA or some of its surrounding circuits. Therefore, it is necessary to identify, with no doubt, the origin of the bitstream. Another potential problem could arise from a long suite of '0' in the synchronous mode : this can lead to an unwanted reconfiguration of the distant FPGA; in this case, there must be a way to cancel the reconfiguration or, better, to avoid it. In such a context, FPGA reconfiguration must be seen as a partnership.
2.1.8. Evolution
Flexport first versions were designed to use indifferently 2K, 3K and 4K[XIL 94] Xilinx family circuits. The same process could be applied to newer families (5K, Spartan, Virtex and 6K[XIL 97]) or SRAM FPGAs from another producers. It is highly desirable to benefit from the bigger performances of FPGA new generations without changing initial choices. But, before the improbable standardization of bitstream files (remember : apart very rare exceptions [XIL 97] , bitstreams files remain secret) , we have to generate and to archive at least a bitstream per target FPGA. Developments of 'Open Hardware Foundation' actions, like the picoJava initiative from SUN, would probably lead to more compatibles architectures and configuration procedures.
Flexport : a flexible interface on FPGA Pag e 2.2. Principle of operation
We want to exchange data between 2 computers equipped with universal interfaces like Flexport. The following 4 steps occur: - One of the two computers, called Initiator (I), identifies and configures the FPGA of its local virtual interface. - Thanks to a Break command sent on the outgoing channel of its interface, the Initiator resets the distant interface (Partner) and acquires its signature (identification) on the in-going channel. - Initiator then sends a compatible configuration file to the distant interface (P) on the outgoing channel. - The link can now be exploited in the chosen mode (synchronous or asynchronous). There is no more Initiator : the two sites are now interchangeable.
Affectation of ingoing and outgoing channels is summarized here :
Identification Break then Identification Clock I P Ack for Break then Signature
Configuration Bitstream I P Configuration Clock
Exploitation Data (or Clock) A B Data (or Clock)
As it can be observed, the 2 first phases make use of a synchronous communication mode. The last phase (Exploitation) can indifferently use a synchronous (see paragraph 2.2.3) or asynchronous mode. In this phase, the transfer is symmetrical (full duplex in asynchronous mode and half duplex in asynchronous mode).
2.2.1. The meta-protocol
In order to enable Identification and remote configuration of a distant Flexport board, a unique procedure, common to all Flexport boards, must be followed. This procedure, called meta-protocol, is activated thru a long delay pulse (Break pseudo- code) on the outgoing channel. The following 2 limits are defined and can determine two sorts of Break events : Page Flexport num - Long Break corresponds to a more than 100 milliseconds activation. It triggers the FPGA reconfiguration thanks to a dedicated external logic (Wait for configuration while emitting a configuration clock). - Short Break is a more than 50 milliseconds activation (but less than 100 milliseconds. It sends the contents of the ID ROM and resets the FPGA (without entering the configuration mode).
It is absolutely necessary to avoid such breaks in the exploitation phase. This is always true in asynchronous mode, when baud rates greater than 300 bauds are used (at this low speed, the NULL code activates the line for less than 34 milliseconds). For lower speeds or in synchronous mode, the Flexport board must be protected against unwanted configurations (Cf. paragraphs 2.1.7 and 2.4.1) ; if protected, there is no more constraint for the data in the Exploitation phase.
In Identification phase, the meta-protocol makes use of a synchronous link where the data is transmitted on the outgoing channel according to a clock received on the in-going channel. There is no constraint on the frequency of this clock (except for an upper limit imposed by the optical tranceivers) . In order to avoid a booting configuration of the FPGA, the meta-protocol is handled by a separate PLD logic. The control is therefore context free guaranteed.
REMARK. — a more satisfying solution for identification would be to convince FPGA producers to incorporate an internal signature to their components. This signature could be read sequentially upon request. This could avoid an external ROM (but this ROM can also provide additional context information such as maximal or actual clock frequency).
2.2.2. Identification file format
The link being synchronous in this initial phase, the identification file is a bitstream beginning with the following 24 bits : 010110000100110001010101 (meaning: 'ULX'=Universal Link Xi, Xi being the internal name of Flexport), the right bit (the 1 of the 'U' character) being transmitted first. In fact, this file corresponds to the synchronous serialization of bytes being mostly ASCII characters. This file is stored in a non volatile memory (NVM) of serial EEPROM type. The end of this file can be a bitstream model compatible with the FPGA on the target board; in this case, a preamble add-on explains the bitstream characteristics and the mode of operation. The aim is to deliver a minimal functionality for exchange without any other configuration file on disk. This default configuration file must however be read (either locally or remotely) before being stored in the FPGA. Flexport : a flexible interface on FPGA Pag e Identification file format is such : 128 bits header + preamble + optional bitstream (contents and commentary are added for clarity).
32 bits : 'ULX'n ;prefix and FPGA code (n='2'=$32 if XC3020, n='E'=$45 if XC4005, n=0 if extension, etc...) 48 bits : xxxxxx ;unique code for this board 24 bits : ccc ;bits count NVM (for exemple 36288 for XC1736) 24 bits : ppp ;P=preamble size (number of bits) 8 bits :%00000010 ;
REMARK. — in the simplest implementation, the 32 first bits of the header are sufficient to identify the interface because they contain an FPGA identifier. End of lines are
The synchronous mode used in the identification and configuration phases is classical : each information bit placed on the outgoing channel is sampled by a rising edge clock signal on the in-going channel. By contrast, the exploitation phase makes use of a special synchronous mode : as in an asynchronous transmission, the byte to send is surrounded by a START bit (0) and a STOP bit (1). Writing a byte in the data register (point 1 in figure 3, signal NWR) applies a START bit on the outgoing channel (point 2, signal SOUT), and implies in turn, when the partner board is also configured in synchronous mode, the sending of a sampling clock on the in-going channel (point 3, signal SIN). Successive bits of the data byte, with LSB first, are sent according to this clock. The clock coming from the distant FPGA exactly delivers 8 rising edges ; the 9th edge (return to the line rest state) will occur only when the data byte has been read by the destination board (point 4, signal NRD). This system implements an auto- synchronisation of the exchange, the emitter always knowing, through the TBE bit (Transmit Buffer Empty, Cf. status register § 2.4.2), when the data has been taken by the receiver. The following chronogram (figure 3) illustrates the sending of $FD in synchronous mode (video inverted signals indicate the sending site).
REMARK. — during exploitation phase in synchronous mode, each site can be transmitter or receiver but the communication is obviously half-duplex (full duplex is possible only in asynchronous mode).
1 2 3 4 Figure 3.Synchronous sending chronogram in exploitation phase
2.3. Material architecture
2.3.1. Representation conventions for signals
Names beginning with N correspond to low acting signals (example NRD=Non ReaD). Inputs and outputs are represented in positive logic but with a 1 resting level (Stop bit=1). In order to minimize power, the emitting LED of the Versatile Link module [HEW 93] will be on with the 0 logic level. (this convention is also used in SIR and MIR modulations of the IrDA standard). Flexport : a flexible interface on FPGA Pag e 2.3.2. Pinout choice
In order to shrink the number of configuration files, we try to use the same bitstream for a given circuit (XC3030A for example) independently of its package (PC44, VQ64, PC68, PC84, PG84, PQ100, VQ100, etc...). We must therefore focus on the pads (silicon die connections) and not on the pins (package connections) to satisfy this objective (using a dedicated constraints file). Obviously, this implies that the PCB designer respects the pin/pad correspondence for each package he uses. Another constraint, interesting for prototypes, is to try to keep a pinout compatibility between different FPGA types. Unfortunately, this constraint is rarely respected by FPGA producers, even with their own products (including for power pins...) and it is not obvious to find a common pins subset in several families. We tried to do that in the ISA bus version of Flexport : we can plug indifferently 2064, 2018, 3020 and 3030 devices on the same PLCC68 holder. A Signal/Pad/pin corresponding table where inter-type pinout compatibility and bitstream unicity is given in annexe I. This corresponding table must be respected by a new interface designer in order to maintain binary compatibility with already existing Flexport boards. It can be observed that 3000A, 3000L and 3100A families share the same pinout.
2.3.3. Physical inputs/outputs
The I/O equipment for Flexport (Cf. figure 4) is based on HFBR-0501 optical links (with a usable bandwidth from DC to 5 megabits/second). This rate can be increased by more than an order of magnitude with more recent components of the same supplier, keeping the same connecting way and this a reasonable price. A RS- 422A tranceiver is also available. Other standards (RS-232C for example) can easily be adapted and coupling infra-red modules is also straightforward.
2.3.4. Flexport different implementations
Today, Flexport has been ported to two types of buses : ISA (tested on PC and HADES60 (from Medusa Computer System)) and PCI bus. This concept can also be used on every other bus standard. Only the lower part of the following synoptics (figure 4) has to be adapted to the signals for the target bus. Page Flexport num
OUT Optical fiber external connection IN
½ 75179A DOUT DTIN NDIN Gal for SBrk detector ND50 meta-protocol handling LBrk detector ND100 M NCE 22V10 E NCEO T NVMD A CSYNC XOUT - ZCMD P C3/C1/C0 R ID CLK O PROM T (NVM) O DIN NRESET NINIT C O configuration FPGA RBF L clock (SRAM) TBE generator CCLK NPRG NLDC NRD IRQ F NWR P C7..C2 D7..D0 G A
GAL decoder Z 7 6 5 4 3 2 1 0 20V8 COMMAND STATUS register I S A - B U S DIR BUFFER
ADDRESS IOR,IOW,AEN IRQ DATA
Figure 4. Flexport board Synoptic (with ISA bus interface) Flexport : a flexible interface on FPGA Pag e 2.3.5. Flexport FPGA programmation
The whole logical design of Flexport was done on HI-Tech [CON 93], a logical circuits IDE made at IRIT. This interactive environment is built on MDL, a structural description language for synchronous and asynchronous logic (See MDL coding example in Annex II). Such a description takes care of the internal architecture of the target FPGA from the beginning of the design and leads to a better usage of its ressources (a behavioral description, far simpler to write, leads generally to a waste of ressources)). MDL enables an incremental modular description : the placement/routing (and therefore the temporal characteristics) of already defined and tested modules can be maintained. The MDL compiler can, from a MDL description, generate VHDL, XNF or CAL files. The bitstream generation is done from the XNF files or directly for the RPUs. The MDL language being syntactically compatible with PALASM, the MDL files can also be used for GAL programmation. As an example, the metaprotocol GAL and the Flexport top module descriptions are given in annex II..
2.4. Software Architecture
As stated in 2.1.3, operating Flexport only requires 2 addresses: a data address and a Command/Status address (Write=Command, Read=Status).
2.4.1. Command register
7 6 5 4 3 2 1 0 INTE RAZ ETIM SMOD C3 C2 C1 C0
INTE interrupts enable (for receiver and/or Timer) RAZ FPGA initialization (different from RESET) ETIM TIMER interrupts enable (embedded in FPGA) SMOD Synchronous Mode in exploitation phase. In this mode, a channel is reserved for data and the other for clock (Cf. paragraph 2.2.3). Communication is half-duplex with auto-synchronization ; With this mode, a high speed can be obtained : the sender knows when the data has been read by the destination (Cf. TBE bit in status register). - C3 =1 , with C1and C0, enables to identify or configure the local board. - C3 =0 , with C1 and C0, enables to identify or configure the distant board (C2 is reserved. More details, for example how to protect against an external reconfiguration, can be found in the identification file in 2.2.2.). The Command Register is initialized with 0 at RESET time. Page Flexport num 2.4.2. Status Register
7 6 5 4 3 2 1 0 IRQ NLDC NINIT XOUT DTIN NPRG TBE RBF
IRQ signal is active (1 value) when an interrupt condition arises : either with a character beeing received or with a TIMER overflow. The NDLC signal is connected to the LDC pin of the FPGA ; this signal is active (0) until the configuration completion. After configuration, it can be affected to a signalling receiver error (bad parity for example). A red LED lits when NDLC signal is 0. The NINIT signal is connected to the INIT pin of the FPGA ; this signal keeps a 0 value during the FPGA initialization. After configuration, it can be used to display the transmitted signal. A green LED lits when the NINIT signal is 0. The XOUT signal comes directly from the XOUT output from the GAL handling the meta-protocol. XOUT enables to read the contents of the local NVM. The DTIN signal is a copy of external serial input (Versatile Link or RS422). It is therefore possible to decode the input by software, when this signal is not too fast. The NPRG signal comes from the P/DONE pin of the FPGA. It becomes 1 when the FPGA has been configured. A 0 value indicates a non configured local FPGA and therefore non operating FPGA. TBE (Transmit Buffer Empty) goes to 1 when the Transmit buffer is Empty. A new character can then be transmitted. In the synchronous mode, this bit indicates that the last character has been read by the receiver : this provides a very simple synchronization technique for the exchange. RBF (Receive Buffer Full) is 1 when the receiving buffer is full. The received character can then be read is this buffer.
2.4.3. C programming example
From the two Command and Status registers, it is very simple to write an application. Being an ISA board on a PC, we suppose that the inportb() and outportb() functions of the Borland C compiler are available (these functions enable direct access to the peripheral space, thanks to IN and OUT instructions). We suppose also that the FPGA is already configured (Cf. IsFpgaOk() function).
#define data 0x02d0 /* basis address for Flexport ISA version */ #define cntrl (data+2) #define RBF 1 #define TBE 2 #define NPRG 4 Flexport : a flexible interface on FPGA Pag e /* IsFpgaOk() routine returns 1 when the FPGA is configured, 0 if not */ int IsFpgaOk(void){ return (inportb(cntrl) & NPRG) ?1:0 ; }
/* non blocking byte read */ /* returns a negative value (-1) if nothing available else the character code in the 8 low order bits of the int */ int getbyte(void){return (inportb(cntrl) & RBF) ?(0x00ff & inportb(data)) :-1 ;}
/* non blocking byte send */ /* returns 1 if OK, 0 if not done (because the Transmit buffer is not yet empty */ int putbyte(unsigned char x){ /* non blocking */ if(inportb(cntrl) & TBE){outportb(data,x) ;return 1 ;} else return 0 ; }
/* It can be noted that these routines are valid whatever the mode : the transmission is either asynchronous (full duplex) or synchronous (half-duplex) according to the bit #4 of the Command Register. In synchronous mode, TBE=1 means that the distant site has read the sent byte and not only the end of its sending (like in asynchronous mode). The transmit speed relies on a local oscillator and on a pre-scaler defined in the FPGA. The rate must match on both sites in asynchronous mode (the bitstreams must ensure that). In synchronous mode, however, the local and distant frequencies can be set independently. The transmission can be either processed under interrupts or by a polling method. */
2.5. FPGAs in industry
Despite numerous advantages carried out by FPGAs, their use in industrial applications is not yet so widespread. Concerning both research oriented developments (HOT-Works by Virtual Computer Corporation, Pamette by DEC-Compaq) or simple generic interfacing tools (FP-Flex by TEK Microsystems, IPG3 by LORIN), a few thousands of these flexible solutions have been delivered. On reason for this relative lack of success comes probably from an economic origin : when a standard interfacing board costs a few dollars, a FPGA equipped board costs two order of magnitude more, without taking in account the investment in a dedicated development system. Even so called 'universal development systems', costly, dont exempt the leader to choose, from the origin of the design, the target FPGA (because of architectural specificity or tests homologation requirements). The challenge between ASICs or ASIPs, developed for standard applications in hundreds of thousand units, and FPGAs with a remaining high unitary cost is therefore unequal. FPGA founders deliver application ready Page Flexport num 'cores' but corresponding solution exist also from ASIC founders. Even the availability, a top argument for FPGAs, can be beaten : dedicated Gate Arrays can be delivered in one day ! (Chip Express LPGA technology). FPGA based boards correspond therefore to smaller specific domains, badly covered with standard solutions. Prototyping remains the major FPGA application field in industrial solutions. In order to change this situation, costs have to be downsized or FPGA specific properties have to be plainly used, for example dynamic reconfiguration. This is the case for networked embedded systems, in particular in multimedia and e-commerce. Enabling an increased flexibility level, the remote configuration, Flexport enters a new domain, without coverture with traditional ASICs or PLDs.
3. Conclusion
The flexible peripheral system presented in this article can be applied to every computer (featuring or not a standard bus). Enabling high bandwidth, automatic synchronization techniques, implicit parameter settings, and complying with any existing protocol, it could be a common interfacing way of connecting experimental platforms, especially those using FPGAs. Indeed, FPGA usage, formerly reserved to specialists, is now accessible to everyone thanks to user friendly development systems : the IRL initiative (Internet Reconfigurable Logic) enables a distant use of powerful FPGA foundry tools. Going further than the mobile code concept, the transfer of configuration data through the Web [ALE 97] is a kind of 'functional teleportation', long awaited by Science Fiction authors !. The possibility of producing, instantly, material by exclusively software ways, and therefore by a larger number of people, is a good way to increase the FPGA application field. But a long way still remains before the FPGA producers agree on standard configuration procedures !
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[XIL 97] XILINX « XC6200 Field Programmable Gate Arrays » 24 Avril 1997. Page Flexport num Annex I
Here is a partial table for Signal/Pad/Pin correspondances in which compatibility between inter-type pinout (3020A and 3030A in this example) and bitstream unicity for a given type are preserved.
FPGAType XC3020A XC3030A Package type PC68 PC84 PC44 PC68 PC84 Pad Pin Pin Pad Pin Pin Pin VCC 18,52 22,64 12,34 18/52 22,64 GND 1,35 1,43 1,23 1,35 1,43 NRESET - 44 54 - 27 44 54 CCLK - 60 74 - 40 60 74 NP/DONE - 45 55 - 28 45 55 D7 37 39 47 47 24 39 47 D6 35 41 49 43 25 41 51 D5 30 48 58 38 31 48 58 D4 28 49 60 34 32 49 60 D3 26 51 62 32 33 51 62 D2 24 53 65 30 35 53 65 D1 22 55 67 28 36 55 67 D0 20 56 70 24 37 56 70 DIN=SIN 18 58 72 22 38 58 72 NWR 16 61 75 20 41 61 75 NRD 15 62 76 19 42 62 76 RBF 14 63 77 18 43 63 77 NINIT=DOUT 41 34 42 51 22 34 42 NLDC=OK 45 30 36 57 20 30 36 HDC=TBE 47 28 34 59 19 28 34 IRQ 4 6 8 4 4 6 8 C2 11 66 82 13 44 66 82 C3=LOCAL 5 5 5 7 3 5 5 C4=SMOD 43 32 39 53 21 32 40 C5=ETIM 7 3 3 9 2 3 3 C6=RAZ 1 9 11 1 6 9 11 C7=INTE 3 7 9 3 5 7 9 XOUT 49 24 30 61 15 24 30 XTL1 31 47 57 39 30 47 57 XTL2 33 43 53 41 26 43 53 H16X 58 16 20 73 11 16 19#
NOTE. — caret correspond to special signals which can be used directly with their name by synthesis tools. # denotes a direct incompatibility. M0, M1 and M2(through 5K) entries are connected to +Vcc (Slave Serial Mode) Flexport : a flexible interface on FPGA Pag e
Annex II
;PALASM file for meta-protocol GAL programmation
GAL22V10;FLEXPORT meta-protocol GAL handler HCNF C3 DTIN ND50 NINI NC ND100 NVMD NCEO C1 C0 GND XTRST ZCMD NPRG NCE DIN NCLK NRST DOUT NDIN XOUT SYNC VCC SYNC=C3*C1*NINI*/NPRG*NRST*NCE+/C3*/C1*/C0*NINI*/NPRG*NRST*NCE NDIN=/DIN*C3+/DIN*C1+/DIN*/C0 NRST=ND50*NRST*/C3+ND50*NRST*C1+ND50*NRST*C0+ND50*/NCEO*/C3+ ND50*/NCEO*C1+ND50*/NCEO*C0+C3*/C1*C0 DOUT=C3+C0*C1+C0*C3+XOUT*/C1 /NPRG=/ND100 NPRG.trst=/ND100 DIN=C3*C0+C1*C0+C3*/C1+/C3*C1+/C3*DTIN NCE=/ND50+NRST+C3*/C1*C0+XTRST NCLK=/HCNF ZCMD=/XTRST XOUT=NVMD*HCNF*NINI*ND50+NVMD*HCNF*/NCE*ND50+ NVMD*HCNF*/NPRG*ND50+C3*/C1*/C0
;MDL file and et relying schema for 115200 baud USART implémentation and megabit synchronous link
IMPORTE TASCIA,RASCIA,BDT8S,REG8IO MODULE FLXPORTS(F8M,NRD,NWS,SIN,RAZ,SMOD,ETIM:NINIT,TBE,RBF,OK,IRQ,H16X) COMPOSANT X3020APC68 PLACE NRD=0,62,NWS=0,61,SIN=0,58,RAZ=0,9,SMOD=0,32,ETIM=0,3 PLACE NINIT.L=0,34,RBF.L=0,63,OK.L=0,30,TBE.L=0,28,IRQ.L=0,6,H16X.L=0,16 RASCIA(SMOD,F8M,H16X,F1,SIN,ZP,SEND:R7,R6,R5,R4,R3,R2,R1,R0,RCLK,ERR,HX,RBF) BDT8S(F8M:H16X,F1,H,INT) REG8IO(R7,R6,R5,R4,R3,R2,R1,R0,RCLK,NWS,NRD:C7,C6,C5,C4,C3,C2,C1,C0) TASCIA(SMOD,F8M,SIN,H,NWS,C7,C6,C5,C4,C3,C2,C1,C0:NDAT,TBE,SEND) NINIT=/NDAT*/SMOD+/SEND*/HX*SMOD+SEND*/NDAT*SMOD ZP=/NRD+RAZ IRQ=RBF+INT*ETIM OK=/ERR FINMOD Page Flexport num Jean Conter is assistant professor in the Data Processing and Applied Mathematics Department of the ENSEEIHT engineering school. Teaching domain: computer architecture. Research domain: smart sensors and dedicated systems in artificial vision VPCAB team.