APPLICATION Flexport : a remotely reconfigurable interface based on FPGA Jean Conter ENSEEIHT-IRIT 2, rue Charles Camichel 31071 Toulouse cedex [email protected] ABSTRACT. FPGAs are the key technology for improving computer architecture. These devices are generally used for computing purposes - so called virtual computing - but can also be employed to perform communication tasks. In this paper, we present an implementation of a remotely reconfigurable interfacing unit (RIU) based on the Xilinx SRAM FPGA technology. This generic approach can be seen as an effective alternative to classical USARTs and, by extending the reconfiguration process to the whole computer architecture, provides a solution for heterogeneous machine communication. RESUME. Le développement des FPGA engendre de nouvelles solutions dans le domaine de l'architecture des ordinateurs. Ces circuits sont en général employés pour réaliser des fonctions de calcul et de supervision- on parle alors de processeurs virtuels- mais ils peuvent également être utilisés dans des fonctions de communication; nous présentons dans cet article une expérience de réalisation d’interface reconfigurable à distance basée sur la technologie FPGA SRAM de Xilinx. Ce nouveau concept d’interface flexible peut se substituer avantageusement aux USART classiques et, en étendant la notion de reconfiguration à l’ensemble des parties constitutives de l’ordinateur, fournit une solution ouverte à la communication entre machines hétérogènes. KEY WORDS : flexible interface, generic serial I/Os, reconfigurable interfacing unit, universal serial link, FPGA remote configuration MOTS-CLES : interface flexible, entrées/sorties séries génériques, unité d’interfaçage reconfigurable, liaison série universelle, configuration de FPGA à distance. This article was originally published (in French) in Techniques et Sciences Informatiques. Volume 18 - n° 10/1999 Page Flexport num 1. Introduction FPGA's (Field Programmable Gate Arrays) have been commercially introduced by Xilinx in 1985. These circuits differ from PLD's (Programmable Logic Devices) by their internal architecture (Cf. figure 1), their density and their programming mode. In fact, as PLDs are essentially based on a two level of logic model (sum of products), FPGAs are more alike Gates Arrays, arrays of logic cells surrounded by IO cells. In a classical ASIC, the intra and inter cell links determine the circuit's functionality and this one is done at production time. In a FPGA, all cells and most of the links remain programmable after production : this post-programmation is called configuration. According to the technology, the user can configure the FPGA once (fuse, antifuse) or as many times as necessary (eeprom, sram). Configuration is done in parallel or serially from a configuration file called bitstream. In this article, we are particularly interested in SRAM technology, in which the bitstream is loaded into a static RAM (every bit determines the on/off status of each internal connection of the FPGA). No specialized device is needed to configure the FPGA with this technology. The debugging is also simpler due to the readback facility which enable to know the state of every internal node at a given moment. This technology is certainly the most flexible as the circuit's functionality can be changed as often as wanted, including when the FPGA is operating (dynamic reconfiguration). The advantages of this later concept is known for a long time [GRA 89] but rarely used in industrialized products. Nevertheless, the technology is confident and enables efficient solutions in various domains such as artificial vision [KEA 97]. For example, a camera with a build-in FPGA [CON 97] can identify shapes at a high rate while enabling, by a simple reconfiguration, various improvements (algorithmic change) without any physical modification on site : obsolescence of material is therefore avoided. The recent achievement of partially reconfigurable FPGA's (a part of the circuit can be modified without disruption of the whole circuit, which can be seen as hardware overlay) enforces the power of this concept. RPUs (Reconfigurable Processing Units) belong to this kind of FPGAs : combining power of processing and ease of use, they are perfectly adapted to experiments on evolutionist material [CON 98]. The design of a FPGA based system requires powerful CAD tools [LUD 97], yesterday mainly based on graphical description (schematic entry) making use of huge primitives libraries. More and more, dedicated logical description languages are used instead of the former graphical approach (VHDL [AST 96], JHDL [BEL 98], LOLA [WIR 96], MDL [CON 93]). Indeed, these languages offer better capabilities in terms of exchange, documentation, modification, modeling, verification, simulation and test. Flexport : a flexible interface on FPGA Pag e I2 I1 I0 I2 I1 I0 fixed OR prog. OR array array 6 8 programmable fixed AND AND array array (Ix represent optional FlipFlop O2 O1 O0 addresses) O2 O1 O0 PAL (GAL) architecture PROM architecture I2 I1 I0 prog OR array programmable AND array. I/O blocks Logic Block (CLB) (IOBs) interconnection Link O2 O1 O0 NB : IOB, CLB and Links are programmable PLA (FPLA) architecture FPGA architecture Figure 1. Simplified architectures of PLDs (PAL, PROM, PLA) and FPGAs Page Flexport num 2. A real world FPGA application When reconfigurable architectures are more and more involved for computing purposes [DEH 96, VUI 96] - 90 references in [GUC 99] - , they have been far less used in generic interfacing units. Beside solutions targeting parallel communication buses (PCI [XIL 95], PCMCIA or VME [HAU 95]), FPGAs can interestingly be used in simple serial links. Indeed, a vast majority of computers are equipped with asynchronous serial links, born at the beginning of computer ages. This mode of communication is simple and robust and, nevertheless exotic implementations (especially at the connector level), a 3 order of magnitude improvement in the data rate enables this standard to be compatible with the best analog modems at the time. Communication thru non guided Infrared links, available on most portable computers, telephones and data assistants, is in the direct continuation of the former serial links (newly available UARTs support at least the SIR protocol of the IRDA standard [TAJ 95]). However, in order to use more and more complex serial interfacing components, specific drivers are needed and make the programmer and final user task difficult (not less than 25 registers on the venerable Z8530). Furthermore, these asynchronous serial links have poor performances to fulfill the communication needs. More recently, fast serial links have been introduced : USB and IEEE 1394. These links offer real advantage compared to the former ones (more speed, hot-plug capability, multiple addressing, power thru the link,...) but also suffer some defaults (short distance, dedicated connectors, fixed communication protocol, durability : is USB necessary compared to IEEE 1394 ? ). FPGA components are a key solution for a more rational and efficient method : a true universal interface and its universal driver. REMARK. — We only consider here serial communication links between two points and will focus on Flexport, an experimental experiment for a virtual interface. 2.1. Main advantages of a reconfigurable interface 2.1.1. Universality A reconfigurable circuit can not only fit to all existing physical protocols but also to experimental ones, to-morrow standards : a simple configuration file gives the generic interface a new functionality. It is then possible to retrieve and process information coming from a remote control, a portable telephone (with an IR link) or from a PDA without needing to invest in a costly specific interface. Flexport : a flexible interface on FPGA Pag e 2.1.2. Flexibility In order to get a real flexibility of the material, its modification (by reconfiguration) must be possible not only from the host system but also from a distant one; thus, only one system is responsible for choosing the communication parameters (format, speed, mode, physical protocol). Therefore, a de facto compatibility can exist between heterogeneous equipments. 2.1.3. Simplicity Having a solution for the configuration process, there is no more need to know the details of the physical implementation in order to program the application : a single control/status register and a data register are only necessary to handle the transfer. If the allocation of each status bit is well defined, writing an universal driver is greatly simplified (for both a polling method or under interrupts). In the present implementation of Flexport, the restriction to 8 bits (with or without parity) addresses the problem of the eventual byte swap for larger busses. This restriction is not definitive. 2.1.4. Confidentiality If only one machine imposes its operating mode, specific coding schemes can be used in order to hinder every line interception (external protection) but also decyphering tentatives on the distant computer (internal protection). In fact, using always the same program or the same hardware to cypher/decypher data can be tampered (FPGA producers claim that it is impossible to disassemble a bitstream : that is not true, even if it requires a lot of effort). Using new and often changed cyphering methods, silently downloaded on the distant host, can certainly add more confidence for each transaction (Cf. figure 2). link interception can be possible non secured side interception can be possible