Autoplanarizing Process for the Passivation of an Integrated Circuit

Europaisches Patentamt J European Patent Office © Publication number: 0 655 776 A1 Office europeen des brevets

EUROPEAN PATENT APPLICATION

@ Date of filing: 30.11.93

@ Date of publication of application: © Applicant: SGS-THOMSON 31.05.95 Bulletin 95/22 MICROELECTRONICS S.r.l. Via C. Olivetti, 2 © Designated Contracting States: 1-20041 Agrate Brianza (Milano) (IT) DE FR GB IT @ Inventor: Cereda, Manlio Sergio Via IV Novembre, 7 I-20050 Lomagna (Ml) (IT) Inventor: Daffra, Stefano Via del Turchino, 21 1-20137 Milano (IT) Inventor: Stucchi, Elena Via Sabotino, 6 I-20047 Brugherio (Ml) (IT)

© In a passivating method using silicon oxidonitride, prior to forming that layer (10), the surface is planarized by overlying the circuit structures (2,3) with at least a first layer (8) of a dielectric material, and on top of this, a second layer (9) of a dielectric material. The layers have such thickness dimensions as to ensure planarization of the top surface. In addition, the invention may be used with a passivation method without oxidonitride wherein the underlying morphology is also planarized by forming FIG. - 3 those same dielectric layers.

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Rank Xerox (UK) Business Services (3. 10/3.09/3.3.4) 1 EP 0 655 776 A1 2

This invention relates to processes for forming moreover, by strain from external forces, as is planarized dielectric layers in the manufacture of likely to occur during the cutting process of the monolithic integrated circuits, and primarily to chip on which the circuit is fabricated for mounting methods for passivating an integrated circuit to a holder. Any areas where the layer is cut or wherein layers of silicon oxidonitride have been 5 caused to part from the circuit structures it ought to specifically formed. protect, are bound to admit moisture into the struc- It is known that dielectric material layers, either tures, thereby harming the quality of the passiva- interposed as inter-metal passivation layers be- tion. tween conductive layers or provided as final pas- As the skilled ones are well aware, to ensure sivation coats over the last metallization layer, io good passivation of devices assembled within plas- serve a dual function of electric insulation and of tics packages, two-layer process schemes have protection for the underlying structures of the in- long been adopted in practice whereby the ox- tegrated circuit from contaminants (impurities, idonitride is associated with PSG (Phosphorus Sili- moisture) or shocks. con Glass), a silicon oxide doped with phosphorus. It is common practice in the pertinent art to 75 PSG forms a good barrier to contamination, mainly assemble integrated circuits within plastics pack- from sodium, and is adequately impervious. ages on account of these being economically more In past practice, the oxidonitride used to be favorable. Most EPROM (Erasable Programmable placed directly over the circuit structures to be Read-Only Memory) volatile storages, whether non- insulated. This layer was then overlaid with a coat erasable such as OTP (One Time Programmable) 20 of PSG. The latter acts to protect the oxidonitride, EPROMs or electrically erasable ones (EEPROMs, which is crumbly in nature, against scratches, such Flash EEPROMs), come indeed encapsulated with- as may harm its integrity and occur during the final in plastics materials. device encapsulating steps, for example. A major These devices must be provided better resis- problem with that arrangement is that the ox- tance to moisture and contamination from outside 25 idonitride deposited directly over the circuit struc- sources than products which are assembled within tures is generally to rest on a fairly irregular con- ceramic packages inherently affording adequate tour surface. Thus, the oxidonitride develops weak- protection. The porous nature of plastics materials ening spots which may readily crack. This problem makes them pervious to impurities and moisture, in may result in the device failing to pass its Pressure fact. Additionally, the circuit assembly process, 30 Pot Test (PPT). With the current trend toward in- which includes heat application, followed by cool- creased miniaturization of the circuits, the problem ing, to the resin comprising the package and con- is made more serious by the denser structures and sequent release of moisture therefrom, does favor attendant reduced spacing of the metallizations, as the intrusion of water into the circuits. Any water well as by the larger number of conductive levels. coming in contact with the conductive layers may 35 Such trend does involve an expansion of the critical corrode them or at least make the integrated circuit areas. unstable and imperil its operation. It has been shown experimentally that in order As the persons of skill in the art are well aware, to improve the reliability of EPROM storage cells the most suitable material to provide such protec- encapsulated within plastics packages under vapor tion is silicon oxidonitride (SixOyNz), wherein the 40 stress, it is of paramount importance that the pas- elements may be present in varying proportions, sivation layer ability to cover and seal off the and which in the extreme instance of oxygen being underlying structures be significantly enhanced. altogether absent, would become silicon nitride, These findings have been confirmed by I.S. Gaeta Si3N4. and K.J. Wu in an article "Improved EPROM mois- Oxidonitride is endowed with excellent impervi- 45 ture performance using Spin-On Glass (SOG) for ousness and retains good UV transmissivity, which passivation planarization", IEEE/IRPS, 1989, pages properties allow it to be used for UV erasable 122-126. storages. Accordingly, it is common pratice to use In this direction, the passivation technology ef- it in the final passivation layer. forts are mostly aimed at making the oxidonotride On the other hand, the oxidonitride in film form 50 substrate as planar as possible. In prior art meth- is characterized by poor step coverage, i.e. low ods, as disclosed in the above-referenced article, a ability to spread smoothly over so-called stepped resin, specifically SOG (Spin-On Glass) has been surfaces and thereby thoroughly cover the under- used for planarization purposes which is a sacrifi- lying surface and retain a conforming pattern with cial organic polymer material commonly used as a the structure beneath. It is therefore prone on 55 planarizer in several steps of the integrated circuit breakage at the morphologically most critical points manufacturing process. With that technique, the of the circuit, where uneven spots are apt to appear oxidonitride potential breakage spots can be mini- in its thickness. Such breakage may be promoted, mized because it is no longer subjected to stresses

2 3 EP 0 655 776 A1 4 from the underlying structure. thoroughly insulated, and constitute the roughest The net outcome is a passivation with greatly regions on the circuit surface. improved coverage. Devices on which it had been The most basic of passivations using ox- used have performed successfully on wet testing. idonitride is that shown schematically in Figure 1 . A However, with the above method, the improved 5 layer 4 of oxidonitride is formed directly over the passivating efficiency is paid for by increased com- structures. The top layer 5 is usually comprised of plexity, and this reflects unfavorably on production PSG. As can be seen in the figure, the oxidonitride costs. shows slendering areas in its thickness at the bot- It is an object of this invention to provide a tom of the metallization levels (hatched areas 6) passivation method of low complexity, but affording io due to very poor coverage, which would bring a good degree of reliability, especially in the in- about the previously outlined problems. stance of plastics packaged integrated circuits and Passivation of this circuit structure with SOG more particularly of those ICs whose passivation planarization added is illustrated in Figure 2 and provides for an oxidonitride layer. described in the aforementioned article, for exam- Another object, closely related to the one 15 pie. The passivation step is commenced by first above, is to lower the cost of devices to be imple- forming an oxidonitride layer 4' directly over the mented using that technique. circuit structure. The whole surface is then covered A further object is to provide such a method with SOG; the layer formation is typically effected which can be readily applied to other passivation by depositing the material in liquid form onto the steps as well. 20 circuit and then causing it to spread evenly by According to the invention, in a passivation spinning the chip that carries the circuit, in accor- method using silicon oxidonitride, prior to forming dance with a well known technique. The SOG will this layer, the surface is planarized by overlying fill the deeper areas completely and make its top the circuit structures with at least a first layer of a surface planar. A subsequent plasma etching step dielectric material topped by a second (optional but 25 will only leave SOG residue (shown at 7 in the provided in the preferred embodiment) layer of a drawing figure) to fill the gaps between upstanding dielectric material. The layers have thicknesses ef- structures. fective to ensure planarization of the top surface. This material must be then allowed to cure The method may be applied in particular to circuits under heat application. Over the planarized mor- enclosed within plastics packages. This passivation 30 phology, a second layer 4" of oxidonitride may be may also be used, however, with devices not en- deposited. Thereafter, a protective finishing layer 5 capsulated in plastics packages, possibly without of PSG is deposited. The oxidonitride forming the forming the final layer of oxidonitride. According to single layer 4'-4" is now planarized, and no break- the invention, moreover, in a method of intermetal ages will occur during passivation. Although effec- passivation, prior to forming a metallization layer, 35 tive, this technique comprises a significantly large the underlying morphology is planarized, again by number of processing steps. formation of the same dielectric layers as above. Illustrated in Figure 3 is a passivation method The invention and its advantages will be more using oxidonitride according to a preferred embodi- clearly apparent from a detailed description of a ment of this invention. The passivating step in- specific method based on its principle, as given 40 eludes formation of the oxidonitride only after the herein below by way of non-limitative example with surface with which it is to come in contact has reference to the accompanying drawings, in which: been planarized. Planarization is carried out by Figure 1 is a sectional view of structures which forming layers of dielectric materials over the cir- have been integrated using a conventional pas- cuit structures 2, 3. In an improved embodiment of sivation scheme; Figure 2 is a sectional view of the 45 the invention, the passivating step begins with the same structures as integrated using a passivation formation of a layer 8 of a dielectric material. It scheme with conventional planarization; and Figure should be noted that, while the dielectric 8 has 3 is a sectional view of the same structures as been shown as a single layer in the drawing figure, integrated using a passivation scheme according to this could actually include a number of superim- one embodiment of this invention. 50 posed layers. Subsequently in the preferred pro- In the drawing figures, integrated structures to cess, a second layer 9 of a dielectric material is be insulated, shown at 2 and 3, are formed on the formed on top of this which may also consist of surface of a body of a semiconductor material 1, multiple layers. This second dielectric material, in such as monocrystalline silicon. These may be accordance with the invention, so spreads out as to storage cells of the high-density EPROM type, and 55 produce a planarized free surface of the layer 9. are shown identical through all the drawing views This stage of the process may be followed by the for convenience of illustration. The layers 3 repre- formation of the silicon oxidonitride layer 10 to sent metallization paths. The latter require to be thereby complete the passivation. The oxidonitride

3 5 EP 0 655 776 A1 6 overlies, according to the invention, a flat morphol- the second dielectric material. In fact, it can spread ogy and undergoes, therefore, no stresses during out over the roughest of morphologies in a non- its deposition. Planarization is ensured, in the pre- conforming but profile-smoothing fashion. The film ferred embodiment, by the provision of both dielec- properties, in particular its capability to conform, tric layers. The first layer is effective to narrow the 5 are defined by the deposition method and specifi- gaps between any two adjacent structures in the cally by its phosphorus content, with a higher circuit, the metallization paths in the example phosphorus content resulting in reduced step cov- shown. In this way, the morphology of the circuit erage. surface is initially made smooth. The second layer On the other hand, the dopant content should completes the planarization by providing a suffi- io be lower than 7% to prevent incidental formation, cient thickness to produce a substantially planar due to moisture penetration, of phosphoric acid top surface. which would attack the metallizations. Preferably, It should spread out so as to meet over the the amount used in this invention is in the 5% areas between circuit structures, representing mor- range, which agrees with the prior art. phologic depressions, and seal them off at least is In practice, passivation is best provided by the upwardly. The film features need not be such that first or filler layer, having a smaller thickness than it will fill the areas between structures completely. the second which is intended to provide planariza- As shown in Figure 3, some voids may be left in tion properly. A ratio of the two dielectrics in the the depressions. To achieve true planarity, a care- range of about 1 :2 represents a good value for this ful selection of the dielectric thickness dimensions 20 invention and is applicable to several products. is instead essential. Such thickness dimensions are With devices and architectures currently employed closely tied to the dimensions of the device. In the today, where a dual layer of USG-PSG is used, specific instance of EPROM storages, account optimum thicknesses for these dielectrics are 5000 should be taken of the architecture of the individual Angstroms for USG and 8000 Angstroms for PSG. cells, the metal-to-metal distance, and the metal- 25 To form the oxidonitride, conventional tech- on-contact overlap. Proper consideration should niques may be used which are available from lit- also be given to the processing steps which pre- erature and need not be discussed in detail herein. cede passivation and affect the circuit structure This is customarily deposited, as is well known to shape, such as the metal profile after etching and the skilled ones, in a PECVD (Plasma Enhanced the shape of the underlying dielectric. Optimum 30 CVD) reactor. thickness dimensions can be found by calculation It should be noted that the absence of a pro- for individual devices. tective top coat on the oxidonitride ~ as is instead In a preferred embodiment, the first layer com- provided in the prior art (the PSG layer itself being prises deposited oxide, usually undoped silicon used for the purpose) ~ does not harm the device dioxide. The latter is known in the art as USG 35 performance because the likelihood of the pas- (Undoped Silicon Glass). This formation is obtained sivation integrity becoming affected is quite small. using a conventional CVD (Chemical Vapor Deposi- The mere reversal in the formation of the PSG and tion) technique. The layer properties will depend on oxidonitride layers provided by the invention, on the technique used, in particular on such physical the other hand, allows the same combination of parameters as deposition pressure and tempera- 40 dielectric materials to be used which has long ture, on the one side, and its chemical precursors, proved effective to form a barrier to external on the other. A film having satisfactory step cov- agents. erage properties to ensure conformity with the un- The reliability of the passivation process de- derlying circuit structure is preferred, although this scribed above has been demonstrated experimen- is no essential prerequisite. 45 tally in the course of wet tests. The better the step coverage property, the It has proved excellent for devices enclosed in lesser will be the layer thickness needed to reduce plastics packages. the gaps between adjacent structures, in fact. The effectiveness of this solution is quite high Preferably, the second dielectric comprises in- for structures to be passivated whose morphologies stead a doped oxide, in particular silicon oxide 50 include fairly closely spaced elevations. In such doped with phosphorus, namely PSG, which is cases, in fact, the PSG layer would better cover the commonly deposited using a CVD technique. As depressions without suffering breakages. In view of previously mentioned, it has been used in the prior the trend toward increased miniaturization, and art for final passivation purposes, as well as in hence denser structures, in today's technology, the other insulating operations during the manufacture 55 invention can be used to even greater advantage. of an integrated circuit, because of its capability to The method of this invention has an additional form a barrier to contaminants. In the process of advantage in that it is uncomplicated. this invention, PSG represents a good choice for

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The number of its processing steps can be ming said silicon oxidonitride layer, at least a small, in the extreme as small as three, i.e. just the first layer of a dielectric material is formed dielectric and oxidonitride layer depositions. Fur- over at least portions of said structures, the thermore, it may be called "self-planarizing" in the thickness of said layer being adequate to pro- sense that no external arrangements are required 5 duce a top surface of the layer which is for planarizing the passivation layers. No sacrificial smooth and substantially planar. materials are used, the formation and subsequent etching whereof would contribute, inter alia, to the 2. A method according to Claim 1, characterized process complexity. On this account, the produc- in that the first layer of dielectric material is a tion cost of devices processed with this method io silicon oxide. can be kept low. Additionally, the procedures and materials used 3. A method according to Claim 2, characterized are those already known in the art, so that no in that the silicon oxide is doped with phos- special equipment must be made available to im- phorus (PSG, Phosphorus Silicon Glass). plement the invention. 15 It may be appreciated that the embodiment 4. A self-planarizing method for passivating with form described in detail hereinabove, in connection silicon oxidonitride an integrated circuit defined with devices assembled within plastics packages on a surface of a body of semiconductor ma- requiring passivation with oxidonitride, may be terial, comprising the formation of a silicon adapted for passivation without oxidonitride by 20 oxidonitride layer over integrated structures of merely omitting the final step of oxidonitride forma- said circuit, characterized in that, prior to for- tion. ming said silicon oxidonitride layer, a first layer The method of this invention may also be of a dielectric material is formed over at least applied, in another preferred embodiment thereof, portions of said structures and at least a sec- to the intermetal passivation step. The planarizing 25 ond layer of a dielectric material is formed dual layer would be similar to the one described, over at least part thereof, the combined thick- except that a metallization layer would be formed ness of the layers being adequate to produce on top after exposing the contacts by etching away a top surface of the second layer which is the dielectrics. smooth and substantially planar. Furthermore, successive metallization levels 30 may be formed sequentially to both encompass the 5. A method according to Claim 4, characterized planarized passivation of this invention and an in that the first and second layers of dielectric overlying conductor layer. Each metallization level material comprise silicon oxides. would then be made available a planarized dielectric substrate of its own. This would be an excellent 35 6. A method according to Claim 5, characterized form of passivation for plastics packaged circuits in that the first oxide layer comprises undoped as well. silicon oxide (USG, Undoped Silicon Glass). It could be used, for example, in combination with the previous embodiment, with the oxidonitride 7. A method according to either Claim 5 or 6, only formed over the last metallization level. 40 characterized in that the second oxide layer is Finally, it should be appreciated that in applica- a silicon oxide doped with phosphorus (PSG). tions of the present invention, the planarizing dielectric layers may be reduced to just one, having 8. A method according to Claim 7, characterized a thickness equal to the combined thicknesses of in that the amount of phosphorus is about 5%. the two dielectric layers. It could either be a single 45 layer of PSG or USG. 9. A method according to any of Claims 4, 5, 6, 7 In the extreme, the dielectric layers for or 8, characterized in that the thickness of the planarization could be only provided in the mor- second layer is approximately twice that of the phologically most critical areas. first layer. 50 Claims 10. A method according to Claim 9, characterized in that the thicknesses of the first and second 1. A self-planarizing method for passivating with layers are about 5000 and 8000 Angstroms, silicon oxidonitride an integrated circuit defined respectively. on a surface of a body of semiconductor ma- 55 terial, comprising the formation of a silicon 11. A self-planarizing method for passivating with oxidonitride layer over integrated structures of silicon oxidonitride an integrated circuit defined said circuit, characterized in that, prior to for- on a surface of a body of semiconductor ma-

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terial, characterized in that it comprises the steps of forming, over at least portions of integrated structures of said circuit, at least a first layer of a dielectric material, and at least a second layer of a dielectric material over at 5 least part thereof, the combined thickness of the layers being adequate to produce a top surface of the second layer which is smooth and substantially planar. 10 12. A method according to Claim 11, characterized in that the first and second layers of dielectric material comprise silicon oxides.

13. A method according to Claim 12, characterized is in that the first oxide layer comprises silicon oxide (USG) undoped with other elements.

14. A method according to either Claim 12 or 13, characterized in that the second oxide layer is 20 a silicon oxide (PSG) doped with phosphorus.

6 EP 0 655 776 A1 Patent Application number European EUROPEAN SEARCH REPORT Office EP 93 83 0480

DOCUMENTS CONSIDERED TO BE RELEVANT Citation of document with indication, where appropriate, Relevant CLASSIFICATION Or THIS, Category of relevant passages to claim APPLICATION (lnt.Cl.6) JS-A-5 077 238 (A. FUJI I ET AL.) L-7, H01L21/314 Ll-14 H01L21/90 * column 4, line 49 - column 6, line 9 * figures 1A-1J * * claims 1,3-6 * A 10

A rfO-A-91 09422 (MITEL CORP) L, 2,4-6, Ll-13 * * page 5, line 29 - page 6, line 17 * claims 1,17 *

JS-A-5 003 062 (D.L.YEN) 1,2,4-7, J, 11-14 * column 3, line 45 - line 52 * * column 5, line 47 - column 6, line 34 *

TECHNICAL. FIELDS SEARCHED (Int.Cl.6) H01L

The present search report has been drawn up for all claims Place of March Dale of completwa of tie iearcb THE HAGUE 19 April 1994 Schuermans, N CATEGORY OF CITED DOCUMENTS T : theory or principle underlying the invention E : earlier patent document, but published on, or X : particularly relevant if taken alone after the filing date Y : particularly relevant if combined with another D : document cited in the application document of the same category L : document cited for other reasons A : technological background O : non-written disclosure & : member of the same patent family, corresponding P : intermediate document document