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And N-Mosfets Fabricated with Novel Surface Passivation

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And N-Mosfets Fabricated with Novel Surface Passivation Germanium'p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AIN) and TaN/HfOz Gate stack S. J. Whang, S. J. Lee, Fei Gao, Nan Wu, C. X. Zhu, Ji Sheng Pan ', Lei Jun Tang *, D. L. Kwong Silicon Nan0 Device Lab., Department of Electrical and Computer Engineering National University of Singapore, IO Kent Ridge Crescent, Singapore, 1 19260, Email; elelsi(iirnus.edu.sg ' Institute of Materials Research and Engineering, Singapore . ' Institute of Microelectronics, Singapore ' Department of Electrical and Computer Engineering, University of Texas Abstract passivation on Ge-substrate using TaN/Hf02 gate stack. The plasma-PH, and thin A1N as a surface passivation method Ge-MOS devices (EOT - 7.5 A, J, - IO" Ncm') are between high-K film and Ge substrate-were used in this fabricated on both n- & p-type Ge-substrates, using novel experiment. surface passivation and TaN/HfOz gate stack. Results show that the plasma-PH, treatment and thin AIN layer at Hf02/Ge Experiments interface are effective to suppress the GeO formation, which is mainly formed during HfD2 deposition, and prevent Ge Several passivation processes are employed on DHF- out-diffusion, resulting in improved C-V characteristics for n- cleaned both n-type (- 0.5 R.cm) and p-type (- 0.1 Ran) MOS device with extremely low leakage. Ge-substrate prior to HfOl deposition; plasma-PHs treatment Thermal stability study of TaNMf02/Ge gate stack shows at 400 "C, thin AIN (- IO A) by reactive sputtering of AI and that low leakage with thin EOT can be obtained after post- N2, TN (Thermal Nitridation) in NH, at 600 "C. HfOz is anneal at 500 "C and degradation is observed above 600 "C. deposited by both MOCVD (Hf(OC(CH3)3)4+02) and ALD It is also observed that good Ge nt-p and pi-" diode (HfCb+H,O), followed by PDA (Post-Deposition Anneal) at characteristics are achieved by S/D activation at 500 "C and 400 "C. Reactive sputtered -150 nm TaN was used as gate 400°C, respectively. Both p- & n-MOSFETs are fabricated by electrode. After gate etching, RTA (Rapid Thermal Anneal) conventional self aligned process with maximum temperature was done at various temperatures for thermal stability study. of 500 "C. Compared to reported Si-MOSFETs, the mobility MOSFETs are fabricated with conventional self-aligned enhancement of 1.6X for hole and 1.8X for electron is process, SourceiDrain was implanted with Phosphorus (n- observed with Ge-MOSFETs. MOS) and Boron (p-MOS) and activated at 500 OC and 400 "C, respectively. Introduction Results and Discussion Ce has recently regained considerable attention, since Ge can provide solutions for major roadblocks that Si technology The measured high-frequency C-V and simulated low- is facing for advanced CMOS devices. This is mainly due to frequency C-V characteristics of n-MOS TaN/HfOz/Ge gate the higher mobility of both electron and hole in Ge-substrate, stack with plasma-PHs treatment are shown in'Fig. 1. EOT of and the ability to deposit high-K dielectrics overcoming the 7.5 A is achieved from simulated C-V with extremely low issue of the absence of stable Ge oxide. Several promising leakage of J, - IO" A/cm2 at V, - VFB = -1 V, along with results have been reported for Ge MOSFETs using GeON [I]. excellent agreement of HFCV and LFCV, indicating high ALDZIQ [2],ALD Hf02 [3],and CVD HfD2 [4]. quality of TaN/Hf02/Ge stack. The HFCVs of Ge p-MOS and Thermal nitridation on Ge-substrate prior to high-K n-MOS capacitors with various surface passivations are deposition has been introduced to improve film quality [2,4]. compared in Fig. 2. As can be seen in Fig. 2a and reported in However, the EOT range of previous works is quite thicker [3, 41, for p-MOS device; the TN Ge-substrate is effective to than the requirement of ITRS roadmap for sub-65 nm improve interface quality. Similar effects are observed for technology. Moreover, most of studies have focused on p- plasma-PHs and AIN treated samples. However, for n-MOS MOS devices without successful demonstration for n-MOS capacitor, the anomalous C-V still cannot be solved with TN devices with EOT less than 20 A. In this work, we developed treatment (Fig. 2b), which is attributed to the formation of and investigated ultra thin EOT (< 10 A) both p- & n-MOS poor-quality unstable oxide. at interface [3, 41 and/or out capacitors/MOSFETs fabricated with novel surface diffusion of Ge [5]. By adopting the Ge-substrate 12.6.1 0-7803-8684- 1/04/$20.00 02004 IEEE IEDM 04-307 passivations with plasma-PH, and AIN layer treatments, for p+-n diode, it is found that the best reverse and forward much improved C-V characteristics without surface state- currents can be obtained after FGA at 400 “C. Based on these related inversion capacitance are obtained. thermal stability results, both p- & n-MOSFETs are XPS analyses of HD2/Ge gate stack with different fabricated by conventional self aligned process with passivations are shown in Fig. 3. First, a Ge 3d spectra in Fig. maximum temperature of 500 “C. Both p- & n-MOSFETs 3a indicates that the GeO is formed mainly during the HD2 exhibit well-behaved Io-VD characteristics (Fig. 1I). Sub- deposition process, and a little increase after PDA. From P 2p threshold swings of 97 mV/dec and 89 mV/dec are obtained spectra in Fig. 3b, the P-0 bond is observed after plasma PHI for p- & n-MOSFETs (Fig. 12). Calculated electron and hole treatment on Ge. As a result, as confirmed in convoluted 0 Is mobility as a function of effective field are shown in Fig. 13. spectra in Fig. 3c, less GeO is formed, compared to TN Ge. Compared to reported Si-MOSFETs [6], 1.6X and 1.8X For AIN-passivated Ge, Fig. 3d shows that A1N is changed to increase in hole and electron peak mobility are observed AI0 after HD2 deposition, which also results in significant suppression of GeO formation, compared to TN (Fig. 3e). Conclusions TEM pictures of plasma-PH, and AIN passivated TaN/Hf02/Ge stacks are shown in Fig. 4. Both samples exhibit very thin (- 5 A) interfacial layer under conformal We demonstrate Ge p- & n-MOS devices (EOT - 7.5 A, Hf02 films which remain amorphous, and no out-diffused Ge I, - IO” A/cm2) fabricated with plasma-PH, and AIN surface is detected in Hf02 layer after 500 “C PDA, from EDX passivation, and using TaNMf02 gate stack. It is found that analysis in Fig. 5. the surface passivation with plasma-PH, treatment and thin AIN layer at Hfl),iGe interface are effective to suppress the The leakage currents of Ge-MOS devices are plotted as a GeO layer and prevent Ge out-diffusion, resulting in function of EOT, and compared with reported results (Fig. 6). improved interface quality for n-MOS device with extremely Plasma-PH, passivated Ge devices demonstrate lower low leakage. In addition, thermal stability study shows that leakage at the EOT range of 7.5 - 17 A, which is comparable the hest EOT with low leakage current and good SID to TaNIHfN/HfD2/Si gate stack [6]. Surface roughness activation characteristics can be obtained by post-anneal at measured by AFM shows no significant increase in RMS 500 OC for n-MOS and 400 “C for p-MOS devices. value after plasma PHI treatment on Ge-substrate (Table 1). Enhancement of bole (1.6X) and electron mobility (1.8X) However, the calculated Dit of Ge n-MOS devices are 8x10” was observed, compared to Si-MOSFETs. - lx1012cm.’.eV-’ (Table 2), implying that more interface engineering work is required. Thermal stability of TaNMfOiGe stack is studied by References examining C-V and leakage current after FGA (Forming Gas Anneal) at 400 “C, followed by postlanneal at various (I) H. Shang, et al., “High Mobility pchannel Germanium MOSFETs with a temperatures (Fig. 7). EOT and VFe remain stable up to 500 Thin Ge Oxyniuide Gate Dielectric,” IEEE lEDM2002 Technical Digerr. “C, 2 min anneal. However, as annealing temperature pp. 441444,2002. increases, VpBshift and EOT increase is observed, due to the (2) C. 0.Chui, et al., “A SuMOOC Germanium MOSFET Technology with High-k Dielecuic and Metal Gate,” IEEE IEDM 2002 Technical Digerr, interfacial layer growth, which also results in leakage current pp, 437440,2002. increase caused by the poor quality GeO [3, 51. Fig. 8 shows (3) C. 0. Chui, H. S:Kim, P. C. McIntp, and K. C. Saraswat, “A EOT and J, as a function of annealing temperature for Germanium NMOSFET Pracess Integrating Metal Gate and Improved different surface passivations. TN-treated device show more Hi-k Dielecmcs,”lEEEIEDM2003 Technieol Digert, pp. 43740,2003. (4) W. P. Bai, et al., “Ge MOS Characteristics with CVD HtQ Gate severe increase of leakage after 600 “C anneal. However, Dielectrics and TaN Gate Electrode,” VLSI Technology 2003, pp. 121- EOT and leakage of plasma-PH3 treated device shows 122,2003. negligible dependence on post-annealing time up to 10 min at (5) K. Kiq M. Sasagawa, K. Tamida, K. Kpno and A. Tonumi, 500 “C (Fig. 9). “Oxidation-Induced Damages on Germanium MIS Capacitors with HR)2 Gate Dielectrics,” SolidStaie Doricer and Moleriols, pp. 292-293,2003, One of the major advantages of Ge-MOSFET is the low (6) H. Y. Yu, et al., “Thermally Robust High Quality Hf”f02 Gate Stack for Advanced CMOS,” IEEE IEDM2003 Technical Digest, pp, 99-102, temperature SID activation, which will mitigate the thermal 2003.
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