Cell Library Creation Using ALF

Journal of Computing and Information Technology - CIT 13, 2005, 3, 235–245 235 Cell Library Creation using ALF Assim Sagahyroon1 and Maddu Karunaratne2 1 American University, Sharjah, UAE 2 University of Pittsburg, Johnstown, Pennsylvania The design of Integrated Circuit ASICs and SoCs typi- In this deep submicron era, an increasing num- cally relies on the availability of a library consisting of ber of effects that were previously insignificant predefined components called technology cells. Silicon vendors use proprietary formats to describe technology are becoming first order and can no longer be cells and macro modules in conjunction with numerous ignored in present day IC design requirements. translators to feed technology library data to Electronic The complex, second-order effects for new sub- Design Automation EDA tools. Multiple grammar formats are used to represent various aspects of the wavelength nanometer processes residence, in- cells in the same technology library, such as behavior ductance, crosstalk, leakage, electromigration, for simulation, timing parameters for synthesis, physical etc. are modeled in abstraction, mostly for the data for layout, noise parameters for signal integrity checks, etc. In addition, most of these formats are highly physical layer. This results in additional number tool-oriented and are not grammatically consistent. In of design iterations that may be required in or- this paper we will discuss the newly adopted IEEE der to fix problems found very late in the design 1603–2003 Advanced Library Format ALF standard which eliminates such drawbacks. This standard defines cycle. Therefore it is becoming much more a grammar for accurate and comprehensive modeling difficult to design in the nanometer era whilst of technology libraries and macro modules in order maintaining expected performance, power sta- to bridge the growing gap between new design rules tic and active, area, design cycle time, man- and the analysis required for complex high-end IC implementations. ufacturability and cost scaling. These effects need to be dealt with at all levels: technology Keywords: ASIC, SoC, Technology Cells, Advanced process, data extraction and library modeling, Library Format ALF . logic synthesis, circuit design, place and route, clock distribution, verification, and final test and assembly. Therefore, architecting a technology cell library with these effects in mind can 1. Introduction help reduce their adverse impact on chip design 2 . Designing integrated circuits ICs and System Traditionally, design rules and high margins on Chip SoC using 0.18-micron and smaller process technologies pose tremendous challen- have been used in practice so far in IC designs ges for design teams. Perhaps the most signifi- to protect and to avoid dealing with signal in- cant problem with existing design environments tegrity issues such as crosstalk noise, electro- is that power, timing, and signal integrity ef- migration, hot electron and antenna effects, etc. fects are strongly interrelated in the nanometer Therefore, ASIC design flow has been mostly domain, but conventional point-solution design focused on achieving the steps of RTL Design tools do not have the capability to consider all Closure, Functional Verification and Test, and of these effects and their interrelationships con- Timing Closure during physical implementa- currently. For example, the number of silicon tion. These goals are almost always achieved in failures caused by signal integrity problems is several iterations, from logic synthesis to lay- on the rise due to the lack of existing design out steps. As the semiconductor feature size tools and methodologies that can address these reduces towards 90nm and below, such prac- issues effectively 1 . tices would not help to exploit the efficient use 236 Cell Library Creation using ALF of available technology for competitive advan- into a Register Transfer Level RTL descrip- tage. Moreover, with supply voltages reducing tion. At this level, the design is described as to one volt or less, voltage drops due to high a dataflow model that will implement the in- switching currents would cause unexpected sig- tended digital circuit. That is, this level con- nal delays in critical circuit areas. Such issues sists of components and their interconnections. need additional point tools to analyze them and Logic synthesis tools are then used to convert safeguard the designs by applying incremental the RTL description to a gate-level netlist. In changes during design and physical implemen- essence, the gate-level netlist is a technology- tation phases. Unless the analysis and repair independent description of the circuit in terms capabilities are combined into the same EDA of a netlist of standard cells such as gates, tool, for high-end designs in SoC domain, the flip-flops, latches, and sometimes multiplexors, iterative process of analysis and repair of sig- counters and interconnections between them. nal integrity violations become inefficient. In The synthesis tool ensures that the generated general, the quality of results depends on the netlist meets timing, area and power specifica- quality of the analysis models that are provided tions. The process of transforming this generic to the tool. A case in point, for signal noise and cell-based logic network into a vendor-specific electromigration, there was no library model- network is known as library binding or tech- ing language available in the industry that could nology mapping. The library contains a set of represent the characterization data. ALF IEEE parameterized technology cells. These cells are standard 1603–2003, approved Sept. 2003 is usually provided with their physical layout, tim- the only standard language available to model ing models, behavioral models, etc. The netlist such details and essential information into tech- is then input to an automatic Place and Route nology cell libraries and macro modules. Other tool to generate the physical layout. The layout modeling languages, though none of them are is verified and then fabricated as an IC chip. IEEE standards, are being enhanced to accom- modate such information to be in par with ALF. At present, ALF is the only available indus- 3. Technology Cell Libraries try standard that can describe not only timing, power and noise, but also electromigration, hot Design approaches can generally be classified electron, antenna and other factors in consistent into custom and semi-custom designs. Com- and comprehensive formats. pared to the custom design approach, the com- plexity and cost of designing an IC is greatly reduced in the semi-custom design approach. 2. IC Design Flow The semi-custom designs use predesigned technology cells and much larger macro mod- In this section, we will briefly describe a typi- ules that are usually optimized, well-designed, cal design flow for ASIC and IP modules. For a and well-characterized. EDA tools are used by comprehensive discussion of this flow, readers designers to choose among the various available cellsmodules and to interconnect them are referred to 3 . to achieve the desired design functionality and The design flow begins with a behavioral spec- performance. Semi-custom designs can fur- ification of the design. The specification doc- ther be subdivided into two categories: array- ument can be an elaborate document that in- based design and cell-based design. Array- cludes delay, area and power constraints, and based designs use a prefabricated matrix of non- other criteria that might govern the design. At connected components named sites; these sites the behavioral level, we are modeling function- are then interconnected to create a circuit with ality of the design in the form of an input-output the desired functionality. This paper is mainly model that suppresses the details about gate and concerned with semi-custom design that is cell- physical level implementations. At this stage, based, for a detailed discussion of array-based the intended input- output relationship can be design, readers can refer to 4 . Cell-based de- verified using functional simulation. Next, ei- signs use libraries of predesigned cells. These ther a Behavioral Synthesis tool or a human cells can be characterized and optimized for the designer transforms the behavioral description different process technologies that the library Cell Library Creation using ALF 237 targets. Each cell in the library is typically pa- ALF, contrasting formats had to be used to rep- rameterized in terms of area, delay, and power. resent the same technology cells to suit different In cell-based designs, engineers can use stan- applications, even from the same EDA vendor. dard cells andor macro cells. Examples of For example: A technology library is described standard cells are basic logic gates such as in- as a logic library and a physical library. An ex- verters, NAND gates and NOR gates. Examples ample of such a commercially available library of macro cells include memories and complex is the Synopsys technology library 5 . This li- datapath components such as adders and multi- brary can be categorized into two libraries: a pliers. logic library and a physical library. The logic Each cell in an ASIC library must contain at library contains information relevant only to the synthesis process and is used for synthesis and least the following information 3 : design optimization. This information includes A circuit schematic pin-to-pin timing, area, pin types and power; A physical

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