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Prostep Ivip CPO Statement Template
CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of -
Digital Systems Modeling Chapter 2 VHDL-Based Design
Digital Systems Modeling Chapter 2 VHDL-Based Design Alain Vachoux Microelectronic Systems Laboratory [email protected] Digital Systems Modeling Chapter 2: VHDL-Based Design Chapter 2: Table of contents ♦ VHDL overview ♦ Synthesis with VHDL ♦ Test bench models & verification techniques A. Vachoux, 2004-2005 Digital Systems Modeling Chapter 2: VHDL-Based Design - 2 A. Vachoux 2004-2005 2-2 Digital Systems Modeling Chapter 2: VHDL-Based Design VHDL highlights (1/2) ♦ Hardware description language • Digital hardware systems • Modeling, simulation, synthesis, documentation • IEEE standard 1076 (1987, 1993, 2002) ♦ Originally created for simulation • IEEE standards 1164 (STD_LOGIC) and 1076.4 (VITAL) ♦ Further adapted to synthesis • Language subset • IEEE standards 1076.3 (packages) and 1076.6 (RTL semantics) A. Vachoux, 2004-2005 Digital Systems Modeling Chapter 2: VHDL-Based Design - 3 A. Vachoux 2004-2005 2-3 Digital Systems Modeling Chapter 2: VHDL-Based Design VHDL highlights (2/2) ♦ Application domain (abstraction levels): Functional -> logic ♦ Modularity • 5 design entities: entity, architecture, package declaration and body, configuration • Separation of interface from implementation • Separate compilation ♦ Strong typing • Every object has a type • Type compatibility checked at compile time ♦ Extensibility: User-defined types ♦ Model of time • Discrete time, integer multiple of some MRT (Minimum Resolvable Time) ♦ Event-driven simulation semantics A. Vachoux, 2004-2005 Digital Systems Modeling Chapter 2: VHDL-Based Design - 4 A. Vachoux 2004-2005 2-4 Digital Systems Modeling Chapter 2: VHDL-Based Design VHDL-based design flow Editor (text or graphic) Test bench models VHDL packages RTL model Logic simulation Logic/RTL Constraints synthesis (area, timing, power) VHDL VITAL standard cell Gate-level modeld netlist Standard cell library SDF file Place & route Delay Layout extraction A. -
Xilinx Synthesis and Verification Design Guide
Synthesis and Simulation Design Guide 8.1i R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. -
Powerplay Power Analysis 8 2013.11.04
PowerPlay Power Analysis 8 2013.11.04 QII53013 Subscribe Send Feedback The PowerPlay Power Analysis tools allow you to estimate device power consumption accurately. As designs grow larger and process technology continues to shrink, power becomes an increasingly important design consideration. When designing a PCB, you must estimate the power consumption of a device accurately to develop an appropriate power budget, and to design the power supplies, voltage regulators, heat sink, and cooling system. The following figure shows the PowerPlay Power Analysis tools ability to estimate power consumption from early design concept through design implementation. Figure 8-1: PowerPlay Power Analysis From Design Concept Through Design Implementation PowerPlay Early Power Estimator Quartus II PowerPlay Power Analyzer Higher Placement and Simulation Routing Results Results Accuracy Quartus II Design Profile User Input Estimation Design Concept Design Implementation Lower PowerPlay Power Analysis Input For the majority of the designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the following accuracy after the power models are final: • PowerPlay Power Analyzer—±20% from silicon, assuming that the PowerPlay Power Analyzer uses the Value Change Dump File (.vcd) generated toggle rates. • PowerPlay EPE spreadsheet— ±20% from the PowerPlay Power Analyzer results using .vcd generated toggle rates. 90% of EPE designs (using .vcd generated toggle rates exported from PPPA) are within ±30% silicon. The toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate level simulation representative of the system operation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. -
Interconnect Solutions Short Form Catalog
Interconnect Solutions Short Form Catalog How to Search this Catalog This digital catalog provides you with three quick ways to find the products and information you are looking for. Just point and click on the bookmarks to the left, the linked images on the next page or the labeled sections of the table of contents. You can also use the “search” function built into Adobe Acrobat to jump directly to any text reference in this document. Acrobat “Search” function instructions: 1. Press CONTROL + F 2. When the dialog box appears, type in the word or words you are looking for and press ENTER. 3. Depending on your version of Acrobat, it will either take you directly to the first instance found, or display a list of pages where the text can be found. In the latter, click on the link to the pages provided. Interconnect Solutions Short Form Catalog Complete Solutions for the Electronics Industry 3M Electronics offers a comprehensive range of Interconnect Solutions for the electronics industry with a product portfolio that includes connectors, cables, cable assemblies and assembly tooling for a wide variety of applications. 3M is dedicated to innovation, continually developing new products that become an important part of everyday life across many diverse markets. A number of 3M solution categories are based on custom-designed products for specialized applications. 3M Electronics can help you design, modify and customize your product as well as help you to seamlessly integrate our products into your manufacturing process on a global basis. RoHS Compliant Statement “RoHS compliant” means that the product or part does not contain any of the following substances in excess of the following maximum concentration values in any homogeneous material, unless the substance is in an application that is exempt under RoHS: (a) 0.1% (by weight) for lead, mercury, hexavalent chromium, polybrominated biphenyls or polybrominated diphenyl ethers; or (b) 0.01% (by weight) for cadmium. -
System-On-Chip Design with Arm® Cortex®-M Processors
System-on-Chip Design with Arm® Cortex®-M Processors Reference Book JOSEPH YIU System-on-Chip Design with Arm® Cortex®-M Processors System-on-Chip Design with Arm® Cortex®-M Processors Reference Book JOSEPH YIU Arm Education Media is an imprint of Arm Limited, 110 Fulbourn Road, Cambridge, CBI 9NJ, UK Copyright © 2019 Arm Limited (or its affiliates). All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording or any other information storage and retrieval system, without permission in writing from the publisher, except under the following conditions: Permissions You may download this book in PDF format from the Arm.com website for personal, non- commercial use only. You may reprint or republish portions of the text for non-commercial, educational or research purposes but only if there is an attribution to Arm Education. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein). Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods and professional practices may become necessary. Readers must always rely on their own experience and knowledge in evaluating and using any information, methods, project work, or experiments described herein. In using such information or methods, they should be mindful of their safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent permitted by law, the publisher and the authors, contributors, and editors shall not have any responsibility or liability for any losses, liabilities, claims, damages, costs or expenses resulting from or suffered in connection with the use of the information and materials set out in this textbook. -
Publication Title 1-1962
publication_title print_identifier online_identifier publisher_name date_monograph_published_print 1-1962 - AIEE General Principles Upon Which Temperature 978-1-5044-0149-4 IEEE 1962 Limits Are Based in the rating of Electric Equipment 1-1969 - IEEE General Priniciples for Temperature Limits in the 978-1-5044-0150-0 IEEE 1968 Rating of Electric Equipment 1-1986 - IEEE Standard General Principles for Temperature Limits in the Rating of Electric Equipment and for the 978-0-7381-2985-3 IEEE 1986 Evaluation of Electrical Insulation 1-2000 - IEEE Recommended Practice - General Principles for Temperature Limits in the Rating of Electrical Equipment and 978-0-7381-2717-0 IEEE 2001 for the Evaluation of Electrical Insulation 100-2000 - The Authoritative Dictionary of IEEE Standards 978-0-7381-2601-2 IEEE 2000 Terms, Seventh Edition 1000-1987 - An American National Standard IEEE Standard for 0-7381-4593-9 IEEE 1988 Mechanical Core Specifications for Microcomputers 1000-1987 - IEEE Standard for an 8-Bit Backplane Interface: 978-0-7381-2756-9 IEEE 1988 STEbus 1001-1988 - IEEE Guide for Interfacing Dispersed Storage and 0-7381-4134-8 IEEE 1989 Generation Facilities With Electric Utility Systems 1002-1987 - IEEE Standard Taxonomy for Software Engineering 0-7381-0399-3 IEEE 1987 Standards 1003.0-1995 - Guide to the POSIX(R) Open System 978-0-7381-3138-2 IEEE 1994 Environment (OSE) 1003.1, 2004 Edition - IEEE Standard for Information Technology - Portable Operating System Interface (POSIX(R)) - 978-0-7381-4040-7 IEEE 2004 Base Definitions 1003.1, 2013 -
Opening Plenary March 2021
Opening Plenary March 2021 Glenn Parsons – IEEE 802.1 WG Chair [email protected] 802.1 plenary agenda Monday, March 8th opening Tuesday, March 16th closing • Copyright Policy • Copyright Policy • Call for Patents • Call for Patents • Participant behavior • Participant behavior • Administrative • Membership status • Membership status • Future Sessions • Future Sessions • Sanity check – current projects • 802 EC report • TG reports • Sanity check – current projects • Outgoing Liaisons • Incoming Liaisons • Motions for EC • TG agendas • Motions for 802.1 • Any other business • Any other business 2 INSTRUCTIONS FOR CHAIRS OF STANDARDS DEVELOPMENT ACTIVITIES At the beginning of each standards development meeting the chair or a designee is to: .Show the following slides (or provide them beforehand) .Advise the standards development group participants that: .IEEE SA’s copyright policy is described in Clause 7 of the IEEE SA Standards Board Bylaws and Clause 6.1 of the IEEE SA Standards Board Operations Manual; .Any material submitted during standards development, whether verbal, recorded, or in written form, is a Contribution and shall comply with the IEEE SA Copyright Policy; .Instruct the Secretary to record in the minutes of the relevant meeting: .That the foregoing information was provided and that the copyright slides were shown (or provided beforehand). .Ask participants to register attendance in IMAT: https://imat.ieee.org 3 IEEE SA COPYRIGHT POLICY By participating in this activity, you agree to comply with the IEEE Code of Ethics, all applicable laws, and all IEEE policies and procedures including, but not limited to, the IEEE SA Copyright Policy. .Previously Published material (copyright assertion indicated) shall not be presented/submitted to the Working Group nor incorporated into a Working Group draft unless permission is granted. -
XMOS for AVB Ethernet Based Networking for Audio/Video
Only a few years ago, computer networks were complex beasts tended by special acolytes and running on different standards. Today they have become commonplace in many homes and offices, simply plugged together using Ethernet technology. The same revolutionary change is coming for Audio/Video (AV) networking, as AVB (Audio XMOS for AVB: Video Bridging) products that run over the same network, Ethernet based networking begin to enter the market. for Audio/Video Putting together networks of AV equipment for professional and consumer use, or for use in How Ethernet Works vehicles, is about to become simpler while also Within Ethernet, data is transmitted between delivering better quality. No longer will devices (such as a computer and a printer) in specialist connectors and cables be needed to packets. Each packet carries one or more create a rats' nest of connectivity. Instead addresses for its destination. Like a postal packet traversing the postal system, the network has no Audio Video Bridging (AVB), a set of knowledge of what is in the packet, but uses the international standards, will make setting up address to pass the packet to the next point in the and managing networks almost as simple as network. just plugging together the different elements. In an Ethernet based network, each endpoint Sound and video sources will be mixed and (computer, storage element, printer etc.) is distributed to screens and speakers, with high identified by a unique address and has a single quality, low latency and tight synchronization. connection to the network, through an Ethernet Furthermore, the connectors and cables are switch. -
Designcon 2004 VHDL-200X and the Future of VHDL
DesignCon 2004 VHDL-200X and the Future of VHDL Jim Lewis, SynthWorks [email protected] Stephen Bailey, Mentor Graphic’s Model Technology Group Erich Marschner, Cadence Design Systems J. Bhasker, eSilicon Corp. Peter Ashenden, Ashenden Designs Pty. Ltd. Abstract VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market1. Many users prefer to use VHDL for RTL design as the language continues to provide desired characteristics in design safety, flexibility and maintainability. While VHDL has provided significant value for digital designers since 1987, it has had only one significant language revision in 1993. It has taken many years for design state-of-practice to catch-up to and, in some cases, surpass the capabilities that have been available in VHDL for over 15 years. Last year, the VHDL Analysis and Standardization Group (VASG), which is responsible for the VHDL standard, received clear indication from the VHDL community that it was now time to look at enhancing VHDL. In response to the user community, VASG initiated the VHDL-200x project2. VHDL-200x will result in at least two revisions of the VHDL standard. The first revision is planned to be completed next year (2004) and will include a C language interface (VHPI); a collection of high user value enhancements to improve designer productivity and modeling capability and potential inclusion of assertion-based verification and testbench modeling enhancements. A second revision is planned to follow about two years later. This paper summarizes VHDL-200X enhancements proposed for the first revision of VHDL. -
Software Architecture for a Multiple AVB Listener and Talker Scenario
Software Architecture for a Multiple AVB Listener and Talker Scenario Christoph Kuhr and Alexander Car^ot Department of Computer Sciences and Languages, Anhalt University of Applied Sciences Lohmannstr. 23, 06366 K¨othen, Germany, fchristoph.kuhr, [email protected] Abstract 1.2 Concept for a Realtime Processing Cloud This paper presents a design approach for an AVB network segment deploying two differ- A specialized and scalable server infrastructure ent types of AVB server for multiple paral- is required to provide the realtime streaming re- lel streams. The first type is an UDP proxy quirements of this research project. The ser- server and the second server type is a digital vice time property of an Ethernet frame arriv- signal processing server. The Linux real time ing on a serial network interface at the wide area operating system configurations are discussed, network (WAN) side of this server cloud, is of as well as the software architecture itself and paramount importance for the software design. the integration of the Jack audio server. A During the service time of a single UDP stream proper operation of the JACK server, along- datagram, no concurrent stream datagrams can side two JACK clients, in this multiprocess- be received. Thus, the latencies of all streams ing environment could be shown, although a arriving on such an interface are accumulated. persisting buffer leak prevents significant jitter In addition to connecting the 60 streams to and latency measurements. A coarse assessment each other, the Soundjack cloud provides dig- shows however, that the operations are within ital signal processing algorithms for audio and reasonable bounds. -
Extremexos® Operating System
Data Sheet Highlights ExtremeXOS has a robust set of Layer 2 and Layer 3 control protocols, provides a flexible architecture for highly resilient networks and has been designed to support the nextgeneration Internet Protocol, IPv6. ExtremeXOS is a highly available and extensible software foundation for converged networks. ExtremeXOS offers high availability for carriergrade voice and video services over IP and for supporting mission- critical business applications such as CRM. • Modular Operating System • High Availability Architecture • Rich set of Layer-2 and Layer-3 ® protocols and features ExtremeXOS Operating System • Secure Network Access through role Version 16.2, 21.1, 22.7, and 30.4 based policy or Identity Management • Extensibility • Integrated Security with NetLogin, Overview MAC Security, IP Security Extreme Networks has created the ExtremeXOS modular Operating • User, location, and time-based System (OS) – for highly available, extensible, high-performance networks. dynamic security policies with ExtremeXOS high availability architecture with EAPS protocol helps reduce Identity Management network downtime for business continuity and access to mission-critical • Insight, control and automation for applications such as CRM, data warehouses and VoIP for carrier and voice virtualized data centers with XNV grade networks. (ExtremeXOS Network Virtualization) • Enhanced resiliency, Built-in security capabilities provide network access control integrated with synchronization, performance for endpoint integrity checking, identity management, and protection for the 2G/3G/4G mobile backhaul network control and management planes. • ExtremeXOS InSite SDK Software Defined Networking Ready with With ExtremeXOS you can extend the capabilities of your network by OpenFlow and OpenStack support integrating specialized application appliances such as security devices into • Ethernet Audio Video Bridging the network, providing insight and control at the network, application and (AVB) enabled user level.