Fundamentals of Digital Logic with VHDL Design .-Mcgraw-Hill, 2000

Total Page:16

File Type:pdf, Size:1020Kb

Fundamentals of Digital Logic with VHDL Design .-Mcgraw-Hill, 2000 1 SYLLABUS FOR COURSE ADVANCED DIGITAL SYSTEMS (VHDL) Lecturer: Dr. Evgeni Perelroyzen Prerequisites for Course 1.Logic Circuits 2.Optimized Implementation of Logic Functions 3.Number Representation 4.Basic Combinational Circuits 5.Basic Sequential Circuits Detailed Teaching Plan 1. DESIGN CONCEPTS 1.1. Digital Hardware 1.1.1. Standard Chips - 7400-Series Standard Chips 1.1.2. Programmable Logic Devices - Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Programming of PLAs and PALs - Complex Programmable Logic Devices (CPLDs) - Field-Programmable Gate Arrays (FPGA) 1.1.3. Custom-Designed Chips 1.2. The Design Process [1, 5, 6] 1.2.1. Design Methodology. Top-Down Design(Flow) [5, 6, 9] 1.2.2. A Systematic Approach to Logic Design [5] 1.2.3. Verification [6, 9] - Summary of the different simulation alternatives [6] - Simulation Speed - Formal Verification - Recommendations for Verification 1.3. Design of Digital Hardware-Digital System Design Process [1, 9] 1.3.1. Basic Design Loop 1.3.2. Design of a Digital Hardware Unit 1.3.3. Overview of Digital Logic Design [5] 1.3.4. Overview of Combinational Circuit Design [5] 2 1.3.5. Overview of Sequential Circuit Design [5] 2. INTRODUCTION TO CAD TOOLS 2.1. Hardware Design Environments – Design Automation [9] 2.2. The Art of Modeling [9] 2.3. Design Entry 2.4. Hardware Simulation(Modeling Digital Systems) [1, 3, 6, 9] - Domains and Levels of Simulation(Modeling) [3] - Functional and Timing Simulation [1] - Oblivious Simulation [9] - Event-Driven Simulation [9] 2.5. Hardware Synthesis and Optimization [1, 9] 2.6. Physical Design 2.7. Summary of Design Flow 2.8. Rapid Prototyping [6] 2.8.1. Rapid Prototyping 2.8.2. Real-time Kernel-a Brief Description 2.8.3. The Development System 2.8.4. Development Phases 2.9. Why use Hardware Description Languages (HDL) [4, 6, 9, 7] - VHSIC(Very High Speed Integrated Circuit) Program - Traditional Schematics - Symbols Versus Entities - Schematics Versus Architecture - A Language for Behavioral Descriptions - A Language for Describing Flow of Data - A Language for Describing Netlist - VHDL(VHSIC Hardware Description Language) as a Standard - VHDL Advantages [7] - New Design Methodology [7] 2.10. What is Logic Synthesis? [7] 2.11. Examples of Circuits Synthesized from VHDL Code 2.12. Development Tools [6] 2.10.1. Synopsys - Design Ware - VHDL Compiler and Design Analyzer - Design Compiler - ATPG Tools - FPGA Compiler - VHDL Simulator 2.13. Test Applications [9] 2.14. Test Bench [6] 2.14.1. VHDL Description of a Simple Test Bench [9]. Simulation 2.14.2. Different Levels of Test Bench 3 2.14.3. Pull up/down 2.12.4. Several Components in the same Test Bench 2.12.5. Waveform Generators 2.12.6. TextIO 2.12.7. A Design Case and Test Bench [7] - Design Description - Writing VHDL Model - Another Test Bench - Synthesizing the Design 2.12. Levels of Abstraction 3. HARDWARE DESCRIPTION LANGUAGES. VHDL [1, 5, 6] 3.1. Introduction to VHDL. Design Methodology Based on VHDL [1, 9] 3.1.1. VHDL Language Abstractions [6] 3.1.2. Design hierarchies-reducing complexity [6] 3.1.3. Basic Concepts in VHDL [3, 4, 9, 7] - Characterizing Hardware Language Timing : Event Scheduling Concurrency : Statement Concurrency Modeling Hardware - Objects and Classes - The Concept of the Signal. Signal Assignments - Concurrent and Sequential Assignment - Process Concurrency. Process Activation by a Signal Event - Delta Time - VHDL Terms - VHDL Design Entity: ENTITY Declaration, ARCHITECTURE Body - Structural and Behavioral Architectures [1, 6, 3] - Mixed Structural and Behavioral Models [3] - Signal-Valued andb Signal-Related Attributes [7] 3.1.4. Components of a VHDL Description [1, 5] - Using Sub-circuits: Declaring a COMPONENT 3.1.5. Construction of a VHDL Program [5] 3.1.6. Representation of Digital Signals in VHDL 3.1.7. Transport Versus Inertial Delay [4] - Inertial Delay Model - Transport Delay Model - Simulation Deltas 3.1.10.Writing Simple VHDL Code 3.1.11.Complete VHDL Examples [5] 3.1.12.How Not to Write VHDL Code 3.1.14.Writing Efficient VHDL Code [7] 4 3.1.13.Documentation in VHDL Code 3.1.14.Other Modeling Languages for describing electronics - Verilog HDL [2, 24, 25] - ABEL [11, 2] - AHPL [9] - ADLIB [37] - CDL [9] - CONLAN [9] - CUPL [2, 12] - HILL [38] - IDL [9] - ISPS [9] - PALASM [2] - SLIDE [39] - TEGAS [9] - TI-HDL [9] - Zeus [9] 3.2. Conventions and VHDL Syntax [1, 3, 9, 7] 3.2.1. Lexical Elements, Separators, and Delimiters 3.2.2. Identifiers 3.2.3. Reserved Words 3.2.4. Literals 3.2.5. Syntax Descriptions [3] - Design File - Library Unit Declarations - Declarations and Specifications - Type Definitions - Concurrent Statements - Sequential Statements - Interfaces and Associations - Expressions 3.2.6. Differences among VHDL-87, VHDL-93 and VHDL-2001 [3, 7] - Lexical Differences - Syntactic Differences - Semantic Differences - Differences in the Standard Environment - VHDL-93 Facilities Not in VHDL-87 or VHDL-93 - Features under Consideration for Removal 3.3. Utilities for High-Level Descriptions [1, 3, 4, 9] 3.3.1. Type Declarations and Usage [1, 4] - Object Types Signal 5 Variables Constants - Data Types Scalar Types Composite Types Incomplete Types File Types - File Type Caveats - Subtypes 3.3.2. Scalar Data Types and Operations [3] - Constants and Variables - Scalar Types - Type Classification - Attributes of Scalar Types - Expressions and Operators 3.3.3. Composite Data Types and Operations [3] - Arrays - Unconstrained Array Types - Array Operations and Referencing - Records 3.3.4. VHDL Operators 3.3.5. Subprogram Parameter Types and Overloading 3.3.6. Other Types and Type-Related Issues 3.3.7. Access Types and Abstract Data Types [3] 3.3.8. Files and Input/Output [3, 7] - File Types and File I/O - The Package Textio Textio Read Operations Textio Write Operations 3.3.9. Predefined Attributes [3, 4] - Value Kind Attributes Value Type Attributes Value Array Attributes Value Block Attributes - Function Kind Attributes Function Type Attributes Function Array Attributes Function Block Attributes Attributes ‘EVENT and ‘LAST_VALUE Attribute ‘LAST_EVENT Attributes ‘ACTIVE and ‘LAST_ACTIVE - Signal Kind Attributes Attribute ‘DELAYED 6 Attribute ‘STABLE Attribute ‘QUIET Attribute ‘TRANSACTION - Type Kind Attributes - Range Kind Attributes 3.3.10. User-Defined Attributes 3.3.11. Packaging Basic Utilities 3.4. Design Organization and Parameterization [1, 9] 3.4.1. Definition and Usage of Subprograms [1, 3, 6, 7, 9] - Subprogram Declaration - Subprogram Body - Subprogram Overloading - Subprogram Return Values and Types - Type Casting and Type Qualification - Procedures - Procedure Parameters - Concurrent Procedure Call Statement - Functions Conversion Functions [4] Resolution Functions [4, 7] - Subprogram Overloading [7] - Visibility of Declarations 3.4.2. Packages : Packaging Parts and Use Clauses(Utilities) [1, 3, 6, 7, 9] - Package Declarations [3, 7] - Package Bodies [3, 7] - Use Clauses [3] - Deferred Constants [4] - The Predefined Package Standard [3] - IEEE Standard Packages [3] : Standard Package [9] Textio Package [3, 9] Std_Logic 1164 Multivalue Logic System Package [3, 9] Standard VHDL Mathematical Packages [3] Standard VHDL Synthesis [3] - Basic Utilities Package [9] 3.4.3. Design Components and Configurations [ 3, 9 ] - Component Declarations - Component Instantiation - Packaging Components - Configuring Component Instances : Architecture Selection 7 - Configuration Specifications (Configuration Statements) - Power of Configurations 3.4.4. Design Libraries [1, 6, 7, 9] 3.4.5. Design Parameterization : Defining an Entity with GENERIC Constants [1, 3, 9] - Parameterizing Behavior - Parameterizing Structure 3.5. Concurrent VHDL - Concurrent Assignment Statements [1, 3, 4, 6, 7] 3.5.1. Simple Signal Assignment 3.5.2. Signal Assignment Versus Variable Assignment [4] - Incorrect Mux Example - Correct Mux Example 3.5.3. Assigning Signal Values Using OTHERS 3.5.4. Selected Signal Assignment 3.5.5. Conditional Signal Assignment 3.5.6. Component Instantiation Statement 3.5.7. Concurrent PROCEDURE CALL Statement 3.5.8. GENERATE Statement [3] - Generating Iterative Structures - Conditionally Generating Structures. Recursive Structures - Configuration of Generate Statements 3.6. Sequential VHDL - Sequential Assignment Statements [1, 4, 6, 7] 3.6.1. PROCESS Statement - Sensitivity List - Process Declarative Region - Process Statement Part - Process Example - Process Execution 3.6.2. BLOCK Statement 3.6.3. IF Statement 3.6.4. CASE Statement 3.6.5. LOOP Statement 3.6.6. NEXT Statement 3.6.7. EXIT Statement 3.6.8. NULL Statement 3.6.9. RETURN Statement 3.6.10. PROCEDURE CALL Statement 3.6.11. ASSERT Statement - Assertion BNF 3.6.12. WAIT Statement [4] 8 - WAIT ON Signal - WAIT UNTIL Expression - WAIT FOR time_expression - Multiple WAIT Conditions - WAIT Time-Out - Sensitivity List Versus WAIT Statement - Concurrent Assignment Problem - Passive Processes 3.7. Structural Specification of Hardware [9] 3.7.1. Parts Library 3.7.2. Wiring of Primitives - Logic Design of Comparator - VHDL Description of a 4-bit Comparator 3.7.3. Wiring Iterative Networks - Design of a 4-bit Comparator - VHDL Description of a 4-bit Comparator 3.7.4. Binding Alternative 3.7.5. Top-Down Wiring - Sequential Comparator - Byte Latch - Byte Comparator 3.8. Behavioral Description of Hardware [9] 3.8.1. Process Statement 3.8.2. Assertion Statement 3.8.3. Sequential WAIT Statement 3.8.4. Formatted ASCII I/O Operations 3.8.5. MSI-Based Design 3.9. Dataflow Descriptions in VHDL [9] 3.9.1. Multiplexing
Recommended publications
  • Prostep Ivip CPO Statement Template
    CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of
    [Show full text]
  • Systemverilog
    SystemVerilog ● Industry's first unified HDVL (Hw Description and Verification language (IEEE 1800) ● Major extension of Verilog language (IEEE 1364) ● Targeted primarily at the chip implementation and verification flow ● Improve productivity in the design of large gate-count, IP- based, bus-intensive chips Sources and references 1. Accellera IEEE SystemVerilog page http://www.systemverilog.com/home.html 2. “Using SystemVerilog for FPGA design. A tutorial based on a simple bus system”, Doulos http://www.doulos.com/knowhow/sysverilog/FPGA/ 3. “SystemVerilog for Design groups”, Slides from Doulos training course 4. Various tutorials on SystemVerilog on Doulos website 5. “SystemVerilog for VHDL Users”, Tom Fitzpatrick, Synopsys Principal Technical Specialist, Date04 http://www.systemverilog.com/techpapers/date04_systemverilog.pdf 6. “SystemVerilog, a design and synthesis perspective”, K. Pieper, Synopsys R&D Manager, HDL Compilers 7. Wikipedia Extensions to Verilog ● Improvements for advanced design requirements – Data types – Higher abstraction (user defined types, struct, unions) – Interfaces ● Properties and assertions built in the language – Assertion Based Verification, Design for Verification ● New features for verification – Models and testbenches using object-oriented techniques (class) – Constrained random test generation – Transaction level modeling ● Direct Programming Interface with C/C++/SystemC – Link to system level simulations Data types: logic module counter (input logic clk, ● Nets and Variables reset, ● enable, Net type,
    [Show full text]
  • Development of Systemc Modules from HDL for System-On-Chip Applications
    University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications".
    [Show full text]
  • Powerplay Power Analysis 8 2013.11.04
    PowerPlay Power Analysis 8 2013.11.04 QII53013 Subscribe Send Feedback The PowerPlay Power Analysis tools allow you to estimate device power consumption accurately. As designs grow larger and process technology continues to shrink, power becomes an increasingly important design consideration. When designing a PCB, you must estimate the power consumption of a device accurately to develop an appropriate power budget, and to design the power supplies, voltage regulators, heat sink, and cooling system. The following figure shows the PowerPlay Power Analysis tools ability to estimate power consumption from early design concept through design implementation. Figure 8-1: PowerPlay Power Analysis From Design Concept Through Design Implementation PowerPlay Early Power Estimator Quartus II PowerPlay Power Analyzer Higher Placement and Simulation Routing Results Results Accuracy Quartus II Design Profile User Input Estimation Design Concept Design Implementation Lower PowerPlay Power Analysis Input For the majority of the designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the following accuracy after the power models are final: • PowerPlay Power Analyzer—±20% from silicon, assuming that the PowerPlay Power Analyzer uses the Value Change Dump File (.vcd) generated toggle rates. • PowerPlay EPE spreadsheet— ±20% from the PowerPlay Power Analyzer results using .vcd generated toggle rates. 90% of EPE designs (using .vcd generated toggle rates exported from PPPA) are within ±30% silicon. The toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate level simulation representative of the system operation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S.
    [Show full text]
  • System-On-Chip Design with Arm® Cortex®-M Processors
    System-on-Chip Design with Arm® Cortex®-M Processors Reference Book JOSEPH YIU System-on-Chip Design with Arm® Cortex®-M Processors System-on-Chip Design with Arm® Cortex®-M Processors Reference Book JOSEPH YIU Arm Education Media is an imprint of Arm Limited, 110 Fulbourn Road, Cambridge, CBI 9NJ, UK Copyright © 2019 Arm Limited (or its affiliates). All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording or any other information storage and retrieval system, without permission in writing from the publisher, except under the following conditions: Permissions You may download this book in PDF format from the Arm.com website for personal, non- commercial use only. You may reprint or republish portions of the text for non-commercial, educational or research purposes but only if there is an attribution to Arm Education. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein). Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods and professional practices may become necessary. Readers must always rely on their own experience and knowledge in evaluating and using any information, methods, project work, or experiments described herein. In using such information or methods, they should be mindful of their safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent permitted by law, the publisher and the authors, contributors, and editors shall not have any responsibility or liability for any losses, liabilities, claims, damages, costs or expenses resulting from or suffered in connection with the use of the information and materials set out in this textbook.
    [Show full text]
  • Publication Title 1-1962
    publication_title print_identifier online_identifier publisher_name date_monograph_published_print 1-1962 - AIEE General Principles Upon Which Temperature 978-1-5044-0149-4 IEEE 1962 Limits Are Based in the rating of Electric Equipment 1-1969 - IEEE General Priniciples for Temperature Limits in the 978-1-5044-0150-0 IEEE 1968 Rating of Electric Equipment 1-1986 - IEEE Standard General Principles for Temperature Limits in the Rating of Electric Equipment and for the 978-0-7381-2985-3 IEEE 1986 Evaluation of Electrical Insulation 1-2000 - IEEE Recommended Practice - General Principles for Temperature Limits in the Rating of Electrical Equipment and 978-0-7381-2717-0 IEEE 2001 for the Evaluation of Electrical Insulation 100-2000 - The Authoritative Dictionary of IEEE Standards 978-0-7381-2601-2 IEEE 2000 Terms, Seventh Edition 1000-1987 - An American National Standard IEEE Standard for 0-7381-4593-9 IEEE 1988 Mechanical Core Specifications for Microcomputers 1000-1987 - IEEE Standard for an 8-Bit Backplane Interface: 978-0-7381-2756-9 IEEE 1988 STEbus 1001-1988 - IEEE Guide for Interfacing Dispersed Storage and 0-7381-4134-8 IEEE 1989 Generation Facilities With Electric Utility Systems 1002-1987 - IEEE Standard Taxonomy for Software Engineering 0-7381-0399-3 IEEE 1987 Standards 1003.0-1995 - Guide to the POSIX(R) Open System 978-0-7381-3138-2 IEEE 1994 Environment (OSE) 1003.1, 2004 Edition - IEEE Standard for Information Technology - Portable Operating System Interface (POSIX(R)) - 978-0-7381-4040-7 IEEE 2004 Base Definitions 1003.1, 2013
    [Show full text]
  • VHDL Modelling Guidelines Simulation and Documentation Aspects
    Second draft, 23 February 1997 CENELEC TC217/WG2 report 2.14 English version VHDL Modelling Guidelines Simulation and Documentation Aspects This CENELEC Report is under preparation and review by the Technical Committee CENELEC TC 217 Working Group 2. CENELEC members are the national electrotechnical committees of Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardisation Comité Européen de Normalisation Electrotechnique Europäisches Komitee für Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B-1050 Brussels CENELEC TC217/WG2 report 2.142 Second draft, 23 February 1997 3DJH LQWHQWLRQDOO\ OHIW EODQN Second draft, 23 February 19973 CENELEC TC217/WG2 report 2.14 )25(:25' 7KLV 7HFKQLFDO 5HSRUW LV WKH ILUVW GUDIW RI WKH &(1(/(& 7&:* UHSRUW 7KH UHSRUW LV GHULYHG IURP WKH (XURSHDQ 6SDFH $JHQF\ V (6$©V 9+'/ 0RGHOOLQJ *XLGHOLQHV UHIHUHQFH $6,& LVVXH GDWHG 6HSWHPEHU 7KLV GUDIW KDV EHHQ SUHSDUHG WDNLQJ LQWR DFFRXQW FRPPHQWV IURP &(1(/(& :* PHPEHUV SUHVHQWHG RQ WKH GHGLFDWHG HPDLO UHIOHFWRU 7KH DXWKRU ZRXOG OLNH WR WKDQN DOO FRQWULEXWRUV IRU WKHLU YDOXDEOH LQSXW 7KH (6$ 9+'/ 0RGHOOLQJ *XLGHOLQHV KDYH EHHQ XVHG LQ (6$ GHYHORSPHQW DQG VWXG\ FRQWUDFWV WR HQVXUH KLJKTXDOLW\ PDLQWDLQDEOH 9+'/ PRGHOV 7KH\ KDYH EHHQ SUHSDUHG E\ 3HWHU 6LQDQGHU ZLWK VXSSRUW IURP 6DQGL +DELQF ERWK DW WKH (6$(67(& 0LFURHOHFWURQLFV DQG 7HFKQRORJ\ 6HFWLRQ :60 32 %R[ $* 1RRUGZLMN
    [Show full text]
  • Waveform Editor
    1. Quartus II Simulator QII53017-9.1.0 This chapter describes how to perform different types of simulations with the Quartus II simulator. Introduction With today’s FPGAs becoming faster and more complex, designers face challenges in validating their designs. Simulation verifies the correctness of the design, reducing board testing and debugging time. The Altera® Quartus® II simulator is included in the Quartus II software to assist designers with design verification. The Quartus II simulator has a comprehensive set of features that are covered in the following sections: ■ “Simulation Flow” on page 1–2 ■ “Waveform Editor” on page 1–5 ■ “Simulator Settings” on page 1–13 ■ “Simulation Report” on page 1–16 ■ “Debugging with the Quartus II Simulator” on page 1–19 ■ “Scripting Support” on page 1–21 The Quartus II simulator supports the following device families: ■ ACEX® 1K ■ APEX™ 20KC, APEX 20KE, APEX II ■ Arria® GX ■ Cyclone® III, Cyclone II, Cyclone ■ FLEX® 10K, FLEX 10KA, FLEX 10KE, FLEX 6000 ■ HardCopy® II, HardCopy ■ MAX® II, MAX 3000A, MAX 7000AE, MAX 7000B, MAX 7000S ■ Stratix® III, Stratix II, Stratix, Stratix GX, Stratix II GX 1 The Quartus II simulator does not support newer devices introduced after Stratix III and Quartus II software version 8.1 and onwards. Use the ModelSim-Altera Edition to run simulations on designs targeting device introductions after Stratix III. For more information about the ModelSim-Altera Edition simulator, refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Handbook. In the Quartus II software version 10.0 and onwards, the Quartus II simulator and Waveform Editor is removed.
    [Show full text]
  • VHDL Verification of FPGA Based ESF-CCS for Nuclear Power Plant I&C
    VHDL Verification of FPGA based ESF-CCS for Nuclear Power Plant I&C System Restu MAERANI1, and Jae Cheon JUNG2 1. Department of NPP Engineering, KINGS, Ulsan, 45014, Indonesia ([email protected]) 2. Department of NPP Engineering, KINGS, Ulsan, 45014, Republic of Korea ([email protected]) Abstract: Verification becomes the focus of activities during the integration phase of design life cycle in the development of the system. Verification methods that will not take much cost and time should be properly selected, accordance with the Measurement of Effectiveness (MOEs) need. Verification is one phase that must be done after completing the implementation process. Since Instrumentation & Control (I&C) system has a role as a very crucial to the control protection system in Nuclear Power Plant (NPP), then software verification is very essential and shall to be achieved for safety critical issue in system level. According to IEEE 1076-2008 standard, VHDL is a language that is easy to read by machines and humans; and make it easier for process development, verification, synthesis and testing for hardware reliability in the design. Because this design uses VHDL code for Field Programmable Gate Array (FPGA) based Engineered Safety features – Component Control System (ESF-CCS) and by referring to the NUREG/CR-7006 during VHDL verification on behavioral simulation process, it should be equivalent with the post layout simulation. Furthermore, Vivado will be used as the VHDL verifier, where the VHDL code itself is created, in order to simplify the process of verification with this design life cycle phase on re-engineering process.
    [Show full text]
  • Xilinx Development Systems: Product Descriptions, Data Book
    1 Development Systems: Product Descriptions November 25, 1997 (Version 2.0) 12* Development Systems Descriptions It’s simple to order a Xilinx Development System. Just choose a Foundation or Alliance Series and a few options. Give your local Xilinx Sales Office a call for information about our evaluation kits. Foundation Series • Foundation Base System (PC) • Foundation Base-Express System (PC) • Foundation Standard System (PC) • Foundation Express System (PC) Alliance Series • Alliance Base (PC or Workstation) • Alliance Standard (PC or Workstation) Alliance Series Options • VIEWlogic Workview Office Standard Development System Options (PC) November 25, 1997 (Version 2.0) 2-3 Development Systems: Product Descriptions Foundation Series: Foundation Base System (PC) Overview Package Features - Foundation Base The Foundation Series provides a complete, ready-to-use System design system for the design of Xilinx programmable logic FND FND FND FND devices. The Foundation Base System provides design Feature BAS STD BSX EXP entry (schematic and Abel HDL), simulation, and device √√√√ implementation tools for a broad array of FPGA and CPLD CPLD Devices √1 √√1 √ devices targeted for low density and high volume applica- FPGA Devices tions. Libraries and Interface √√√√ Schematic Editor √√√√ System Features HDL Editor √√√√ • Project manager Graphical State Editor √√√√ • Schematic editor ABEL 6 Entry / Synthesis √√√√ • Integrated HDL editor with support for the Abel 6 HDL VHDL Entry / Synthesis √√ • Functional and timing simulator √√ • EDIF, VHDL (VITAL compliant), and Verilog / SDF Verilog Entry / Synthesis √√√√ design interfaces Schematic-centric Synthesis • Device implementation software for Xilinx CPLDs and HDL-centric Synthesis √ FPGAs Simulator √√√√ • Comprehensive on-line help, on-line documentation, Device Implementation √√√√ and software tutorials Maintenance2 √√√√ • Software maintenance, including hotline support and 11/12/97 software updates Notes: 1.
    [Show full text]
  • DIGITAL COMMUNICATION and CONTROL CIRCUITS for 60Ghz
    DIGITAL COMMUNICATION AND CONTROL CIRCUITS FOR 60GHz FULLY INTEGRATED CMOS DIGITAL RADIO A Thesis Presented to The Academic Faculty by Gopal B. Iyer In Partial Fulfillment of Requirements for the Degree Master of Science in School of Electrical and Computer Engineering Georgia Institute of Technology May 2010 COPYRIGHT © 2010 BY GOPAL B. IYER DIGITAL COMMUNICATION AND CONTROL CIRCUITS FOR 60GHz FULLY INTEGRATED CMOS DIGITAL RADIO Approved by: Dr. Joy Laskar, Advisor School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Saibal Mukhopadhyay School of Electrical and Computer Engineering Georgia Institute of Technology Dr. Manos Tentzeris School of Electrical and Computer Engineering Georgia Institute of Technology Date Approved: 2nd April 2010 I dedicate all my research work and the culmination, this thesis: to my Mom, Dad, my sisters, Sheela and Sheetal my brother-in-law, Vinayak, and to the apple of my eye, my nephew, Vivek ACKNOWLEDGEMENTS I would like to thank my advisor Dr. Joy Laskar for his inspiring leadership and guidance throughout the course of my research project. I would also like to express my gratitude to Dr. Saibal Mukhopadhyay and Dr. Manos Tentzeris for taking the time and serving on my reading committee. I wish to acknowledge Dr Stephane Pinel and Dr. Bevin Perumana for providing excellent technical guidance in helping me complete my research work. In particular I would like to thank Dr. Bevin Perumana, for mentoring me in the art of Mixed Signal Design. I wish to thank Dr. Padmanava Sen and Dr. Saikat Sarkar for their constant support and valuable friendship. I take this opportunity to thank all the team members of the Millimeter-Wave Applications Group, who have been a part of this Digital Radio Transceiver project.
    [Show full text]
  • DESIGN VERIFICATION of POWER MANAGEMENT UNIT and CLOCK GENERATION BLOCK of Wi-Fi Soc
    ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 5, Issue 2, February 2016 DESIGN VERIFICATION OF POWER MANAGEMENT UNIT AND CLOCK GENERATION BLOCK OF Wi-Fi SoC Chandrahas Reddy.M1 and Sugandhi.k2 1 M.Tech .Vlsi Design, SRM University, Chennai, India 2Asst.Professor (Sr.G), Department of Electronics and Communication SRM University, Chennai, India. Abstract variants during this execution flow. A typical SOC may contains the cores like a It is all about the importance of processor or processor sub-system, a the system on chip and the typical processor bus, a peripheral bus, a bridge intellectual property design verification between the two buses, and many flow that is followed in the industry, peripheral devices such as data motivation behind this project and the transformation engines, data ports (e.g. time plan that was followed in the UARTs, MACs) and controllers (e.g., execution of project. DMA). The sub-systems included in a specific SOC depend on the intended The term “system on a chip”, or device and a series of tradeoffs and SOC really implies two things, the requirements, such as cost, form factor, product itself and the methodology used power, performance, and functionality. to design it. A SOC product integrates several sub-systems, many or all of The verification methodology of an which would’ve been separate discrete SOC flow includes the stimulation of chips in the past into a single chip. design by providing input stimuli through Depending on how tightly you restrict Testbench setup and verify that it the definition, a SOC may be only a functioning as per intended specifications single silicon die, or possibly many dies and this input stimulus exercises through a inside a single package.
    [Show full text]