Fundamentals of Digital Logic with VHDL Design .-Mcgraw-Hill, 2000
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1 SYLLABUS FOR COURSE ADVANCED DIGITAL SYSTEMS (VHDL) Lecturer: Dr. Evgeni Perelroyzen Prerequisites for Course 1.Logic Circuits 2.Optimized Implementation of Logic Functions 3.Number Representation 4.Basic Combinational Circuits 5.Basic Sequential Circuits Detailed Teaching Plan 1. DESIGN CONCEPTS 1.1. Digital Hardware 1.1.1. Standard Chips - 7400-Series Standard Chips 1.1.2. Programmable Logic Devices - Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Programming of PLAs and PALs - Complex Programmable Logic Devices (CPLDs) - Field-Programmable Gate Arrays (FPGA) 1.1.3. Custom-Designed Chips 1.2. The Design Process [1, 5, 6] 1.2.1. Design Methodology. Top-Down Design(Flow) [5, 6, 9] 1.2.2. A Systematic Approach to Logic Design [5] 1.2.3. Verification [6, 9] - Summary of the different simulation alternatives [6] - Simulation Speed - Formal Verification - Recommendations for Verification 1.3. Design of Digital Hardware-Digital System Design Process [1, 9] 1.3.1. Basic Design Loop 1.3.2. Design of a Digital Hardware Unit 1.3.3. Overview of Digital Logic Design [5] 1.3.4. Overview of Combinational Circuit Design [5] 2 1.3.5. Overview of Sequential Circuit Design [5] 2. INTRODUCTION TO CAD TOOLS 2.1. Hardware Design Environments – Design Automation [9] 2.2. The Art of Modeling [9] 2.3. Design Entry 2.4. Hardware Simulation(Modeling Digital Systems) [1, 3, 6, 9] - Domains and Levels of Simulation(Modeling) [3] - Functional and Timing Simulation [1] - Oblivious Simulation [9] - Event-Driven Simulation [9] 2.5. Hardware Synthesis and Optimization [1, 9] 2.6. Physical Design 2.7. Summary of Design Flow 2.8. Rapid Prototyping [6] 2.8.1. Rapid Prototyping 2.8.2. Real-time Kernel-a Brief Description 2.8.3. The Development System 2.8.4. Development Phases 2.9. Why use Hardware Description Languages (HDL) [4, 6, 9, 7] - VHSIC(Very High Speed Integrated Circuit) Program - Traditional Schematics - Symbols Versus Entities - Schematics Versus Architecture - A Language for Behavioral Descriptions - A Language for Describing Flow of Data - A Language for Describing Netlist - VHDL(VHSIC Hardware Description Language) as a Standard - VHDL Advantages [7] - New Design Methodology [7] 2.10. What is Logic Synthesis? [7] 2.11. Examples of Circuits Synthesized from VHDL Code 2.12. Development Tools [6] 2.10.1. Synopsys - Design Ware - VHDL Compiler and Design Analyzer - Design Compiler - ATPG Tools - FPGA Compiler - VHDL Simulator 2.13. Test Applications [9] 2.14. Test Bench [6] 2.14.1. VHDL Description of a Simple Test Bench [9]. Simulation 2.14.2. Different Levels of Test Bench 3 2.14.3. Pull up/down 2.12.4. Several Components in the same Test Bench 2.12.5. Waveform Generators 2.12.6. TextIO 2.12.7. A Design Case and Test Bench [7] - Design Description - Writing VHDL Model - Another Test Bench - Synthesizing the Design 2.12. Levels of Abstraction 3. HARDWARE DESCRIPTION LANGUAGES. VHDL [1, 5, 6] 3.1. Introduction to VHDL. Design Methodology Based on VHDL [1, 9] 3.1.1. VHDL Language Abstractions [6] 3.1.2. Design hierarchies-reducing complexity [6] 3.1.3. Basic Concepts in VHDL [3, 4, 9, 7] - Characterizing Hardware Language Timing : Event Scheduling Concurrency : Statement Concurrency Modeling Hardware - Objects and Classes - The Concept of the Signal. Signal Assignments - Concurrent and Sequential Assignment - Process Concurrency. Process Activation by a Signal Event - Delta Time - VHDL Terms - VHDL Design Entity: ENTITY Declaration, ARCHITECTURE Body - Structural and Behavioral Architectures [1, 6, 3] - Mixed Structural and Behavioral Models [3] - Signal-Valued andb Signal-Related Attributes [7] 3.1.4. Components of a VHDL Description [1, 5] - Using Sub-circuits: Declaring a COMPONENT 3.1.5. Construction of a VHDL Program [5] 3.1.6. Representation of Digital Signals in VHDL 3.1.7. Transport Versus Inertial Delay [4] - Inertial Delay Model - Transport Delay Model - Simulation Deltas 3.1.10.Writing Simple VHDL Code 3.1.11.Complete VHDL Examples [5] 3.1.12.How Not to Write VHDL Code 3.1.14.Writing Efficient VHDL Code [7] 4 3.1.13.Documentation in VHDL Code 3.1.14.Other Modeling Languages for describing electronics - Verilog HDL [2, 24, 25] - ABEL [11, 2] - AHPL [9] - ADLIB [37] - CDL [9] - CONLAN [9] - CUPL [2, 12] - HILL [38] - IDL [9] - ISPS [9] - PALASM [2] - SLIDE [39] - TEGAS [9] - TI-HDL [9] - Zeus [9] 3.2. Conventions and VHDL Syntax [1, 3, 9, 7] 3.2.1. Lexical Elements, Separators, and Delimiters 3.2.2. Identifiers 3.2.3. Reserved Words 3.2.4. Literals 3.2.5. Syntax Descriptions [3] - Design File - Library Unit Declarations - Declarations and Specifications - Type Definitions - Concurrent Statements - Sequential Statements - Interfaces and Associations - Expressions 3.2.6. Differences among VHDL-87, VHDL-93 and VHDL-2001 [3, 7] - Lexical Differences - Syntactic Differences - Semantic Differences - Differences in the Standard Environment - VHDL-93 Facilities Not in VHDL-87 or VHDL-93 - Features under Consideration for Removal 3.3. Utilities for High-Level Descriptions [1, 3, 4, 9] 3.3.1. Type Declarations and Usage [1, 4] - Object Types Signal 5 Variables Constants - Data Types Scalar Types Composite Types Incomplete Types File Types - File Type Caveats - Subtypes 3.3.2. Scalar Data Types and Operations [3] - Constants and Variables - Scalar Types - Type Classification - Attributes of Scalar Types - Expressions and Operators 3.3.3. Composite Data Types and Operations [3] - Arrays - Unconstrained Array Types - Array Operations and Referencing - Records 3.3.4. VHDL Operators 3.3.5. Subprogram Parameter Types and Overloading 3.3.6. Other Types and Type-Related Issues 3.3.7. Access Types and Abstract Data Types [3] 3.3.8. Files and Input/Output [3, 7] - File Types and File I/O - The Package Textio Textio Read Operations Textio Write Operations 3.3.9. Predefined Attributes [3, 4] - Value Kind Attributes Value Type Attributes Value Array Attributes Value Block Attributes - Function Kind Attributes Function Type Attributes Function Array Attributes Function Block Attributes Attributes ‘EVENT and ‘LAST_VALUE Attribute ‘LAST_EVENT Attributes ‘ACTIVE and ‘LAST_ACTIVE - Signal Kind Attributes Attribute ‘DELAYED 6 Attribute ‘STABLE Attribute ‘QUIET Attribute ‘TRANSACTION - Type Kind Attributes - Range Kind Attributes 3.3.10. User-Defined Attributes 3.3.11. Packaging Basic Utilities 3.4. Design Organization and Parameterization [1, 9] 3.4.1. Definition and Usage of Subprograms [1, 3, 6, 7, 9] - Subprogram Declaration - Subprogram Body - Subprogram Overloading - Subprogram Return Values and Types - Type Casting and Type Qualification - Procedures - Procedure Parameters - Concurrent Procedure Call Statement - Functions Conversion Functions [4] Resolution Functions [4, 7] - Subprogram Overloading [7] - Visibility of Declarations 3.4.2. Packages : Packaging Parts and Use Clauses(Utilities) [1, 3, 6, 7, 9] - Package Declarations [3, 7] - Package Bodies [3, 7] - Use Clauses [3] - Deferred Constants [4] - The Predefined Package Standard [3] - IEEE Standard Packages [3] : Standard Package [9] Textio Package [3, 9] Std_Logic 1164 Multivalue Logic System Package [3, 9] Standard VHDL Mathematical Packages [3] Standard VHDL Synthesis [3] - Basic Utilities Package [9] 3.4.3. Design Components and Configurations [ 3, 9 ] - Component Declarations - Component Instantiation - Packaging Components - Configuring Component Instances : Architecture Selection 7 - Configuration Specifications (Configuration Statements) - Power of Configurations 3.4.4. Design Libraries [1, 6, 7, 9] 3.4.5. Design Parameterization : Defining an Entity with GENERIC Constants [1, 3, 9] - Parameterizing Behavior - Parameterizing Structure 3.5. Concurrent VHDL - Concurrent Assignment Statements [1, 3, 4, 6, 7] 3.5.1. Simple Signal Assignment 3.5.2. Signal Assignment Versus Variable Assignment [4] - Incorrect Mux Example - Correct Mux Example 3.5.3. Assigning Signal Values Using OTHERS 3.5.4. Selected Signal Assignment 3.5.5. Conditional Signal Assignment 3.5.6. Component Instantiation Statement 3.5.7. Concurrent PROCEDURE CALL Statement 3.5.8. GENERATE Statement [3] - Generating Iterative Structures - Conditionally Generating Structures. Recursive Structures - Configuration of Generate Statements 3.6. Sequential VHDL - Sequential Assignment Statements [1, 4, 6, 7] 3.6.1. PROCESS Statement - Sensitivity List - Process Declarative Region - Process Statement Part - Process Example - Process Execution 3.6.2. BLOCK Statement 3.6.3. IF Statement 3.6.4. CASE Statement 3.6.5. LOOP Statement 3.6.6. NEXT Statement 3.6.7. EXIT Statement 3.6.8. NULL Statement 3.6.9. RETURN Statement 3.6.10. PROCEDURE CALL Statement 3.6.11. ASSERT Statement - Assertion BNF 3.6.12. WAIT Statement [4] 8 - WAIT ON Signal - WAIT UNTIL Expression - WAIT FOR time_expression - Multiple WAIT Conditions - WAIT Time-Out - Sensitivity List Versus WAIT Statement - Concurrent Assignment Problem - Passive Processes 3.7. Structural Specification of Hardware [9] 3.7.1. Parts Library 3.7.2. Wiring of Primitives - Logic Design of Comparator - VHDL Description of a 4-bit Comparator 3.7.3. Wiring Iterative Networks - Design of a 4-bit Comparator - VHDL Description of a 4-bit Comparator 3.7.4. Binding Alternative 3.7.5. Top-Down Wiring - Sequential Comparator - Byte Latch - Byte Comparator 3.8. Behavioral Description of Hardware [9] 3.8.1. Process Statement 3.8.2. Assertion Statement 3.8.3. Sequential WAIT Statement 3.8.4. Formatted ASCII I/O Operations 3.8.5. MSI-Based Design 3.9. Dataflow Descriptions in VHDL [9] 3.9.1. Multiplexing