SURVEY OF DESIGN TECHNIQUES FOR SIGNAL INTEGRITY
by
Raghuveer Karnati
A Thesis Submitted to the Faculty of
The College ofEngineering
in Partial Fulfillment of the Requirements for the Degree of
Master of Science
Florida Atlantic University
Boca Raton, Florida
December 2003 SURVEY OF DESIGN TECHNIQUES FOR SIGNAL INTEGRITY
by
Raghuveer Kamati
This thesis was prepared under the direction of the candidate's thesis advisor, Dr. Ravi Shankar, Department of Computer Science and Engineering, and has been approved by the members of his supervisory committee. It was submitted to the faculty of The College of Engineering and was accepted in partial fulfillment of the requirements for the degree of Master of Science.
SUPERVISORY COMMITTEE: Po_:~ Thesis Advisor
Dr. Zvi Roth
Dr. Sam Hsu
rman, Department of Computer S tence and engineering ~ZL~ Dean, College of Engineering
Division of Research and Graduate Studies Date
11 ACKNOWLEDGEMENTS
I take this opportunity to extend my whole - hearted thankfulness to my thesis advisor and mentor Dr. Ravi Shankar, whose vision and commitment got me here from the basics of a transistor to Signal Integrity in Deep Sub-Micron designs. I thank my committee members Dr. Sam Hsu and Dr. Zvi Roth for going through my manuscript and for their valuable comments. I extend my thanks to my friend Ghaiyyur Quraishi, Application
Engineer, Mentor Graphics Corporation, for his help with parasitic extractors and his strong support. I thank Dr.Khoman Phang and Vincent Mui for giving access to their work on Substrate Coupling Noise.
I extend my thanks to Vanitha Siva Subramanyam for her help with conclusions and figures of my thesis and Anbuselvan Kuppuswamy for helping me with concepts of signal integrity in RF and PCB designs. I appreciate Haritha Jillelllamudi for her support and help with arranging my thesis. I also thank Dr. Surya Prasad Jayadevappa for his valuable suggestions. I thank Soham Soni for being my partner in Assura Evaluation project. I thank my colleagues at CVSI, Gaurav Shah and Alok Seth for patiently listening to my ideas for my thesis. I thank Jigisha Goswami and Abhijit Ajmera for
lll helping me with system problems. I thank my Uncle, Aunt and Vineet for their support through out this work. I also thank Dr. Tarun Prasad for his cooperation. I extend my gratitude to my family, who always gave me the motivation to succeed. Last but not least,
I thank Lord Raghavendhra for his blessings, which gave me the strength and courage to complete this work successfully.
IV ABSTRACT
Author: Raghuveer Karnati
Title: Survey of Design Techniques for Signal Integrity
Institution: Florida Atlantic University
Advisor: Dr. Ravi Shankar
Degree: Master of Science
Year: 2003
Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems that effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools
and make recommendations that aids in developing a methodology for perfect design
closure with an emphasis on signal integrity. These recommendations would form a basis
for developing a methodology to analyze interference effects at higher levels of
abstraction.
v LIST OF CONTENTS
List of Figures ...... xiii
List of Tables ...... xvii
Glossary ...... xviii
1. INTRODUCTION ...... 1
1.1. Introduction ...... 1
1.2. Deep Submicron Design ...... 1
1.3. Approach Used for Literature Search, Analysis and Synthesis ...... 6
1.4. What is Signal Integrity ...... 10
1.5. Introduction to Common Signal Integrity ...... 13
1.6. How signal Integrity Effects Affect DSM Designs ...... 17
1. 7. Overview of this Report ...... 19
1.8. Summary ...... 20
2. SIGNAL INTEGRITY ISSUES AT ABSTRACT IP LEVEL. ••.••...... •••. 21
2.1. Introduction ...... 21
2.2. Signal Integrity Issues at Abstract IP Level...... 24
2.2.1. A Designers Perspective ofSI Issues ...... 25
vi 2.2.2. I P Authors Perspective ofSI Issues ...... 29
2.2.3. I P Block Integrators Perspective of SI Issues ...... 32
2.2.4. General Techniques for Solving SI Issues in SoC Designs ...... 34
2.3. Overview of Signal Integrity Specs for IP Blocks ...... 34
2.4. Summary ...... 36
3. SIGNAL INTEGRITY ISSUES AT IMPLEMENTATION
LEVEL ...... 37
3.1. Introduction ...... 37
3.2. Interconnect Noise Fundamentals ...... 38
3.3. Crosstalk Analysis ...... 40
3.3.1. Devgan Model...... 41
3.3.2. Lumped RC Model...... 42
3.3.3. Distributed Two Pi RC Model...... 43
3.4. Crosstalk Reduction ...... 44
3 .4.1. Routing ...... 44
3.4.1.a. Grid -Less Routing Mode- Wire Spacing ...... 45
3.4.1.b. Gridded Routing Model- Channel Routing ...... 46
3 .4.2. Wire Ordering ...... 48
3.4.3. Buffer Insertion ...... 48
3 .4.4. Intentional Skewing ...... 49
3.4.5. Transistor Sizing ...... 50
3.4.6. Power supply Shielding ...... 50
Vll 3.4.7. Raised cosine Signaling ...... 51
3.5. Comparative Study of Crosstalk Reduction Techniques ...... 52
3.6. Power Grid Noise Fundamentals ...... 53
3.7. Power Grid Analysis ...... 56
3.7.1. Static Approach ...... 57
3.7.2. Dynamic Approach ...... 58
3.7.3. Analyzing Power Grid Data ...... 60
3.7.4. Electromigration Analysis ...... 61
3.8. Power Grid Noise Reduction Techniques ...... 62
3.8.1. Circuit Techniques ...... 62
3.8.1.a. Increasing Fall Time (tf) or Rise Time (ta) ...... 62
3.8.1.b. Reducing Switching Voltage (Vsw) ...... 63
3.8.l.c. Reducing Switching Capacitance (Csw) ...... 63
3.8.2. Improved Noise Immunity ...... 63
3.8.2.a. Dynamic Logic ...... 63
3.8.2.b. Regulated Supply ...... 64
3.8.2.c. Differential Signaling ...... 64
3.8.2.d. Transmitting Reference Level...... 65
3.8.2.e. Substrate Referencing ...... 65
3.8.3. Power Grid Noise Suppression ...... 66
3.8.3.a. Separate Supply/Guard Rings ...... 66
3.8.3.b. Decoupling Capacitance ...... 66
3.8.4. Reducing Electromigration Problems ...... 67
Vlll 3.9. Substrate Noise Fundamentals ...... 68
3.9.1. Parasitic Effect ofSubstrate ...... 68
3.9.2. Substrate Noise Coupling Effects in Mixed Signal
Integrated Circuits ...... 70
3.10. Modeling Techniques for Substrate Noise Coupling ...... 72
3.10.1. Finite Difference Mesh Method ...... 72
3.10.2. Boundary Elements Method ...... 76
3.10.3. Preprocessing Analytical Method ...... 83
3.1 0.4. Simple Resistive Macromodel Method ...... 85
3.10.5. Summary of Trade-off of Substrate Noise Coupling
Technique ...... 88
3.11. Substrate Noise Coupling Reduction Techniques ...... 90
3.11.1. Guard Ring ...... 90
3.11.2. N- Well Trenches ...... 91
3.11.3. Supply Bounce Reduction ...... 91
3.11.4. Floorplanning ...... 92
3.12. Inductance Noise Fundamentals ...... 95
3.13. Inductance Analysis ...... 92
3.13.1. Partial Equivalent Elements Circuit (PEEC) Model...... 96
3.13.2. Loop Inductance Approach ...... 100
3.14. Design Issues and Guidelines ...... 102
3 .14.1. Shielding ...... 103
3 .14.2. Twisted- Bundle Layout Structure ...... 103
IX 3.14.3. Staggered Inverter Patterns ...... 104
3.14.4. Inter-Digitated Wires ...... 105
3.14.5. Shield Insertion and Net Ordering ...... 105
3.14.6. Dedicated Ground Planes ...... 105
3.15. Summary of Signal Integrity Effects, Analysis Models and
Reduction Techniques ...... 106
4. SIGNAL INTEGRITY MANAGEMENT IN PHYSICAL DESIGN
FLOWS ...... 108
4.1. Introduction ...... 108
4.2. Early Signal Integrity Design Planning ...... 109
4.3. Signal Integrity Management...... 113
4.4. Signal Integrity Sign-off ...... 114
4.5. Signal Integrity Aware Methodologies for Physical Design ...... 115
4.5.1. Early Functional and Delay Noise Analysis Methodology ...... 115
4.5.2. Custom Wire load Model...... 122
4.5.3. Design Small Blocks, then Assemble them ...... 123
4.5.4. Constant Delay Synthesis ...... 123
4.5.6. Placement Aware Synthesis ...... 124
4.6. Tool Driven Physical Design Flows (From Signal Integrity Perspective) ... 125
4.6.1. Cadence Design Systems ...... 125
4.6.2. Synopsys Inc ...... 126
4.6.3. Sequence Design Inc ...... 127
X 4.6.4. Monterey Design Systems ...... 129
4.6.5. Magma Design Automation ...... 130
4.7. Summary ...... 132
5. TOOLS FOR SIGNAL INTEGRITY ...... 133
5.1. Introduction ...... 133
5.2. Sequence Design Inc ...... 134
5.2.1. Physical Studio ...... 134
5.3. Synopsys Inc ...... 139
5.3.1. Prime Time SI...... 139
5.4. Cadence Design Systems ...... 143
5.4.1. Celt IC ...... 143
5.4.2. Voltage Storm ...... 149
5.4.3. SeismIC ...... 153
5.5. Monterey Design Systems ...... 156
5.5.1. Dolphin ...... 156
5.6. Magma Design Automation ...... 160
5.6.1. BlastNoise ...... 160
5.6.2. Diamond SI Sign-offVerification- Level SI...... 163
5.7. A Comparison of Signal Integrity Tools ...... 166
5.8. Summary ...... 170
Xl 6. DISCUSSION ...... 171
6.1. Crosstalk ...... 171
6.1.1. Routing ...... 173
6.1.1.a. Grid -Less Routing Mode - Wire Spacing ...... 173
6.1.1.b. Gridded Routing Model- Channel Routing ...... 173
6.1.2. Wire Ordering ...... 17 4
6.1.3. Buffer Insertion ...... 175
6.1.4. Intentional SkewiJ;lg ...... 175
6.1.5. Transistor Sizing ...... 176
6.1.6. Power supply Shielding ...... 176
6.1.7. Raised cosine Signaling ...... 177
6.2. Power Grid Noise ...... 178
6.3. Substrate Noise ...... 180
6.4. Inductance Noise ...... 182
6.5 Recommendations Based on Our Survey ...... 183
7. CONCLUSIONS ...... 185
Bibliography ...... 188
Xll LIST OF FIGURES
Fig 1.1. Feature Size Vs Delay ...... 4
Fig 1.2. Feature Size Vs Capacitance ...... 5
Fig 1.3. Model Flow ...... 7
Fig 2.1. Interconnect Performance Parameters for SoC Designs ...... 24
Fig 2.2. High Level Methodology for SI Specs, withAMS and I-V Specs ...... 36
Fig 3.1. Types oflnterconnect...... 39
Fig 3.2.a. Signal Delay Caused By Crosstalk Noise ...... 39
Fig. 3.2.b. Logic Error Caused By Crosstalk Noise ...... 40
Fig.3.3. Lumped Model for Noise Glitch Analysis ...... 42
Fig 3.4. Distributed Model for Noise Glitch Analysis ...... 43
Fig 3.5. Non Uniform Wire Placement ...... 46
Fig 3.6. Layer and Track Assignment ...... 47
Fig 3.7.a. Without Buffer...... 48
Fig 3.7.b. With Buffer ...... 48
Fig 3.8. Shielding Implementation ...... 51
Fig 3.9. Crosstalk Noise Spectrum for Square and RCA Waveforms ...... 52
Fig 3.10. Energy Cone ...... 54
Fig 3.11. Power Supply Voltage Drop ...... 55
Fig 3.12. Interconnect With Electromigration Failure ...... 55
xm Fig 3.13. Return Path through Inductance Causes di/dt Noise ...... 65
Fig 3.14. On-Chip Capacitance and Bonding Wire Inductance Form an LC Tank
With Resonance Frequency ro and a Damping Factor~· ...... 67
Fig 3.15. Parasitic Effect on a Capacitor Made of Two Polysilicon Layers ...... 69
Fig 3.16.a. Substrate as a Parasitic Return Path ...... 69
Fig 3.16.b. Substrate as a Parasitic Path to AC Ground ...... 70
Fig 3.17. The Substrate Noise Coupling Problem ...... 71
Fig 3.18.a. A Control Volume in the Box Integration Technique ...... 73
Fig 3.18.b. Capacitances and Resistances around a Mesh Node in the Electrical
Substrate Mesh ...... 73
Fig 3.19.a Geometry of Multi-Layer Doping ...... 79
Fig 3.19.b. Two Equi-potential Contact Coordinates on the Surface ofthe Substrate ..... 79
Fig 3.20.a. Two Points Substrate Impedance Ports Separated By Distance, d ...... 84
Fig 3.20.b. Determining Resistive Coupling between Ports Using Point-to-Point
lmpedance ...... 84
Fig 3.21. Macromodel For the Substrate When Thee Back Plane is Ground ...... 86
Fig 3.22. Guard Bands Layout...... 90
Fig 3.23. On-Chip Supply Bounce Due to the Voltage Drop across Bond-Wire
Package Inductance ...... 91
Fig 3.24. Good Floorplanning to Reduce the Effect of the Substrate Noise Coupling ..... 92
Fig 3.25. Self Inductance ...... 93
Fig 3.26. Mutual Inductance ...... 94
Fig 3.27.a. Short Circuit Current...... 97
XIV Fig 3.27.b. Charging Current From Capacitance to Ground ...... 97
Fig 3.27.c. Currents in Driver-Receiver Grid Topology ...... 97
Fig 3.28.a. Single Signal Net for Lumped RLC Model...... 100
Fig 3.28.b. Circuit Model for Lumped RLC ...... 101
Fig 3.28.c. Single Signal Net for Distributed RLC Model ...... 101
Fig 3.28.d. Circuit Model for Distributed RLC ...... 101
Fig 3.29. Shielding ...... 103
Fig 3.30. Twisted Bundle Layout ...... 104
Fig 3.31. Staggered Inverters ...... 104
Fig 3.32. Inter-Digitated Wires ...... 105
Fig 3.33. Ground Planes ...... 106
Fig 4.1. Signal Integrity Management throughout IC Design Flow ...... 111
Fig 4.2. SI Management Methodology from Block Level, Platform Level and
Chip Level Flow ...... 118
Fig 4.3. Post-Route Functional Noise Repair...... 121
Fig 4.4. Cadence RTL-GDSII Flow ...... 126
Fig 4.5. Synopsys Timing and Signal Integrity Analysis Flow ...... 127
Fig 4.6. Sequence Nanocool Design Flow ...... 128
Fig 4.7. Monterey's "Global Design Technology" Flow ...... 130
Fig 4.8. Magma's Hierarchical RTL to GDSII Flow ...... 131
Fig 5.1. Pre-Route Mode ...... 137
Fig 5.2. Post-Route Mode ...... 138
Fig 5.3. Prime Time SI Crosstalk Analysis Flow ...... 142
XV Fig 5.4. CeltiC Data Flow ...... 146
Fig 5.5. IR Drop Analysis ...... 150
Fig 5.6. SeismiC Data Flow ...... 154
Fig 5.7. Magma Crosstalk Analysis, Two Pi RC Modeling ...... 162
Fig 5.8. Magma's Signal Electromigration (EM) Analysis ...... 163
Fig 5.9. The Resistive Power Grid Network ...... 165
xvi LIST OF TABLES
Table 1.1: International TechnologyRoadmap for Semiconductors (1999) ...... 3
Table 3.1: Comparison of Crosstalk Reduction Techniques ...... 53
Table 3.2: Table 3.2 Values of the Parameters Cmn Based on Different Conditions ...... 80
Table 3.2: The Summary and Trade-offbetween Advantages and Limitations in
Different Substrate Noise Coupling Techniques ...... 89
Table 3.3: Summary of Signal Integrity Effects, Analysis Models and Reduction
Techniques ...... 106
Table 5.1: A Comparison of Signal Integrity Tools ...... 166
Table 6.1: Comparison of Crosstalk Reduction Techniques ...... 178
Table 6.2: Recommendations Based on Survey of Analysis Methods, Reduction
Techniques and EDA Vendor Tools for Signal Integrity in Integrated
Circuit Design ...... 184
xvn GLOSSARY
AC Alternating Current ALF Advanced Library Format ASIC Application Specific Integrated Circuit ASSP Application Specific Standard Product A WE Asymptotic Waveform Evaluation BiCMOS Bi-Polar Complementary Metal Oxide Semi-Conductor CAD Computer-Aided Design CMOS Complementary Metal-Oxide Semiconductor CTE Common Timing Engine DC Direct Current DCT Discrete Cosine Transform DEF Design Exchange Format DSM Deep Sub-Micron DSPF Detailed Standard Parasitic Format ECO Engineering Change Order EDA Engineering Design Automation EM ElectroMigration GDSII Geometric Data Stream II GHz GigaHertz GUI Graphical User Interface IC Integrated Circuit ILM Interface Logic Models 110 Input/Output IP Intellectual Property IRDrop Current Resistance Drop LEF Library Exchange Format
xviii MHz MegaHertz MTF Message Text Format NRE Non-Recurring Engineering PEEC Partial Equivalent Elements Circuit PKS Physically Knowledgeable Synthesis RCA Raised Cosine Approximation RCDB Resistance Capacitance Data Base RF Radio Frequency RLC Resistance, Inductance and Capacitance RMS Root Mean Square RSPF Reduced Standard Parasitic Format RTL Register Transfer Level SBPF Synopsys Binary Parasitic Format SDF Standard Description Format SE-PKS Silicon Ensemble-Physically Knowledgeable Synthesis SI Signal Integrity SiGe Silicon Germanium soc System On Chip SPEF Standard Parasitic Extraction Format SPICE Simulated Program with Integrated Circuit Emphasis STA Static Timing Analysis TCL Tool Command Language TLF Timing Library Format TWF Timing Window File UDN User Defined Noise vc Virtual Component VHDL Very High Speed Integrated Circuit Hardware Description Language VLSI Very Large Scale Integration VSIA Virtual Socket Interface Alliance 3-D Three Dimensional 3G Third Generation
XIX To
My uncles, Satyam Polineni and Umamaheswara S Prasad Chapter 1
Introduction
1.1. Introduction:
Decades of remarkable microelectronic technology development has largely benefited from transistor scaling. The smaller feature size allows both higher chip density and higher transistor performance simultaneously [Mbou03]. With shrinking feature sizes, the average delay of a logic gate is now dominated by the interconnection (metal wires) rather than by the transistor itself. Most of the potential electrical problems, such as crosstalk, critical timing, substrate bounce and clock skew, etc. are related to the signal propagation and/or high (peak) currents through these metal wires.
1.2. Deep Submicron Designs:
Designs with feature size of 0.35 J.Lm and below are termed as Deep Submicron Designs.
Typical features of Deep Submicron Devices includes Operating frequency of 2.5 GHz,
Operating Voltage of 1.5 Volts and consists of about 50 Million Devices [Ment02]. Deep
Submicron effects - particularly those relating to interconnects - have thus been billed as
1 potential show stoppers to the continuation of Moore's law. Among the effects commonly mentioned are [Keut03]:
• Signal Integrity
• Increased power dissipation
• Design Complexity
• Chip Packaging/ Testing
• Higher Design on Recurring Engineering (NRE) Cost
Signal Integrity in Deep Submicron Designs affects:
• The rising resistance - capacitance (RC) delay of on-chip wiring
• Noise considerations such as crosstalk delay and delay unpredictability
• Reliability concerns due to rising current densities and oxide electric fields
Many factors often have to be considered simultaneously and evaluated carefully to uncover potential noise problems [Keut03]. Global or local power supply variations may lead to reduced noise margins and false switching. They may also cause variations in gate delays that lead to timing errors. A glitch introduced through cross-coupling capacitance may directly lead to functional failures in latches or dynamic logic circuits. Cross coupling capacitance, a significant portion of total wire capacitance, can also give rise to significant changes in wire delays, which is already the dominant delay for many signal nets.
2 As Semiconductor technologies evolve at an very aggressive pace, increasing frequencies together with decreasing geometries lead to a number of issues that Integrated Circuit
(IC) designers can no longer ignore. Table 1.1 shows the relation between interconnects and shrinking transistor size.
Table 1.1. International Technology Roadmap for Semiconductors [Keut03]
Technology in J.lm 0.35 0.25 0.18 0.13 0.15 0.10 0.07 0.05
Year 1995 1997 1999 2001 2003 2006 2009 2012
Number of in'leroonned layers 4-5 6 6·7 7 7-8 7-8 8-9 9
Max lfC length (metersichip) 360 820 1480 2160 2840 5140 10000 24000
ln1eroonnect pitch {nm) 800 590 420 360 300 240 170 130
Metal height/width aspect ratio 1.5 1.8 1.8 2.0 2.1 2.4 2.7 3.0
On-chip high performance clock (MHz) 500 750 1250 1500 2100 3500 6000 10000
VDO(V) 3.3 2.5 1.5 1.35 1.2 1.2 1.2 1.2
The key trend in the move from 0.5 f.Lm to 0.10 f.Lm and below process technologies is the dominance of the interconnect to a point where IC design becomes interconnect driven.
Dominance of the Interconnect:
Interconnect starts to dominate the total delay of signals and the trend illustrates the fact that it will only become worse as process size continues to shrink. Fig 1.1 shows the relation between shrinking transistor size and delay. In order to overcome this problem, technologists are introducing new materials such as copper and low-k dielectrics in order to reduce both resistance and capacitance of interconnects [Saxa03]. However, these efforts, while providing temporary relief do not eradicate the interconnect dominance, and introduce other complications in both modeling and analysis. (For instance, copper 3 resistivity is dependent on the width of the interconnect, and use of low-k dielectric i~ localized, which adds to the complexity of the modeling of coupling capacitance).
30
25
~ 20 10 5 0 0.7 0.5 0.3 0.1 Technology Generation (Microns) Fig.l.l. Feature Size Vs Delay [Keut03] Dominance of the Coupling Effect: In order to account for interconnect in today's design flows, design methodologies have been adapted and, throughout the flow, a more interconnect centric methodology is emerging. However, so far, most of the interconnect aspect of a circuit timing behavior has been estimated using crude assumptions, one of which being that the interconnect delay can be expressed as a linear function of the interconnect length. This assumption relies on the fact that a net capacitance is composed of an area and a fringe component, whereas the coupling between adjacent shapes is negligible [Guth97]. Fig 1.2 shows the increasing overall capacitance with decreasing transistor size. 4 ... 3.5 oTa.~ 'Iii' 3 ~~%':).; '~~>~\s:i; E ('\ v Li 2.5 v c !! 2 "l:l c= c.. !'C u 1.5 1 0.5 0 0.5 0.35 025 0.18 0.15 0.13 0.1 0.07 0.05 Technology Generation Microns Fig.1.2. Feature Size Vs Capacitance [Keut03) Impact of Conpling on Design Performance: Coupling capacitance becomes the first order component of overall net capacitance, and measuring its effect accurately is critical when assessing the overall design performance [Poll02]. Today's complex circuits with die sizes over 300 ~-tm2 , a critical bus traversing only a fourth of the die will have an interconnect length over 15 ~-tm. Even more critical are clock networks, where it is common practice to have a wiring as long as 100 ~-tm. On such long wires, coupling is a major part of the total net delay, and a worst case analysis shows that the impact is enormous. This worst case scenario has the merit to provide enough guard banding to the design flow which guarantees the overall performance of the circuit. On the other hand, because this approach tends to over- estimate the effect of coupling, the result will be sub optimal, either from an area point of view (too many 5 buffers), a power consumption point of view (use of high-drive buffers) or a performance standpoint (not able to design the fastest circuit the process could deliver). 1.3. Approach used for literature survey, analysis and synthesis: To start with, we defined the problem domain as: Evolve method(s) to enhance design productivity so far as the impact of silicon chip fabrication on system design is concerned. This goal originated from a project with iDEN division, Motorola Inc., entitled "Design Productivity Initiative". Our goal here was to identify the methodologies, languages and tools that are available and that can aid in reducing the design time, specifically with regard to the impact of chip fabrication on chip design. We chose the specific topic of signal integrity, considering its importance in present and future integrated circuit designs. ITRS has identified signal integrity as one of the five cross-cutting challenges, and only one of the two that are fabrication pertinent, the other one being manufacturing integration [ITRS02]. Signal Integrity also refers to variety of issues which expanded our scope significantly. 6 Model Flow: Fig 1.3. Model Flow Signal Integrity: The foundation for our model started with understanding the concept of signal integrity, factors that contribute to deterioration of signal integrity, and their effects on system performance. We depended mostly on Engineering Design Automation (EDA) magazines [UnAu03, Sing03] and books such as [Sinh03] by Raminder Pal Singh. Identify Benchmarks: After understanding the concepts and their effects our next target was to identify guidelines or benchmarks for signal integrity. We noted that Virtual Socket Interface Alliance (VSIA) is one such organization that benchmarks specifications for signal integrity in Intellectual Property (IP) blocks [VSIA03]. We have collected and presented some of their views on signal integrity from the perspectives of a designer, IP block 7 author, and IP block Integrator. Most of the thesis notes were collected from [VSIA03] and websites of several EDA vendors [Cade02, Magm02] along with EDA magazines [Ohr02, Sing03]. Catalogue Analysis Methods: Signal integrity causes delay or nmse at the high-level but it is represented with resistance, capacitance and induction (RLC) at circuit level. Our next aim was to understand signal integrity at circuit level, and identify the potential contributors to deterioration of signal integrity circuit level. For this purpose we referred to books such as [Raba96, Sain02]. This gave us a good understanding of effects of resistance, capacitance and inductance on integrated circuits. Then our focus was to understand, how these contributors can be modeled and their effects can be analyzed. Several conference papers such as [Deva97, Rahm98, Roac70, Ranj96] were analyzed to understand different methods of modeling and analysis. Several methods were also provided in the subsequent chapters. Catalogue Reduction Techniques: Once it is modeled and their effects are analyzed they should be reduced for better signal integrity. Our next goal was to understand and analyze several reduction techniques that are widely used in the industry. We also analyzed several methods from academia which are undergoing research, as today's methodologies contribute to tomorrow's tools. This search was done mostly from several conferences [Tsui97, Kozy97, Lim97, Mass98], 8 EDA vendor websites [MontOl, Cade03, Cade03a], and publications from research groups [CongOl, CongOl, HeydOl]. This gave us a good understanding of modeling and reduction of factors affecting signal integrity. Methodologies: Then our focus shifted to the understanding of the importance of signal integrity in physical design flows. We noted that signal integrity must be dealt at every level of the physical design flow. Some reports from industry and academia are provided to support our claim. Then we started analyzing conventional industry wide accepted physical design flows along with tool driven EDA vendor flows. We noticed that the industry norm is to perform analysis and reduction of signal integrity just prior to tape-out. We also noticed the interest of some EDA vendors in acknowledging the importance of signal integrity by moving the analysis and reduction phase to earlier levels of the flow rather than just prior to sign-off [Mcca02]. Our thesis notes are dependent on conference papers [Bece03, Keut98], EDA vendor websites [Cade02a, Sequ02a, Sequ03c] , and Industry reports from several user groups such as [Mont02, Magm03, Deep02]. Signal Integrity Tools: We analyzed several conference papers and reports in identifying the perfect design closure with an emphasis on signal integrity. But we were less clear on how our catalogued analysis and reduction techniques are being utilized in the present EDA vendor tools. Our next target was to understand how the present tools are satisfying the needs of today's integrated circuit design. For this purpose we tried to understand the 9 relationship between the analysis models and reduction techniques. We analyzed several analysis and reduction techniques that were incorporated in today's tools. We noticed a gap in the tools in addressing the future issues. Present tools are still striving to handle interconnect crosstalk and power grid noise. Efficient tools are yet to come in the areas of substrate noise and inductance extraction and reduction. This thesis notes in this area were mostly based on conference presentations by EDA vendors [Dutt03, Land03, HoltOl], EDA vendor websites [Cade02b, Cade03b, Mont02a], user groups [Deep02, Data02]. Proposed Recommendations: This survey gave us a clear understanding of the effects of signal integrity in integrated circuit design at deep sub-micron technologies. We have provided several comparative analysis tables which aid in developing a methodology for reducing deterioration of signal integrity in deep sub-micron designs. Our literature survey also formed the basis for developing a high-level methodology to analyze interference effects. This high-level model analyzes interference at transaction level with parameters from circuit level. We are now focusing on incorporating an analysis model that effectively calculates the RLC parameters for this high-level methodology. 1.4. What is Signal Integrity? Signal integrity includes all IC design effects that cause the design to malfunction due to the distortion of the signal waveform. Currently, cross-coupling capacitance dominates 10 the inter-layer capacitance with every new process technology, because the wires are getting much closer to each other. Designing integrated circuits (ICs) using 0.18-micron and smaller process technologies poses tremendous challenges for IC design teams. The number of silicon failures that are caused by signal integrity problems is on the rise due to the lack of existing design tools and methodologies that can address these issues effectively. As a result, the importance of integrating signal integrity solutions into the IC design flow is growing [Sylv99]. The term "signal integrity" is often used to refer to a broad set of issues, such as: • Crosstalk noise and the detrimental effects it can have on chip operation • Electromigration both in signal lines and power distribution networks • IR (voltage) drop in power lines that can cause chip operational problems • Manufacturing-related issues that if not addressed can lead to chip failure Incorporating signal integrity solutions into the IC design flow thus becomes a necessity. Timing is dominated by interconnect-dependent RC delay in deep-submicron designs. Previously dismissed as secondary effects, cross coupling, via resistance, inductance, power integrity and wire self-heating become first-order design parameters. Design flows using various point tools fail to predict final timing during early stages of the design. The ever-increasing complexity of system-on-chip design, coupled with uncorrelated tool flows, makes it more difficult to achieve design closure on all fronts [PeteOO]. Special tool capabilities are needed to ensure that all aspects of the design, from timing closure to signal integrity to power requirements, are to be addressed simultaneously. The ability of 11 a physical design system concurrently to analyze and correct for various signal integrity problems during a physical implementation flow is highly dependent on the architecture ofthe design system. A single data model, combined with an integrated design system, is necessary to address deep-submicron effects efficiently and to provide design closure in a timely manner. With the scaling of the horizontal dimensions of wires, the aspect ratio of the horizontal to vertical dimensions is reduced, resulting in increased ratios of coupling capacitance (lateral) to ground capacitance (over or under crossovers or to substrate). Depending on the relative rate of switching (rise and fall times ofthe signals) and the amount ofmutual capacitance, there can be significant crosstalk noise [Sequ03a]. Deep-submicron designs often contain millions of devices. The current densities (current per cross-sectional area) in the power and signal lines are consequently high and can result in either power or signal electromigration problems. The electron "wind" induced by the current in the metal power lines causes metal ions to migrate. That phenomenon of transport of mass in the path of a de flow, as in the metal power lines in the design, is termed power electromigration. The power electromigration effect is harmful from the point of view of design reliability, since the transport of mass can cause open circuits, or shorts, to neighboring wires. In most conventional IC design flows signal integrity analysis is performed as a post layout activity. Unfortunately, this is the wrong time to be analyzing for signal integrity 12 effects. Attempting to analyze and correct for these issues post-layout often results in costly and time consuming design iterations, failed schedules, reduced product performance and often, larger die sizes and poorer manufacturing yield. In general, signal integrity refers to the physical effects that cause signal deterioration and physical deformation, both of which pose the threat of design failure. 1.5. Introduction to Common Signal Integrity Effects: Early IC implementation technologies were cell delay dominated. That is, delays associated with the logic elements far outweighed delays associated with the interconnect. By comparison, today's Deep Sub-Micron (DSM) implementation technologies are interconnect delay dominated. Any changes in signal behavior can have a major effect on the quality of the design. Crosstalk: When a signal switches, the voltage waveform of a neighboring net may be affected due to cross-coupling capacitance between interconnects. This effect is called crosstalk. Crosstalk can hurt both timing and functionality [Keut03]. It was not an issue with designs of 0.5 pm or larger line-widths, but as the technology decreases to 0.25 pm and below, the coupling capacitance becomes a significant factor, and induces crosstalk effects that cannot be ignored. Crosstalk analysis determines the noise induced on a net (the victim) by its switching neighboring nets (the aggressors). It can be a static or dynamic analysis. When the victim 13 net is quiescent, or if there is a separation of the switching windows of the victim net from the aggressor net, crosstalk induces a noise that can be analyzed statically. If the aggressor net causes enough voltage variation in the victim net to affect its digital state (i.e., from logical 1 to 0, or vice-versa), the noise propagates and can eventually be latched by a flip-flop to produce a functional fault. When the switching windows of the aggressor and victim nets overlap, crosstalk effect will increase the delay of the victim net if the aggressor net switches in the opposite direction, which may cause setup problems. The crosstalk effect will reduce the delay of the victim net if the aggressor net switches in the same direction, which may cause hold problems. The ratio of cross-capacitance to the total capacitance value of a net is an important variable in the analysis of crosstalk effect. The ratio can provide qualitative information and is very helpful as a screening variable. However, the ratio cannot be used quantitatively to determine the severity of the crosstalk effects. An analysis tool that can simulate the dynamic switching speed is necessary for correct modeling of the crosstalk effect. The switching time of the aggressor net is important in determining the effect of crosstalk delay on the victim net. There can be different delay time based on the switching time of the aggressor input. Electromigration: Electromigration is the problem of net disintegration in a chip due to high current density. This effect has not been a problem until the advent of deep submicron designs [Poll02]. As circuits get faster and bigger, more currents flow through the interconnects. At the 14 same time, the wires get narrower due to lithography and device improvement as technology moves beyond 0.25 micron to 0.18 micron, 0.15 micron and 0.13 micron. The current density, which is the amount of current flowing through an interconnect per unit area, increases nonlinearly with deep submicron designs. It is no longer feasible for manufacturing to provide enough cross-section area on the interconnects to guarantee "net integrity" at all line-width. When there is too much current density through the interconnect for extended period of time, the metal will disintegrate and will cause either open or short in the interconnects. When this failure happens before the end of life of the chip in the system, it causes a system failure. IRDrop: DSM devices are prone to voltage drop (often referred to as voltage (IR) drop) effects caused by the resistance associated with the network of wires used to distribute power and ground from the external pins to the internal circuitry. Voltage drop effects are becoming increasingly significant, because the resistivity of the power and ground tracks rises as a function of decreasing feature sizes (track widths). Also, the rising clock rates seen in modem devices cause a corresponding increase in dynamic power requirements, resulting in dynamic IR drop across power nets [Sequ03a]. The input-to-output delays across a logic gate increase in a non-linear manner as the voltage supplied to the gate is reduced, which can cause the gate to miss its timing specifications. There is also an increase in the interconnect delays associated with underpowered gates. Furthermore, a gate's input switching thresholds are modified when its supply is reduced, which causes the gate to be more susceptible to noise. Last but not least, victim nets driven by 15 underpowered logic gates may become more susceptible to glitches caused by aggressor nets. When the voltage drops in power network or voltage rise in ground network become excessive due to IR Drop, the devices will run at slower speed. The IR drop problem becomes more important for the deep submicron designs with: • Increase in current due to more devices in a design and higher current through each device, • Increase in wire and contact/via resistance due to narrower wires and fewer contacts/vias, and • Decrease of supply voltage to 1.5 volts or below. Inductance: As clock frequency of the design increases to above 500 MHz in process technologies of 0.13 micron and below, on-chip inductance effect can become important for Application Specific Integrated Circuit (ASIC) and Application Specific Standard Product (ASSP) chips. Traditionally, the extraction and simulation of the self-inductance and mutual inductance of all interconnects has not been practical since the compute-intense 3D numerical extraction method that has to be applied [Sequ03a]. Since the inductive effect is only important for long nets with high frequency signals in high performance designs, the extraction, and analysis of the self- inductance effect is focused on the clock nets and mutual-inductance effect is focused on high-frequency bus signals. In order to limit the 16 inductance effect, the most important consideration is to provide current return paths for the high frequency signals. Substrate Noise Coupling: Substrate coupling occurs due to flow of alternating currents in the substrate. These currents are generated by fast-switching (typically) digital devices [Poll02]. For designers, typically designs where problems occur include embedded Data Converters or memories in large ASIC or ASSP ICs. 1.6. How Signal Integrity Effects Affect DSM Designs? Crosstalk: In many cases, the crosstalk effect can cause significant difference in the timing of the switching waveform of the victim net when the switching windows of the aggressor nets and the victim net overlap. When the aggressor nets switch in opposite direction to the victim net, the victim net can have significantly longer switching time and can cause setup time violation at the flip-flops or latches, or output timing window error. When the aggressor nets switch in the same direction as the victim net, the victim net can have significant shorter switching time. This can cause hold time violation at the flip-flops or latches. This is primarily caused by different switching times of the aggressor and victim inputs. 17 IR drop: IR drop can cause the chip to fail due to • Performance (circuit running slower than specification) • Functionality problem (setup or hold violations) • Unreliable operation (less noise margin) There can be significant delay due to decrease supply values. These problems can generally be found at the prototype stage when chips are first delivered from the fabrication unit. However, the effort to identify the IR drop problem can be extensive and can cause significant delay in the design cycle. For many designs, the problem is being addressed by over-designing with wide power buses and multiple power meshes. However, the corresponding reduction of the amount of available routing resource is no longer acceptable. Inductance: When frequencies are high, and lines are wide and long, self-inductance can wreak havoc with delays and mutual inductance can cause noise, crosstalk and other signal-integrity problems [Sequ03a]. On ASICs, inductive effects are generally confined to power and clock lines, although long, on-chip buses can cause problems as well. The low resistance of copper interconnect may also present inductance problems. 18 Substrate Noise Coupling: The parasitic material of substrate influences the behavior of a circuit design. For example, the capacitance of the substrate delays signal transmissions to different locations of the device. The current flowing to the ground through the substrate leaves a voltage drop, which affects the device operation. In addition, the substrate is not a perfect isolation between devices, leading to unwanted "cross-talk" in integrated circuits. 1. 7. Overview of this thesis: The remaining part of this thesis is organized as follows: • Signal Integrity at Abstract Intellectual Property (IP) Level: This chapter provides a background and solutions for signal integrity problems of IP blocks in System On Chip (SOC) design. This chapter also discusses Designer's perspective of Signal Integrity that affect authors and integrators of IP blocks. • Signal Integrity Issues at Implementation Level: This chapter provides information about sources that effect signal integrity at implementation level. It also discusses the solutions to overcome signal integrity problems for successful designs. • Signal Integrity Management in Physical Design Flows: This chapter discusses the importance of early signal integrity analysis. It also discusses several signal integrity aware physical design methodologies that are widely accepted in the industry in detail. 19 • Tools for Signal Integrity: This chapter discusses tools available to combat signal integrity effects like interconnect crosstalk, IR Drop, Electromigration and Substrate Noise from five major EDA vendors. • Conclusion and Future work: This work tries to explore the signal integrity effects in Deep Sub-micron designs. Much work lies ahead. Possible innovations and approaches are discussed in this chapter. 1.8. Summary: This chapter provides an introduction to deep sub-micron designs. The importance of signal integrity issues in deep sub-micron designs is discussed. An introduction to signal integrity issues is provided. A basic understanding of signal integrity effects on integrated circuits is provided. This chapter is concluded with an overview of the thesis about the brief introduction of following chapters. 20 Chapter 2 Signal Integrity Issues at Abstract Intellectual Property (IP) Level 2.1. Introduction: Today's semiconductor fabrication technology can manufacture chips containing tens of millions of gates, thus allowing full systems to be integrated onto a single semiconductor chip. Most of these System-on-Chip (SoC) methodologies involve the selection and integration of appropriate existing internal or third party IP blocks - called Virtual Components (VCs) - based on an architecture which meets the original product requirement. This SoC methodology effort involves the specification of standard formats and interface requirements that will ensure the successful reuse and integration of such Virtual Components (VCs). This allows the separation of VC creation and SoC integration, and has helped legitimize the emerging third party IP business. As a result, most SoC design methodologies focus on the creation of IP libraries containing appropriately collared VCs, along with the techniques to extract and integrate these existing, qualified VCs into a SoC [Sing03]. By the very nature of these methods, there is considerable data hidden within the VCs. The key to successful integration is the provision of sufficient information about each VC to the integrator to allow successful integration of these components. 21 If the components are all soft (i.e., in an Register Transfer Level (RTL) format such as Very High speed integrated circuit Hardware description Language (VHDL) or Verilog), such data hiding is minimized and the blocks may be physically implemented together. On the other hand, if the VCs are hard (i.e., polygons in a layout in, for example, Geometric Data Stream II (GDSII) format), a form of block-based implementation must be used. In this case, the VCs are viewed as black boxes that must be physically integrated together. Their functional, clock, test and physical requirements must be sufficiently delineated to properly integrate such VCs with the rest of the SoC design [Ohr03]. As a VC block author completes the design, there is a need to "package" the design so that it is useful to the integrator. In this packaging process, the design remains unchanged, but several data views are prepared for the design. It is these views that allow the integrator to understand and integrate the design into a larger system without requiring complete visibility into the design. System-on-Chip (SoC) design has taken many meanings for IC designers. However, for all of them, the issues of Intellectual Property (IP) block integration and verification are important problems. Key characteristics of System on Chip (SoC) designs include: • Requirement for IP migration/targeting: Top-down design is necessary. • Multiple feedback loops between analog and digital blocks: Chip-wide functional design and verification is important. • Tight constraints on jloorplanning: Analog blocks need constraints. 22 • Numerous custom analog, digital, and standard cell digital blocks: Many are important from different design groups or IP vendors. • High-performance analog blocks: They are sensitive to nmse and linearity requirements. Process Data Parameters for SoC Designs: SoC designs tend to be a generation or two behind leading edge designs. To help provide some context for the process parameters within which such designs are created, [ITRS02] shows some data in terms of current and next generation process technologies, as well as its usage model for high-performance and cost-performance applications. There is a growing Signal Integrity (SI) problem as designs move toward 0.13 micron processes. More of the wire surface is in the side walls (with aspect ratios growing from 1.8 to 2.1) and the pitch is reducing (from 0.56 to 0.39 microns) while the switching frequencies are increasing (from 30 to 40 GHz) and chip size, which is related to wire length, grows (from 340 to 430 mm2). All of these factors aggravate the already significant crosstalk issues in 0.18 micron processes. Similarly, the reduction in voltage (from 1.8 to 1.5 Volts and below) coupled with the increase in power and current. This coupled with a faster clock (from 1.2 to 1.6 GHz) further stresses power distribution design. Similarly, the 2 tripling of the logic density (from 6.2M to 18M tranistors/cm ) and memory (from 256M 2 to 768M transistors/cm ), and their associated increases in charge and current densities, further aggravates substrate coupling issues. Thus, as shown by these comparisons, all the parameters which are thought to be improving the semiconductor processing also unfortunately worsen the SI issues [Dani02]. 23 2.2. Signal Integrity Issues at Abstract IP Level: Problems with Scaling Technology: As technologies scales, it becomes very difficult to both design (or "author") IP blocks and then integrate them. Typical process parameters of SoC designs consist of signal integrity issues appearing in the form of power grid noise, interconnect crosstalk and substrate coupling. •IR Drop •IR Drop ·Inductance (some • Desi~;~n Around ASIC daslgn around) Inductance • Cro sstall< • Crosstalk •IR Drop •IR Drop •IR Drop •Inductance (some ASSP • Design Around • Design Around Inductance Inductance design around) ·Crosstalk • Crosstalk • Crosstalk •IR Drop pP •IR Drop •IR Drop •IR Drop • Design Around • Design Around • Design Around • Inductance Inductance Inductance Inductance • Crosstalk • Croatalk • croatalk • Crosstalk Analog/RF AI the above issues and "''bstJatt cottpllnu: lssuesarevery deliglt depended 0.35~ 0.25p 0.18p 0.13p Feature Size Fig 2.1.Interconnect Performance Parameters for SoC Designs The snapshot above shows the SI effects designers experience in various design types and technologies [Bisw02]. For System-on-Chip design, these problems refer to the various IP blocks that are provided for integration. Problems that are considered "esoteric" and applicable only to high-end custom designs such as microprocessors often move 24 successively to Application Specific Integrated Circuit (ASIC) designs within a couple of process generations. Thus, one can safely predict that signal integrity issues that have been plaguing high-end microprocessor designers for several years now will also become a significant headache for ASIC and SoC designers in the near future. The rest of the chapter provides a designer's perspective to the signal integrity issues that affect authors and integrators of blocks used in System-on-Chip designs along with a basic understanding of SI issues in SoC designs. 2.2.1. A Designer's Perspective of SI Issues : Dealing With Interconnect Crosstalk: Interconnect crosstalk can be defined as any deviation from the ideal signal waveform propagating in an interconnect wire caused due to the influence of signal transitions in other wires in the neighborhood [Sing02]. This influence is usually due to the capacitive coupling between the victim net and one or more aggressor nets, although inductive coupling is also beginning to show up in cutting edge custom designs. Since ASIC and SoC designs tend to lag cutting edge designs by a generation or two, inductive noise is not yet a problem for these designs. So designers focus is solely on capacitive crosstalk. Capacitive crosstalk is manifested either as a degradation of interconnect delays resulting in a lowered operating frequency for the chip, or in intermittent failure of the chip. When two neighboring signals transition simultaneously, they can affect each other's slew rate (and consequently, transition delay) depending upon their transition directions, relative 25 driver strengths and wire parasitics. Thus, two signals transitioning in the same direction will tend to speed each other up, whereas two signals transitioning in opposite directions will slow each other down. Delay degradation on critical nets can lower the operating frequency of the chip appreciably. In contrast, the failure effect is caused by the voltage pulse induced on a quiescent victim net due to one or more aggressor nets switching in its neighborhood. The problem of interconnect crosstalk is getting worse with each process generation due to non-ideal scaling of wires. Since wires grow relatively narrower and taller with each generation (in order to keep their resistance manageable), the ratio of the coupling capacitance of a wire to its total capacitance is increasing with each generation. Dealing With Power Grid: The trend of increasing design stze and power consumption and decreasing supply voltage (thus increasing current) is resulting in an increase in the amount of power grid IR drop and ground bounce on chips. This trend is critical as the IR drop and ground bounce noise margins are decreasing along with the supply voltage. Chip failures due to power grid issues, whether IR drop or electromigration, are already being discovered by chip designers [Cade02]. Since these issues are related to the number and way components are assembled on a chip and are primarily a global phenomenon, power grid analysis is becoming a required addition to many design flows. Of course, not all designs require power grid analysis, but increasing numbers are susceptible to problems. 26 When components of a design do not see the specified power rail voltage, functional or timing failures will result. Functional failures result from insufficient power for the component to operate properly. Timing failures result from gate delays increasing beyond the timing requirements of the paths (and ultimately cause setup or hold failures). These failures can be intermittent if the power voltage assumption is violated only under certain operating conditions. Electromigration failures could even result in the failure of the chip at a customer site. Because power grid issues are due to interactions between components and the global integration of components, a set of interface specifications are necessary to permit the verification of the power grid by the chip integrator. Another signal integrity issue that will soon become significant while designing power grids is that of providing adequate current return paths to counter inductive coupling. Note that the operating frequency for the purposes of inductance analysis is decided by the signal rise time and not the clock period. As ASIC and SoC designs move towards the gigahertz domain and inductive reactances start becoming comparable to resistances, it will become important to extend the current role of the power grid as a capacitive crosstalk shield to also provide shielding for inductive noise. Although solutions as extreme as power planes that have been used in some high-end microprocessor designs will probably not migrate to ASIC and SoC methodologies, recent work on templated and interdigitated routing in which a track is reserved for power after every few signal tracks seems promising for inductive noise handling in these contexts. 27 Dealing With Substrate Noise Coupling: Substrate coupling occurs in many types of circuits, from small Radio Frequency (RF) designs to large embedded memories. The key aspect of the problem is the flow of AC currents in the substrate. These currents are generated by fast-switching (typically) digital devices. For designers, typically designs where problems occur include embedded Data Converters or memories in large ASIC or ASSP ICs. Designers are faced with a difficult problem of authoring accurate analog blocks in a digital process which will function in unknown substrate environments. This problem inherently limits how aggressive the specifications of the analog blocks can be. Moreover, the integrator of the blocks must be able to verify that the substrate noise will not cause certain blocks to fail - or at least the verification of the integrated block must be accurate and efficient - before the integrator will consider integrating the block. Currently, very little technology exists in the way of CAD (EDA) tools and methodologies, that the designer can rely upon for verification of substrate coupling in the SoC design process. This is because SoC designs tend to be large IC's, and the extraction (and then analysis) problem is mathematically intense - and sometimes complex, depending on the substrate doping layers. Several Analysis and reduction techniques exist for substrate coupling, which are discussed in subsequent chapters. 28 2.2.2. IP Author's Perspective of SI Issues: Interconnect Crosstalk: Crosstalk coupling can occur within any pair of adjacent signals, irrespective of whether they belong to the same logical/physical hierarchy or not. Thus, crosstalk noise can occur between IP block signals routed next to each other, between chip level wires lying next to each other, or between a chip level wire routed next to a IP block wire. It is the third of these three cases that is unique to SoC designs. In each of the other two cases, the designer/integrator has sufficient design visibility and available data to analyze the crosstalk effects completely. However, in the third case, the chip integrator may not have visibility inside the IP block, and the block author may not have knowledge about the chip level environment of the block. Although the techniques used to combat crosstalk noise vary from one design/integration house to another, it is possible to abstract the issues that are common to all interconnect crosstalk scenarios. The data that needs to be communicated for effective control of crosstalk noise effects across the boundary of the IP block can be listed at a level high enough to be largely independent of the signal integrity methodologies and algorithms employed by the designers and integrators. Ideally, it includes some metrics for the maximum permissible noise (including slew and transition window requirements) at the input ports and the maximum noise possible at the output ports (including slews and transition windows and their variation with external load). The IP block author can also specify external no-fly zone/shielding requirements or the locations of crosstalk sensitive interconnect polygons (and potential aggressors, if any, for external wires). The goal is to 29 present a simplified yet reasonably accurate model for the IP block while still preserving its black box nature. Power Grid Design: Component authors generally have very little information about the quality of the power supply at the pins of the component. A common methodology for SoC designs is for the component author and component integrator to agree ahead of time on the voltage to be applied to the component pins given the maximum current required by the component. A typical approach is to assume a fixed level, say 5%, of power degradation to the component. The component author then ensures that the component operates to specifications under this assumption. As components increase in size and are constructed hierarchically, it is the responsibility of the component author to modify the power degradation assumption in order to ensure that the assumptions of the sub-components are maintained as they are used in the larger components. Assuming uniform power degradation, results in conservative design, because not all components see the fully degraded power supply voltage. Components are also generally designed assuming that power enters only from the power pins. A growing trend today is that this assumption is not always valid -- power commonly flows through components as well. Since the amount of current flowing through a component cannot be determined until chip integration, it should be possible to specify current limits on the component pins to make sure electromigration limits of the component will not be violated when integrated in the design. 30 A model is required to represent the power grid behaviors of a component. The model is created by the component author and is applied by the chip integrator. The model must provide some visibility into the component's internals. Because IR drop issues can be investigated in either a static or dynamic sense, various models of a component are possible. In a static analysis, only power grid resistance data is required of the component. In a dynamic analysis, RC data of the component is required. The model of component power consumption must be a function of the loading on the component, so that the total power consumption of the component as well as any dynamic behaviors can be derived once the component environment is determined. The component model must also be able to specify acceptable ranges of input characteristics and output loading. Dynamic modeling will result in larger data sets to represent the model. Substrate Coupling: A block author needs to be careful to plan for guard rings and provide clear guidelines for the integrator to follow to allow for more robust design [Sinh03]. Often, circuits are just designed to be robust (through overdesign and differential techniques) and a lot of slack is built into the required performance specifications. However, this is very difficult to do with current & upcoming standards such as Bluetooth and 3G where the analog and RF blocks are very difficult to design even by themselves (since they operate at 2.45 GHz and more). 31 2.2.3. IP Block Integrator's Perspective of SI Issues: Interconnect Crosstalk: From the integrator's point of view, the main difficulties in analyzing the crosstalk noise effects accurately are the lack of visibility into the IP block and the massive amount of electrical and physical interconnect data and logical/timing window data required for accurate analysis. The data that should be communicated between the IP block author and the integrator can be abstracted in order to enable the latter to get around the first problem (viz., lack of visibility) while analyzing crosstalk effects. There are two approaches that can be used to handle crosstalk nmse Issues. The conservative approach is to increase the delay error bars and flag every gate that can be a potential failure in the worst possible physical realization of the IP block. The problem with this approach is the fact that the worst possible physical realization can often not be identified easily. Thus, a more realistic approach to handling firm or soft IP is for the block author to identify the set of signals that the author feels may be critical, and then communicate maximum coupling ratio or required shielding constraints for them. The integrator must then take these constraints into account while doing the physical design of the chip; the integrator's added visibility into the IP blocks will allow the application of the standard crosstalk noise methodology to the entire chip. 32 Power Grid Design: Integrators have little knowledge of the internals of components, so they might not be aware of operating assumptions the component designer made when designing the component. A common assumption is that power comes into the component, and none passes through, this is not true in practice and has been the source of some failures. Specification of power ports for a component is a common source of disconnect. If a large component has a single long power port passing over the component, there can be questions as to how the port should be used; the various options include only a single connection at one end, connections at both ends, or additional connectivity midway as well. Since the way the component is connected to the global grid can even alter the power grid characteristics in the component (for instance, a power rung of a component can be supplemented by additional metal by the integrator), there must be some way of resolving power port usage models. Integrators need to be able to assume that if the power noise requirements for a component are met, then the component will function properly. In order to test this, the integrator needs appropriate models of the power grid of the components as well as how the components consume power. The component author may also need to be able to provide specifications as to IR drop or electromigration at various points in the component. The integrator's need for tools that are fast enough in analyzing the behavior of the chip after the components are assembled is also of utmost importance. 33 Substrate Coupling: As integration levels rise for analog, RF, and sensitive custom digital blocks, the skill base of the integrator needs to change - from predominantly understanding issues in Standard Cell ASIC block integration, involving a small number of analog blocks, to understanding the multitude of intricate power, interconnect, and substrate issues with many highly sensitive blocks. The whole parasitic model for the IC needs to be modeled. 2.2.4. General Techniques for Solving SI Issues in SoC Designs: • The basic approaches to handling crosstalk noise are either by controlling the signal slew (by driver/receiver sizing or repeater insertion) or by reducing the ratio of bad coupling capacitance to its total capacitance (by wire engineering) [Goer03]. • The general approach to handling power grid noise is to overdesign the power grid of the chip at the cost of metal consumption. • Substrate coupling is handled by placing guard rings around the sensitive IP blocks, grounding the guard rings on dedicated bond pads and dedicated package pins and using floorplanning intelligently to keep noisy digital IP blocks away from sensitive blocks. Several other techniques for handling Crosstalk, IR drop and Substrate Coupling are discussed in following chapters. 34 2.3. Overview of Signal Integrity Specs for IP Blocks: The Virtual Socket Interface Alliance (VSIA) was formed by group of major EDA and semiconductor companies with the goal of establishing both a unified vision for chip industry and the technical standards required to enable the most critical component of the vision: the mix and match of intellectual property (IP) cores from multiple sources [VSIA02]. Much like the way physical components are mixed and matches on a printed circuit board, IP in standardized forms My be rapidly mixed and matched into system chips. To facilitate mix and match, VSIA specifies "open" interface standards, which will allow IP cores or blocks to fit quickly into "Virtual Sockets" at both functional level (e.g., interface protocols) and the physical level (e.g., clock, test and power structures). This will allow VC providers to productize and maintain a uniform set of IP deliverables, rather than requiring them to support numerous sets of deliverables needed for many unique customer design flows. VSIA specifies existing de facto, or open, or proprietary data formats. Additionally, VSIA endorses emerging standards from other groups that meet VSIA technical requirements. The VSIA Signal Integrity specs document explain deliverables, data formats, their associated design guidelines and example designs for the signal integrity (SI) issues of both digital and analog-mixed signal virtual components in SoC design. The specifications are focused on SI issues in the communication between the VC authors and integrators for the integration as hard blocks [Ohr02]. The scope of the work is defined by the boundary conditions and currently limited to power grid, interconnect crosstalk 35 and substrate coupling. This document also discusses the issues related to the power grid and signal electromigration. Issues such as IC package noise are very important in understanding the SI effects in SoC design. These specifications focus on the 0.18~-t process generation dealing with issues that may occur down to 0.13~-t and beyond. Analog/Mixed slgn.. l Digital Virtual Comp~nent (VC) Virtual Component (VC) Analog and Mixed Signal 1-V Specifications Specifications Fig 2.2. High Level Methodology for Using SI Specs, withAMS and 1-V Specs The scope of these specifications has been bounded by the following considerations: • Current and future severity and seriousness of the issues. • Verifiability before manufacturing of silicon. • Appropriateness for the document information between the VC author and integrator. 2.4. Summary: This chapter is started with a discussion of signal integrity metrics at abstract IP level. A brief idea of present system on chip designs is provided. The signal integrity issues such as interconnect crosstalk, power grid noise, substrate coupling noise are discussed from IP block author's, designer's and integrator's perspective. Several design ideas are 36 discussed in this section. Virtual Socket Interface Alliance (VSIA) is a group of major companies with a goal of establishing unified vision for chip industry. Signal Integrity is one concern from VSIA's perspective. A brief overview ofVSIA's signal integrity specs is provided. 37 Chapter 3 Signal Integrity Issues at Implementation Level 3.1. Introduction: The main signal integrity problems are crosstalk noise, crosstalk induced delay variations, power supply voltage drop, substrate coupling and self and mutual inductance. Crosstalk noise and crosstalk -induced delay variations are changes induced in a nominal signal by interference from neighboring nets. These effects have become steadily more important as interconnect lines have become thicker in proportion to their width, with the corresponding increase in the ratio of coupling to grounded capacitance. Crosstalk noise can be treated on several levels- it can be analyzed either exactly through circuit simulation, or approximately by means of various simplifications. The main objective here is not to analyze these problems but to produce a chip that is free of them. Voltage drops in the power supply network, either static or dynamic, are conceptually simple. Since the networks are huge, however, considerable effort has gone into computational simplifications. This also leads naturally into electromigration concerns. 38 Substrate coupling arises since all parts of the chip are built on a common, electrically conductive substrate, the silicon wafer. The effects of substrate coupling are well known among analog designers, especially those that must contend with large noisy digital circuits on the same chip. This problem must be considered during floorplanning, and verified after layout. Inductance is another area that is well understood if efficiency is not a prime concern. Simulating the chip including coupled inductors will give the right result-one that matches silicon. This approach is computationally infeasible for all but the smallest chips. Thus, how inductance can be extracted, how it is modeled, and how it can be avoided are of prime concern. 3.2. Interconnect noise fundamentals: With the scaling of the horizontal dimensions of wires, the aspect ratio of the horizontal to vertical dimensions is reduced, resulting in increased ratios of coupling capacitance to substrate capacitances. Figure 3.1 shows capacitance associated with wires. Cxcoup and Ccrossover represent the coupling capacitances and C fringe and C area represent the substrate capacitances. When the signals in the neighboring wires switch, the coupling capacitors cause transfer of charge between them. Depending on the relative rate of switching (rise and fall times of the signals) and the amount of mutual capacitance, there can be significant crosstalk noise. 39 Ccrossover - Crossover Capacitance Cxcoup - Cross-coupling Capacitance Carea - Area Capacitance Crnnge - Fringe Capacitance Fig 3.1. Types of Interconnect Crosstalk noise between neighboring signal wires can cause two major problems that affect the operational integrity ofiC designs [Magm02]: • Crosstalk delay changes the signal propagation on some of the nets, reducing achievable clock speed as illustrated in Figure 3.2.a. • Crosstalk glitch causes voltage spikes on some nets, resulting in false logic states being captured in the registers as shown in Figure3.2.b. C1oad- Load Capacitance Cune-line- Line-Line Capacitance (a) 40 r--i I f I I r 3. Low:nolse : I I • I I I _____ J I I • I __ Agigte1I&Or Error! Rwire - Wire Resistance Cwire - Wire Capacitance Cc - Coupling Capacitance (b) Fig 3.2. (a) Signal Delay Caused by Crosstalk Noise (b) Logic Error Caused by Crosstalk Noise Attempting to fix the effects of crosstalk after layout is both costly and risky from the point of view of chip design and time to market. These types of effects must be analyzed for and corrected automatically throughout the design flow, starting early in the flow. To efficiently achieve concurrent analysis and correction of crosstalk noise, it is necessary for the place and route engines to have access to incremental extraction and analysis capabilities [RabaOl]. This allows the design to be optimized based on data-driven decisions. 3.3. Crosstalk Analysis: Noise glitch analysis has traditionally been done using transient analysis methods such as SPICE simulations. But the method is costly and impractical for large-scale deep- submicron designs that have hundreds of thousands or millions of nets. In most cases noise analysis can be done using linear circuit models and can be well approximated 41 using linear model reduction methods. Although the reduced order models are much faster than Spice, the higher order models are still expensive in computation time, when a large number of nets are involved. The best methods in the speed-accuracy trade-off are the analysis models that can determine the safe nets. Safe nets are those that have noise values sufficiently less than the noise margins, such that they do not require detailed analysis. The more expensive analysis models, including transient analysis, can then be applied to the smaller number of residual nets to eliminate false warnings. The following are the typical analytical models used for computing the effect of crosstalk glitch on the victim net, as measured at the input pins of the gate connected to the net. 3.3.1. The Devgan Model: The Devgan model estimates the upper bound on the noise glitch value in the victim net due to transitions on capacitive-coupled aggressor nets [Deva97]. While this model is pessimistic it provides the first order budgeting of the noise margins for the noise optimizer. In this model the victim aggressors are RC trees, with the victim initially at a steady state. The max noise voltage induced by the transitions on all aggressors connected to each subnode of the victim is computed as a sum of the displacement current through the coupling capacitors to that subnode. This current flowing from the source to the termination of the victim RC tree lends itself to an Elmore-like computation used for delay calculation in signal trees, but in this case it applies to the upper bound of the induced voltage due to crosstalk glitch. 42 3.3.2. Lumped RC Model: Lumped RC models are useful for fast noise glitch estimation. The resistance value R is a key factor in the accuracy of computation. For noise glitch computation, the victim line is assumed to be at Vdd or Yss· R represents the driver resistance. The resistance changes as the victim net voltage changes due to the crosstalk induced noise. Using timing tables from standard synthesis libraries (.Lib, TLF) is unreliable, since they are characterized under the conditions of input voltage swings and measured around fixed output transition points and lead to underestimation of the noise glitch. The difference in the resistance values are particularly worse for multi-input gates and complex gates such as NAND and NOR cells. With the proper value set for R, reliable values for the glitch can be obtained and the lumped model used as a means for fast computation of the crosstalk glitch estimation. Cc represents the coupling capacitance between the victim aggressor pair and Tr the full transition time of the aggressor waveform, considered to be a saturated voltage ramp. The glitch contributions of individual aggressors, computed at the end point of Tr, are summed up for the final result. The lumped model is especially useful in calculation of the width of the glitch. The width is measured between the 50 percent points of the noise glitch voltage value. Vout Cc - Coupling Capacitance Vout - Output Voltage R Cg - Ground Capacitance R- Output Resistance Tr- Input Voltage Fig 3. 3. Lumped Model for Noise Glitch Analysis 43 3.3.3. Distributed Two Pi RC Model: Distributed two pi RC models takes into account the contributions of coupling capacitance located near the victim net's driver as well as from those located near the input terminals of the gates connected away from the driver [Rahm98]. Rd - Resistance at node d Rs - Resistance at node s Re - Resistance at node e Csl - Capacitance at Sl Cs2 - Capacitance at s2 Cel - Capacitance at el Ce2 - Capacitance at e2 Vout - Output Voltage Tr - Input Voltage Fig 3.4. Distributed Model for Noise Glitch Analysis The above network has a 3-pole transfer function given by: V01JI.(S) = (3.1) Where S1, S2, S3: Poles a1, a2, b 1, b2: weight function dependent on resistor and capacitor values With Poles O>S1>S2 and the most dominant pole: S1 (3.2) Where Vagg - Aggressor Voltage 44 The time response Vout(t) is computed by partial fraction expansion and Inverse Laplace Transformation with initial conditions set to zero. The value of the poles is a function of the resistors and capacitors in the network, which is determined by the position of the individual coupling capacitor from the victim to the aggressor signal wire. The sum of the individual noise contribution at each sub-node of the victim is summed to get the final glitch value for a victim-aggressor pair. Noise from multiple aggressors are computed and composed using either straight sum, or a max() function or Root Sum Square. 3.4. Crosstalk reduction: One way to deal with crosstalk is to minimize its effect via design stage optimizations. Several viable reduction techniques are currently available [Cong97, CongOl]. 3.4.1. Routing: Crosstalk is routing dependent, since the coupling capacitance relies on the wire spacing and overlapping distance. The common routing approach taken by recent work is to apply a conventional routing algorithm first, and then iteratively apply a new algorithm that alters the layout until the crosstalk effect is minimized. This is known as post-layout optimization. To work effectively, an iterative routing algorithm needs to factor in the extracted coupling capacitance from each previous layout. The algorithm should also assume the worst-case signal-switching scenario and take into account the driving capacity of the nets. Crosstalk-avoidance routing falls into two categories. The first uses a grid-less routing model where the spacing between wires is adjusted to reduce the crosstalk [Khoo97, Chen92, Macc02]. The second category uses a gridded routing model 45 where crosstalk minimization works have been done using channel routing [Kirk94, Thak95] and switchbox routing [Gao94]. An example from each category is discussed below. 3.4.1.a. Grid-less routing model- Wire Spacing: When considering crosstalk problems on buses, one of the more intuitive solutions is increasing the space between wires. Wire spacing is a well-liked approach because it does not require additional capabilities from the existing placing and routing tools. In [Chen92], a non-uniform wire placement technique was presented. The number of bus wires N, the width available for spacing W, the average switching rate of the line aL, and the average simultaneous switching rate of two adjacent wires ax are the required inputs of the wire placement algorithm. Using the above information, the algorithm determines a set of wire distance assignment array. Figure 3.5 shows a sample inter-wire distance assignment array, where the bolded lines are the individual wires in a 4-bit bus. 46 W- Total Width dn - Distance between wires dl d2 d3 d4 d5 . . . <. . > . < > ...... * * * * * ...... * ...... * * * .. ... * * ... * ... * .. ... * •* ...... • • • • .. .. • • .. .. • .. •* .. .. • ...... • ...... • .. .. & .. .. • ...... • .. .. • & .. .. • • • • .. .. • • .. .. • .. • .. .. • & .. .. • • • .. .. • • .. .. • .. • .. .. • • & .. .. • • • .. .. • • .. .. • .. • .. .. • • & .. • .. • • • .. .. • • .. .. • .. • .. .. • • & .. .. • • • • .. .. • • .. .. • .. • .. .. • • & .. .. • • • • .. .. • • .. .. • .. • .. .. • & .. .. • • • • ...... • .. • .. .. • & .. .. • • • • ...... • .. • .. .. • • & .. • .. • • • • .. .. • • .. .. • .. • .. .. • • & .. .. • • • • .. .. • • .. .. • .. • .. .. • • & .. .. • • • • .. .. • • .. .. • ... • .. ... • • .. '* • '* • • • • ...... • • '* '* • ... • .. '* • • .. .. * .. • • • .. • • '* .. '* * .. '* • • .. .. • '* • • • .. '* • • '* '* .. * .. '* • • . .. • .. • • • • .. .. • • .. '* • '* • .. .. • • . .. • .. • • • • .. .. • • '* .. • 1 2 3 4 w Fig 3. 5. Non Uniform Wire Placement 3.4.1.b. Gridded routing model- Channel Routing: Many crosstalk-reduction, channel-routing algorithms have been proposed for gridded channel routing [Zhou96, CherOl, Chen97, Zhou97, SaxeOO, Vitt97] . A simple algorithm is considered for giving an idea of the model. First, the net that experiences the worst crosstalk noise is selected as the target [Chen97]. Then, different reassignment techniques can be applied to eliminate the crosstalk effects incurred on this target. For instance, reassigning long parallel wire segments to different layers, such as metall and metal2, can eliminate overlaps. Adjacent wire segments can also be relocated to different tracks or routing paths. The former is called layer reassignment, while the latter is known as track reassignment. Figure 3.6 illustrates the reassignment techniques. After reassignment, if the target net no longer has the worst-case crosstalk effect, then a new 47 target is chosen to repeat the reassignment process. The procedure terminates once no more crosstalk elimination can be achieved. [Original Layout] 1 2 3 5 0 1 4 2 5 6 11 0 7 D 7 6 6 8 trt~ck 1 trtlck 2 track 3 10' trac~ 4 0 9 0 0 10 5 9 14 9 14 D 13 12 4 3 8 12 0 [Modified Layout] 2 3 5 0 1 .4 2 5 6 11 0 7 0 7 6 6 8 track 1 track 2 track 3 track 4 ---·-· Metal Layer 1 Metal Layer 2 Metal Layer 3 Fig 3.6. Layer and Track Assignment Layer reassignment: Wire segment 3 has a long overlap with segment 2. In the modified version, wire segment 2 is reassigned to another layer to eliminate overlap between the two wires. Track reassignment: The overlap between segment 3 and 12 can be eliminated if wire 12 is reassigned from track 3 to track 4. 48 3.4.2. Wire Ordering: Instead of performing post-routing optimizations, crosstalk can be dealt with during the initial routing stage as a wire-ordering problem. This is a subset of crosstalk-driven routing solutions. Finding an appropriate ordering of the nets can lead to significant minimization of crosstalk noise. The process of determining a good wire order can be formulated as follows [Shao02]. Consider that in an NxN crosstalk matrix, the coordinate C(i,j) represents the crosstalk on net i due to an adjacent netj. The wire-ordering problem then resolves to find an ordering such that the total crosstalk is less than a threshold value T. 3.4.3. Buffer Insertion: Traditionally, buffer insertion has been used as a timing optimization technique to reduce the delay of long interconnects. However, buffer insertion can also be used as a crosstalk noise avoidance technique [Alpe99, Dube02, HeydOl, Tenh02, Li97, Chal97, Lill96]. Buffer insertion reduces the parallel lengths of interconnects, which is directly proportional to the crosstalk noise. Figure 3.7 illustrates the noise effect on a victim net, with and without a buffer. 49 I --1II II p IT • • • IT (a) ;fooi"' > NM __;-; I 11 I II IT • ·~ I I ~ J'\.. noise < NM ...1\..1> noise<: NM (b) Fig 3.7 (a) Without Buffer (b) With Buffer In figure 3. 7, the top wire is the aggressor net and the bottom is the victim. The aggressor net induces crosstalk noise on the victim net. NM stands for the noise margin of the receiving gate. As shown in figure 3.7.b, inserting a buffer can distribute the capacitive coupling between the two newly-created wires, which results in a smaller noise pulse on the input of the inserted buffer than in the input of the receiver in graph of figure 3.7.a. As long as the noise induced after buffer insertion is less than the noise margin, then no noise should get propagated to the output due to the buffer's restoring logic function. 3.4.4. Intentional Skewing: Simultaneous switching crosstalk delay, caused by opposite bit transitions on adjacent wires, is an issue that cannot be solved by buffer insertion alone. To prevent this simultaneous switching event, a technique known as "intentional skewing a shift" is used as a complement to buffer insertion [HiroOO]. This technique structures the wires within a 50 bus into alternating wires with normal timing and shifted timing. This way, no adjacent wires will switch at the same time. With the signals on the normal timing lines reaching their destinations sooner, the delayed signals will experience less coupling effect from their neighbors. The shifted timing of a wire can be established either with an inverter chain or a two-phase clocking scheme. Although this technique introduces a delay on the time-shifted wires, the overall bus delay for the shifted wires is reduced because the dominant crosstalk delay is suppressed. 3.4.5. Transistor Sizing: If the victim driver is sized up, then its effective conductance increases, allowing it to withstand transient perturbations by holding a voltage (V dd or Gnd) steadier [Xiao99]. Similarly, if an aggressor driver is scaled down, the amount of noise it can induce on a victim is decreased because it can no longer transition as fast. However, increasing the driver size has a two fold impact on crosstalk. The noise on the wire with the sized driver is decreased, but its neighbors' noise will increase. Although increasing the size of a wire's receiver, while keeping everything else unchanged, will decrease noise on the receiving wire, the impact is insignificant. 3.4.6. Power Supply Shielding: Shielding is another method available for reducing the capacitive coupling. This technique is implemented by adding V oo and V ss "shields" between wires, as illustrated in figure 3.8. This way, the power supply lines isolate the wires and in tum eliminate crosstalk effects caused by adjacent wire transitions [YeeOO]. The process of shielding is 51 applied between cell-placement and routing during the design stage. Other shielding benefits include the creation of a finer power grid distribution, or a more regular power supply routing structure. However, shielding can potentially suffer a significant area penalty. Implementation of a full-shielding chip, where a shield is inserted between every wire, may take up half of all routing resources. Therefore, extra spaces between cells are usually needed to permit additional track routing if shields are used. Additionally, shielding also introduces blockages that are difficult to handle with ordinary routing tool. The sample shielding algorithm proposed was able to reduce the worst-case noise from over 50% of VDD to less than 6% of VDD on two chosen benchmark circuits. The increased area overhead after shielding were 25% and 35% for the two circuits. Vdd- Power Supply Vss- Ground signal vss signal Fig 3.8. Shielding Implementation 3.4.7. Raised Cosine Signaling Raised cosine signaling is a new signaling scheme to reduce crosstalk, where the waveforms for data transfer on busses are modified. The actual capacitive coupling is also a function of the signal frequency [BashOl]. Traditionally, square pulses are used as the basis waveforms due to their simplicity in generation and detection. square 52 waveforms are replaced with Raised Cosine Approximation (RCA) pulses that are band- limited to 2fo frequency, where fo is the fundamental frequency. By band-limiting the transmitted pulses, crosstalk originating from unnecessary high frequency components can be minimized. A sample crosstalk noise spectrum comparison between RCA and square pulses are shown in figure 3.9. 20 ... _...... _ 0 ·----·--·- . . . ' isquare Input fulse -20 m "0 -40 -60 -80 -100 0 2 4 6 8 10 12 14 16 18 20 Frequency (GHz) Fig 3.9. Crosstalk Noise Spectrum for Square and RCA Waveforms 3.5. Comparative Study of Crosstalk reduction techniques: Different Crosstalk reduction and tolerance techniques are compared in terms of effectiveness, delay and area. The effectiveness on the circuit after the application of the techniques, delay introduced due to the applying the technique and area considerations of the technique are tabulated in Table 3.1. 53 Table 3.1 : Comparison of Crosstalk Reduction Techniques [Chou03] Elf'eetive:aess Delay Area Category Wire Spachtg Medium Low Low I Cha11nel Routing Medium Low Low I Wire Ordering Low Low Low ButTer Insertion Low Low I Low Jntc11tional Skewing Low Low Low ' Tran.,istor Sbiag High Medium Medium Power Supply High Low I High I Shielding Raised-Cosine Low Low Low ! Signaling 3.6. Power grid noise fundamentals: Computations in integrated circuits are driven by the energy from a DC power supply. In order to perform computations, this energy is transferred, stored and then dissipated as heat in the integrated circuits. The rate of computations and the number of computing elements in an integrated circuit determine the rate of energy delivery or the power delivery requirements of the circuits. Since the rate of computations is time-varying, the power and current requirements of the integrated circuit will also vary with time. Delivering a time-varying current at a constant supply voltage with nominal variations is 54 the goal of the power distribution network design. The trend of increasing power and clock frequency while reducing power supply voltage causes the power supply network to experience larger dildt noise. Since device threshold voltage does not scale well with the reduced supply voltage in scaled technologies, the gate current drive becomes more sensitive to the supply voltage variations. As a result, circuit designs require that the supply variation remain at least a fixed percentage of the supply voltage [BorkOO, Gron98, Darn98]. With each technology generation, the larger di/dt noise makes it difficult to ensure that the supply variation does not exceed this fixed percentage. Fig. 3.10 shows energy cone that explains how energy is derived and dissipated as heat. Power delivery problem Supply electrical power to the at a specified voltage to the power . contacts . . ----~---~---:------. Remove heat from the heat ; sources to control the internal ;•• temperature ! . Thermal Man age ment . Problem Fig 3.10. Energy Cone The two main concerns in the design of the power grid are the transient voltage variations at nodes in the power grid and the long term reliability of the interconnects in the power grid. The transient voltage variations are caused by the flow of time-varying current 55 through the power distribution network. These voltage variations degrade noise margins (possibly causing functional failure), increase the delay of logic gates, increase clock skew, and reduce gate oxide reliability [MontOl]. Fig 3.11. shows power supply voltage drop. In- Current at Node n Fig 3.11. Power Supply Voltage Drop The interconnects of the power grid become susceptible to electromigration (EM) induced failure when they carry high currents over a sustained period of time. Several CAD tools exist to identify the voltage drop and EM problem locations. The power grid can then be redesigned to enhance its reliability. Fig 3.12 shows electromigration in interconnects. Failed Wire Fig 3.12. Interconnect with Electromigration Failure 56 The current through the signal wires alternate as the drivers charge and discharge the current through the transistors. This gives rise to thermal or Joule heating of the wire, that can lead to mechanical stress and breakdown of the metal structures and stress in the surrounding oxides layers that often leads to shorted neighboring wires. Maintaining the RMS current densities in the signal wires to acceptable levels prevents the problem. There are several techniques at different levels of abstraction that reduce the supply voltage variations and lead to the design of a robust power distribution network [Leun88, Itoh87, Tabo90, Chen96, Larr97, Rain94, Sidi97, Alls91, Hash92]. Post-layout verification of the supply voltage variations and the use of decoupling capacitors to reduce these variations are required in the later design stage. Several techniques and problems for the design of the power distribution network in high-performance integrated circuits were discussed here. 3.7. Power grid analysis: Power grid analysis for either blocks or full-chip can be divided into two basic phases. Each phase can be varied in complexity and accuracy depending on the stage in the design process where the power distribution analysis is applied. Nevertheless, accurate verification requires consideration at the transistor level. First, the circuit description (behavioral, gate or transistor level) as well as the power grid including parasitic elements have to be extracted from the design database. Secondly, the current distribution in the power grid has to be calculated. This can be done in two different ways. One possibility is to calculate the power grid and transistor circuit together. This takes into account the 57 coupled nature of the problem and provides an accurate picture, but also limits the size of the problem that can be handled. The complexity of the problem and run times will limit the application of this method to a block level. Especially for digital circuits, a more efficient two-step technique can be applied. The first step is to calculate the current consumption for all circuit elements assuming ideal power supply values using static or dynamic current data, later on referred to as static and dynamic approaches. The second step is to use computed loading currents to calculate the current distribution in the power grid. The resulting IR drop can be fed back into the first step to improve the accuracy of the current data drawn from the power grid. Usually, one iteration loop is sufficient to get realistic IR drop and current data for the power grid. The separation into two steps allows the exploitation of specialized algorithms during each step which in return improves speed and capacity. Static simulations are useful for fast analysis of the power distribution trends in the design, whereas dynamic simulations can pinpoint problems due to simultaneously switching gates within a block. 3.7.1. Static approach: A static approach to calculate the currents is useful as a first step in power grid analysis. Practical experience has shown that most major power grid design problems will show up during analysis based on static current data. Additionally, performing static analysis is much faster than a dynamic one, allowing a designer to make several iterations quickly while making changes to a portion of the power grid. 58 Accurate static calculation can be performed by considering the amount of charge drawn from the power grid during each clock cycle based on the switching activity at the gate level. The accuracy of this approach depends heavily on accurate device and interconnect capacitance data as well as the accuracy of the actual switching probability. Switching data can be derived from probabilistic analysis as well as vector-based simulation at the behavioral, gate or transistor level [Tsui97, Kozy97, Lim97, Veen84]. The average power dissipation for each gate can be expressed by the relatively accurate approximation [Yuan97]. The average power is given by: Pavg = 1/2 * CL * vdd * Ps * f (3.3) Where, CL- Loading Capacitance vdd- Supply Voltage P s - Switching Probability f- Frequency Where by CL is the effective loading capacitance seen by the gate, Vdd the supply voltage, Ps the switching probability and f is the clock frequency. Static current values estimated in this way are generally very close to actual average current values, and are therefore very useful for electromigration analysis. 3.7.2. Dynamic approach: Dynamic analysis has to be performed to verify instantaneous voltage drops at the power grid due to simultaneously switching gates. Just after a clock transition, many of the gates 59 in a design begin to switch simultaneously, causing peak current consumption and peak IR drop on a power grid. This effect will not be seen using a static current calculation, which is the reason a dynamic verification must be performed for sign off. The dynamic peak IR drop will cause additional delays until the signals settle and may cause timing conflicts in aggressive designs. A representative set of vectors has to be used for dynamic IR drop analysis. Ideally a large set of vectors would be simulated to ensure that no IR drop problems occur under operating conditions. However this is impractical due to the simulation time that would be required to run a large set of vectors. Different techniques have been proposed to either reduce the number of vectors to be considered for a dynamic analysis [Tsui97] or to find a subset from all possible input stimuli representing a similar power distribution [Marc97, Krst97]. In practice, only a few tens of vectors are used to identify IR drop problems. Dynamic power grid analysis presents some unique challenges due to the size of the problem as well as the time required to perform dynamic simulation at the transistor level. To reduce the time required for performing dynamic simulation at transistor level, macro modeling techniques based on gate-level simulation have been proposed [Gupt97, Bogl97] and are utilized during synthesis and optimization. Because of the accuracy required for final verification, transistor level analysis that takes into account the interdependency of power consumption, signal delay and slope degradation is still required. 60 3.7.3. Analyzing power grid data: Due to the immense quantity of data generated during power grid analysis, data pruning has to be applied before reporting results. Application-dependent data filtering ensures that only critical sections of the design need to be investigated in detail. A visual plot is extremely useful for tracking down the elements of a design that are contributing to excessive IR-drop or electromigration problems. During static IR-drop analysis with Lt-sat data, the absolute value of the voltage on each node is not particularly meaningful. The important aspect to observe is the voltage distribution trends in the design. Frequently one or two areas of a design are found to be operating at much lower voltages than the rest of the chip. This indicates that the portion of the power grid supplying these areas may be insufficient and that more accurate analysis, such as activity-based static analysis, has to be performed on those portions of the design. Examining the current distribution in the power grid shows the source of the supply current for a block. Especially for blocks with IR problems, the expected source from visual inspection of the power grid and the real source differ significantly. Activity-based static analysis and full dynamic analysis produce meaningful data values that may be compared to design specifications for sign-off purposes. Any portions of the design that exhibit excessive voltage drop with activity-based current data should be carefully inspected to locate the cause. Changes should be made until this condition is corrected. 61 3.7.4. Electromigration analysis: Power grid electromigration analyses require the creation of models for a chip. Model data is provided for each metal and via layer in the chip [Cade03]. Each metal layer model provides the layer thickness; current density limits for peak, average, and RMS currents through wire segments (different foundries provide different rules) for simple threshold checks; and a set of model parameters for the mean time to failure (MTF) model. Different model parameters may be applied for narrow wires and wide wires, where an additional model parameter defines the boundary between narrow and wide wires. Each via and contact model provides the current limits for peak, average, and RMS currents through each via/contact for simple threshold checks, and a set of model parameters for the MTF model. An MTF model can be based on Black's equation or some other model. Where, Black's equation is given as: tJO--A·-:~rJ exp [ VH]kT (3.4) Where, t50 - Time to Failure vH- Activation Energy T- Temperature k- Temperature Constant Where t so is the median time to failure in an ensemble of samples, A is a constant that needs to be empirically determined and vH is the activation energy for failure [Cade03a]. The experimental values found for the activation energy suggested grain boundary diffusion as the mass transport mechanism. The actual MTF value for an individual component can be misleading, and because the MTF values of relatively 62 reliable components can vary over a very wide range, it is more useful to examine the inverse of the MTF. The inverse of the MTF is referred to as EM risk - the risk that the design will fail during the time of operation. During reliability analysis, the components with larger EM risk values are the ones most likely to fail. Detailed analysis for Electromigration reliability is made by calculating the theoretical time to failure and EM risk value for each element and using the proper failure statistics to obtain a failure probability as a function of time for the entire chip. The results are highly dependent on the choice of the statistical model used. Extreme value lognormal, also known as multilognormal statistics, is used, assuming the failure probability to be that of a chain that fails at the weakest link. The links are assumed to be lognormally distributed. Since the wire segments with highest EM risk are identified, these can be provided to the designer for an engineering change order (ECO) if the overall chip probability is below specification. Improving the reliability of the least reliable elements in the design will drastically increase the overall MTF of the design. 3.8. Power grid noise reduction techniques: 3.8.1. Circuit techniques: 3.8.1.a. Increasing Fall time (tr) or Rise time (ta): One of the most popular techniques for noise reduction is to make fall time (tr) and rise time (ta) process independent [Gubb87]. A larger tr or ta translates to lower noise. When designing a buffer for certain speed, worst case process, temperature and power supply variations are considered. By adding circuits that measure the actual chip performance, the buffer peak current, Ip can be regulated to achieve a maximum allowed tr. this 63 technique is called as slew rate control. Process compensation circuits are used to regulate the rise/fall time of the second-to-last stage buffer [Leun88]. This is done by feeding back the input or the output of the last stage buffer to control the drive capability of the second-to-last stage buffer. 3.8.1.b. Reducing switching voltage (Vsw): di/dt noise is also reduced by using lower signal swing. This reduces noise generation, but it also makes the receiver more sensitive to noise, unless differential signaling is used. Reduced swing also improves noise when using on-chip decoupling capacitance [Itoh87]. 3.8.1.c. Reducing switching capacitance (Csw): A lesser known noise reduction technique consist of active circuits for reducing the switching capacitance (Csw) [Tabo90]. For a standard 8-bit bus, all bits may switch simultaneously such that Csw = 8.Cpin· By adding some coding overhead, the maximum number of pin transitions between two consecutive bus transfers can be reduced [Chen96]. 3.8.2. Improved noise immunity: 3.8.2.a. Dynamic Logic: The sensitivity of dynamic logic can be significantly increased by providing weak feedback to dynamic nodes [Larr97]. This technique reduces the probability of logic failures due to erroneously charged/discharged high- impedance nodes caused by di/dt 64 noise, crosstalk. However, weak feedback does not prevent delay failures and is therefore not a general purpose solution to noise scaling. 3.8.2.b. Regulated supply: An alternative to separate supply is to use active circuit techniques to generate a stable on-chip Vdd, a so called regulated supply. However, the regulation circuitry fails if the unregulated supply is varying beyond a certain limit. Therefore, this method is only a viable solution if the noise levels on the unregulated supply can be kept constant with scaling by other noise management techniques. 3.8.2.c. Differential signaling: Proper design of differential circuits will make external noise appear as common mode noise. This will eliminate the issue of 1/0 reference levels and this is a suitable solution for off-chip communication. However failure may occur if noise makes the signals exceed the common mode range on the receiver. Another advantage of differential signaling is that it is often implemented with low-swing signals, such that noise generation is reduced. This makes differential signaling an attractive solution for off-chip drivers to handle scaling of noise [Rain94]. Another important use of differential signaling is on-chip communication between a digital and analog section that have separate power supplies. Digital control signals feeding an analog circuit must have a return path for the current that charges/discharges capacitive loads in the analog section. Fig 3.13 shows a single ended signal indicating that di/dt noise will be generated in the analog circuitry since the return path goes through an inductive bonding wire. This noise 65 will be eliminated if using differential signaling or if the analog and digital sections share a common V ss· Digital cin:uitry...... ,_...1 Analog cin:uitry I Vin - Input Voltage L- Inductance Vss- Ground Fig 3.13. Return Path Through Inductance Causes di/dt Noise 3.8.2.d. Transmitting Reference Level: A disadvantage of differential signaling is the doubling of interconnections, which is especially costly for I/0 interfaces. An alternative approach is to transmit a reference voltage level in parallel with a databus [Sidi97]. This improves the noise immunity of the receiver but does not reduce the noise generation of the transmitter. The receiver is built conceptually built with differential amplifiers, where one input is tied to the transmitted reference level and the other input is one bit of the databus. This will also make noise show up as common mode noise. Combining this scheme with a constant - weight code would give similar properties as differential signaling, but with a potential reduction in the number of I/0 pins. 3.8.2.e. Substrate referencing: A special case of reference level transmission is to use the substrate on a chip as the only reference level. If all internal signals, receivers and transmitters on a chip are referenced 66 to a single voltage, on - chip circuitry will not experience any problems with noise on either Vdd or Vss [Alls91]. This is achieved by each node having a strong capacitive coupling to the substrate and embedding high impedance current sources to V dd in the circuitry. This method can be combined with differential circuit techniques and regulated power supply. This method is usually limited to small analog - style circuits. 3.8.3. Power grid noise suppression: 3.8.3.a. Separate supply/guard rings: By having a separate Vdd (in a P-substrate/ N-well technology) for sensitive analog circuits, the product of inductance and switching capacitance (L * Csw) can be made small for the analog section by using more power supply pins for each unit of switched capacitance. Designers of analog/mixed- mode circuits often combine separate supply with guard rings in an attempt to shield sensitive analog circuits from switching noise generated by digital circuits. 3.8.3.b. Decoupling capacitance: By intentionally adding capacitance between Vdd and V55, the decoupling capacitance can be made much larger than the switched capacitance such that the noise is reduced. This technique is effective for switching of internal circuits [Hash92]. Assuming decoupling capacitance will scale as total chip capacitance, the ratio of switching voltage to peak noise voltage (VswNnMax) is given as: (3.5) 67 Where, Vsw- Switching Voltage Vnmax -Peak Noise Volatge cd- decoupling capacitance This indicates a promtsmg nmse management technique. Fig 3.14 shows on-chip capacitance and bonding wire inductance form an LC tank. Vdd - Input Voltage Vss- Ground Rvdd - Input Resistance Cd - Wire Capacitance Rd - Wire Resistance Fig 3.14. On-chip Capacitance and Bonding Wire Inductance form an LC Tank with Resonance Frequency ro and a Damping Factor ~ ro- Resonance Frequency (1/Sqrt (L *C)) ~-Damping Factor (R/2*Sqrt (C/L)) L- Inductance R-Resistance C- Capacitance 3.8.4. Reducing Electromigration problems: Electromigration failures can be reduced in several ways. The basic idea in all approaches is to reduce the average current density seen by any metal segment. The simplest approach is to widen the metal lines [Cade03]. However, increasing the width beyond a certain point leads to over-design, which costs area and can reduce yields. Another approach is to change the current flow in the power grid itself by adding jumpers and straps between different points in the grid. This would reroute current around the affected 68 areas, but such changes would require another verification pass to confirm that the problem has not simply been moved to another area of the design. 3.9. Substrate Noise Fundamentals 3.9.1. Parasitic Effect of Substrate The parasitic material of substrate influences the behavior of a circuit design. For example, the capacitance of the substrate delays signal transmissions to different locations of the device [Huij96]. The current flowing to the ground through the substrate leaves a voltage drop, which affects the device operation. In addition, the substrate is not a perfect isolation between devices, leading to unwanted "cross-talk" in integrated circuits. As illustrated in Fig.3 .15, a parasitic resistance inductance and capacitance (RLC) circuit on a capacitor is introduced when the substrate is connected with bonding wires. This affects integrated devices in the circuit. For instance, a typical bonding inductance of 4nH together with 1OpF capacitance has a resonant frequency of 800MHz, which is a source of instabilities and oscillations. 69 Diffusion (Substrate Contact) Substrate (a) (b) Fig 3.15. (a) Parasitic Effect on a Capacitor made of Two Polysilicon Layers (b) Equivalent RLCModel In the common silicon substrate, the phenomenon of the cross-talk occurs if a sensitive cell, like analog portions of the integrated circuits, is presented along this parasitic path. It is perturbed by the noisy signal, so that the substrate is used as a parasitic return path for signals carrying relevant information shown in Fig.3.16.a. Also, the cross-talk problem arises in any substrate coupled regions such as the collector of an npn transistor or a bonding pad changes state. Oxide Signal Source Substrate (a) 70 Cws - Wire to Substrate Capacitance Noise Source V(f) l f =' freq. of noise ...... P Substrate (b) Fig 3.16. (a) Substrate as a Parasitic Return Path (b) Substrate as a Parasitic Path to AC Ground Furthermore, the substrate can also drive AC noise to the ground when the least resistive path is followed and the noise flow is determined by the distribution of substrate contacts to AC ground. In Fig.3.16.b, the presence of a backside contact produces a vertical current. Besides this, there are lots of parasitic capacitances existing at every node in a circuit. Cws is the capacitance between the substrate and a well which can provide a channel for noise to go into the substrate. When the well contact is connected to a digital supply, noise on the supply may be coupled to the substrate through the junction capacitance Cws· Consequently, the substrate behaves as a noise vehicle and channel. 3.9.2. Substrate Noise Coupling Effects in Mixed-Signal Integrated Circuits As depicted in Fig.3.17, being capacitively coupled to the substrate through junction capacitances and interconnected bonding pad capacitances, the digital switching node 71 causes fluctuations in the underlying voltage. Thus, a substrate current pulse flows between the surrounding substrate contacts and the switching node [Verg98]. Vg -- Ground Voltage R - Resistance Vin - Input Voltage Cdigit_Sub- Substrate Capacitance in Digital Circuitry Fig 3.17: The Substrate Noise Coupling Problem Even worse, variations in the backgate potential voltage of sensitive transistors in the analog portion will happen if the fluctuations spread through the common substrate. The variations in the backgate voltage induce noise spikes in its drain current and voltage because of the junction capacitances and the body effect of the sensitive transistors in the analog portion. It can impair the performance of the integrated circuit, and even totally corrupt the functionality of the system. Recently, substrate noise has begun to plague fully digital circuits due to further advances in chip miniaturization and innovative circuit design. The effects of substrate noise may cause critical path delays, thus other paths 72 may become critical as a result of the increase in generalized delay. Localized delay degradation may cause clock skews and glitches. As a result, it is very important to develop some methodologies and modeling techniques for substrate noise coupling in both pre-layout and post-layout stages in order to determine the amount of coupling required between the sensitive nodes and noisy nodes. There are several current techniques to simplify on the physical equations and allow for efficient substrate coupling analysis when circuit simulators or other general-purpose simulators are used. 3.10. Modeling Techniques for Substrate Noise Coupling: 3.10.1. Finite Difference Mesh Method : The Finite Difference Mesh Method is the earliest technique developed for substrate noise coupling. It employs the discretization technique to assume the substrate as layers of uniformly a doped semi-conductor of varying doping density outside the diffusion regions [Verg98]. As illustrated in Fig.3.18.a, using a finite difference operator, nodes are defined across the entire substrate volume. The electric field vector between adjacent nodes is also approximated. Discretizing on the substrate volume results in a mesh circuit consisting of nodes interconnected by branches of capacitors and resistors in parallel, shown in Fig.3.18.b, the values of which are determined from process parameters - dielectric constant, sheet resistivity or doping density. 73 Nodej Nodej r...... wir···· .. ···· .. ···r I ~ :~ /······~! hij 1 J : ---~~~-t_ i ; ...... i Nod~··r··· .. l Cij ------X:::~:~~::::~:.·.·.· CJ ·················-... ---C!:L Gij (a) (b) Fig 3.18 (a) A Control Volume in the Box Integration technique (b) Capacitances and Resistances Around a Mesh Node in the Electrical Substrate Mesh Ignoring magnetic fields and using the identity Y' • (Y'xa) = 0, Maxwell's equations can be written as: an 1 Y'·J+Y'·- =0 where D = cE; and J = -E; and it gives, at p 1 a - (Y' ·E) + c-(Y' ·E) = 0 (3.6) p at V.-V. E .. = I 1 (3.7) y hij where p is the sheet resistivity, cis the dielectric constant, and E is the electric field intensity vector. In this stage, a simple box integration technique should be utilized to solve the above equation, since the substrate is spatially discretized. From Gauss' law, it gives V·E=k (3.8) 74 p' and k=- where p' is the charge density of the material. From the 8 divergence theorem, LEdS= LkdA (3.9) where Si is the surface area of the cube and Ai is the volume of the cube shown in Fig.3.18.a. The left hand side of the equation (3.9) can be approximated as fsi EdS ~ LEii. sij = LEii. wijdij = k ·A; (3.10) j j Modifying the equation (3.8) and (3.9), it provides (3.11) Substituting the equation (3.11) and (3.7) into (3.6), it results a a + C..(-V,--V.)] =0 (3.12) I[ aij cv;- vj) 1 j l)at' at where as modeled with RC circuit elements shown in Fig.3.18.b. The above result shows that the areas of contact and diffusion are represented as equipotential regions in the resulting three-dimensional RC mesh and treated as ports in the multiport network. For 3D substrate noise coupling simulations, a marcomodeling can be used, and an admittance parameter matrix Y(s) of a linear circuit should be formed as follows: 75 Y11 (s) y 12 (s) Y21(s) Y22(s) = (3.13) In order to solve the above matrix Y(s), Asymptotic Waveform Evaluation (AWE) should be utilized because A WE can use a few dominant zeros and poles to efficiently approximate the time domain response of large liner circuits. Each A WE approximation Yij(s) consists of a partial fraction expansion: ~ k..l yii(s) = LJ v. + dii (3.14) l=t s-Pii,I where dij is any direct coupling between the input and output, Pij is complex poles, kij is complex zeros, and q is the number of poles in the approximation. This macromodeling technique can be applied to simulate noise coupling in VLSI chip, instead of conventional device circuit simulators. This Finite Difference Mesh Method's solution accuracy depends highly on the resolution of discretization. In addition, it is necessary to use fine grids to accurately approximate the non-linearity of the electric field intensity. In such two cases, the size of the resulting finite difference mesh matrix, with an increasing number of ports and fine grids, becomes too large to solve. There are three suggested methods for RC model network reduction: • use a moment-matching method to reduce an RC mesh model, 76 • use a coarse grids to reduce the overall number of grids, • ignore substrate capacitances, and consider the substrate as a purely resistive mesh Even though the above methods may reduce RC matrix, the finite difference method generally has a huge sparse matrix because it consists of discretzing the entire substrate and applying different equations at each node, due to the usage of a purely numerical calculation technique. Consequently, the Finite Difference Mesh method can be utilized to determine reduced order substrate models. 3.10.2. Boundary Element Method Dr. R. Gharpurey and Dr. R. G. Meyer have developed the boundary element methods using the Green's function for efficient calculation of substrate macromodels in the last decade [Roac70, Ranj96]. The marcomodels can be included in circuit simulators such as Simulated Program with Integrated Circuit Emphasis (SPICE), in order to predict the effects of substrate noise coupling and to allow optimization of the layout to minimize these effects. For the electrostatic case, capacitance Cij between contacts i and j are defined as the ratio of the charge on contact j to the potential of contact i, or Cij = Qj I ¢ . By Stokes' Theorem, (3.15) 77 where E is the electric field in the medium and nis the unit outward normal vector to the surfaceS. Similarly, the resistance between contacts is defined as (3.16) where a is the medium conductivity. In both the capacitive and resistive cases, the potential satisfies the Laplace equation. Thus, they can be interchanged freely. Moreover, substrate susceptance is typically much smaller than the conductance below 50Hz. Therefore, it may be ignored and all substrate impedances may be considered as purely resistances. First of all, the Poisson's equation is used: (3.17) where ¢is the electrostatic potential. For the resistive substrate case, the above Poisson's 2 equation can be reduced to \1 ¢ = 0. Applying the Green's function to (3.17) gives the electrostatic potential at an observation point r, due to a unit current density injected at a source point, r', defined as ¢(r) = fv p(r')G(r,r')d 3r' (3.18) where Vis the chip's volume region, as well as G (r, r') is the Green's function satisfying the boundary conditions of the substrate. The electrostatic potential of a contact is calculated as the result of averaging all internal contact partitions. Based on (3 .18), the potential of the contact i can be obtained as 1 ¢· = -::----::------(3.19) 1 V. f f p.Gdv.dv. I Jv, Jvj ; ; I 78 where Vi and Vj are the volumes of contacts i and j respectively, and Pj 1s charge distribution on j. pj = Qj I Vj is chosen over j, and substitutes it into (3 .19), and it gives, - Qj 11 Gdv.dv. (3.20) or,"'· --VV v v. ; ' j j I } By considering (3 .20) for all combinations of contacts and the solution to (3 .18) for each contact pair, the following coefficient-of-potential matrix equation [P] can be generated: [ct>]= [P][Q] and [Q]= [c][ct>] (3.21) 1 where c = P- is called coefficient of induction matrix. For a contact i, the capacitance to ground Ci and all mutual capacitances Cij are defined as N C;=Lcii (3.22) j=l where, and N is the size of matrix c. Based on the above fundamental of the boundary's conditions, the electrostatic Green's function in a multi-layer substrate can be derived. Fig 3.19.a shows the geometry ofmulti-layer doping. When there are multiple substrate layers, each with a different conductivity, the Green's function can be applied to the layered-media boundary conditions since these Green's functions can include any effects due to possibly finite extent of the substrate and vertically-varying conductivity. Fig 3.19.b shows two equipotential contact coordinates on the surface of the substrate. 79 cjl constant b---.-. Z=O Z=-dN ~=0 (a) t:x a~, b1 a2, b1 Contact I (b) Fig 3.19 (a) Geometry of Multi-Layer Doping (b) Two Equipotential Contact Coordinates on the Surface of the Substrate As depicted in Fig.3 .19 .a, the substrate is formatted as a dielectric and is characterized by several layers of varying dielectric constants Ek, where k is the layer number in the substrate. Assume that the bottom of the substrate is in contact with an ideal ground- plane and the substrate is purely resistive and lossy-dielectric. 80 A typical substrate example with two surface contacts is shown in Fig.3.19.b, including the point charge q = (x, y, z = 0), and observation point p = (x', y', z' = 0), with dielectric permittivity EN. The Green's function involves an infinite series of sinusoidal functions oo oo m1lX m1lX' nny nny' G(r,r') = G0 IZ"z\,() + LLfmnCmn cos(-)cos(-)cos(-)cos(-) (3.23) m=On=O a a b b where fmn is given by !, = 1 fJN tanh(rmnd) + r N (3.24) mn ab YB N fJ N + r N tanh(rmnd) The values of the parameters Cmn in (3.23) based on different conditions Table 3.2 Values of the Parameters Cmn Based on Different Conditions Parameters Values Conditions Cmn 0 m=n=O Cmn 2 m = 0 or n = 0, but m '* n Cmn 4 m,n>O According to the above relationship, fJN and r N can be derived from the following equation: (3.25) 81 where ek = tanh(rmn X (d- dk)), ['k = 0, fJk = 1.0, and kE [1, N]. Form= n = 0 at the surface, it gives (3.26) where Consequently, all the parameters in (3.23) can be solved. From (3.23), a further expression can be derived for the average potential at contact i due to the charge on contact}: "'· = --Qj i i G(s .,s.)ds .ds., (3.27) 'rl s s S S. 1 I 1 I j j I J Using the relationship in (3.20), it gives 1 P .. =-=--r/J; i i G(s.,s.)ds.ds. (3.28) y Q s s S S. 1 I 1 I j j j I J where Si and Sj are the surface areas of the contact i and j respectively. Pij is the entry of matrix P. Substituting (3.22) and (3.26) into (3.28) and integrating, an explicit formula for Pij can be obtained: 82 where (a~, a2) and (b1, b2) are the x- andy-coordinate of contact i and (a3, ~) and (a3, ~) are the x- and y-coordinate of contact j shown on the Fig.3 .19. b. Modifying the second term of (3.28), it shows: ~~ a1z ±a34 biz ±b34 L....L....kmn cos(m1r ' ' )cos(m1r ' ' ) (3.30) m=On=O a b where Furthermore, the contact coordinates, (a~, az) and (b~, bz), can be substituted by the substrate dimensions with ratios of integers p, q, and (3 .30) becomes (3.31) When the substrate dimensions and the ratios of the contact coordinates are integral ratios, the two-dimensional discrete cosine transform (DCT) of a series kmn can be used to compute. The DCT can be calculated very efficiently by the use of the fast Fourier transform. In addition, the DCT needs to be derived only once for a given substrate structure since the value ofkmn is solely dependent on the properties of the substrate in z- direction. As a result, the calculation ofPij only requires a simple DCT, and only matrix P needs to be calculated and inverted [Nikn98]. The major advantage of the Boundary Element Method is that it is not dependent on discretization, which differs from the Finite Difference Mesh Method. This method dramatically reduces the size of the matrix to be solved, because it is limited by the fact 83 that the impedance matrix is inverted, and P is fully dense. Moreover, the speed of this technique is several times faster than techniques using a purely numerical approach, and the matrix P can be computed to high accuracy by choosing large P and Q, without a major penalty in set-up time. The Boundary Element Method can offer results that are within 10% of the actual answer, even though it is erroneous to assume that a port has a constant current density across it. 3.10.3. Preprocessing Analytical Method: The previous two substrate coupling techniques, the Finite Difference Mesh Method and Boundary Element Method can only be utilized after layout extraction and do not provide a priori insight to the designer. The following two methods, the Preprocessing Analytical Method, and Simple Resistive Method, can provide some insights to circuit designers in the early stage of design. In a pre-processing stage, pre-computed z parameters are used to develop a preprocessing analytical method for substrate noise coupling [Verg95]. This approach is then used in an extraction stage to find out point-to-point impedances. First of all, three assumptions are made. Current density across ports is uniform, ports are equipotential, and the effects of chip edge are ignored. As deprived in Fig.3.20.a, two square ports are on top of the substrate separated by a distance, d. Characterizing the electrical interaction, the matrix equation between two ports is given as follows: (3.32) 84 where Zii is the potential observed at point i when a unit current is injected into point i, while point j is floating due to zero current. Zjj is the potential at point j due to a unit current injected at point j. Zij = Zji is the potential at one point when a unit current is injected at the other. Zii and Zjj are constant because of ignoring the effects of the edges in the lateral plane. Zij is a function of only the distance d between the two points. As Zij is inversely proportional to d, it gives: zij(d)=k0 + d+ ;; + ...... + ;: Z;;=K1 (3.33) zj =K2 where the constants, K1, K2, ki. and the polynomial order, m can be determined by first precomputing the actual parameters using curve fitting techniques on data points obtained by a 3-D numerical simulator. P epitaxial layer P+ buried layer P substrate P+ channel stop implant (b) (a) Fig 3.20 (a) Two Points Substrate Impedance Ports Separated by Distance, d (b) Determining Resistive Coupling Between Ports Using Point-to-Point Impedance For multiple ports on the surface, large ports should be discretized into smaller ports, illustrated in Fig.3.20.a, due to the assumption ofuniform current density across the port. 85 Using the above preprocessing analytical model, an admittance and impedance matrix can be formed. The impedances for the ports I, II and III shown in Fig.3.20.b can be calculated as follows: -I Ytt Ytz Yt3 Yt4 Zu Z12 Z13 zt4 Yzt Yzz Yz3 Yz4 = Zzt Zzz Zz3 Zz4 (3.34) Y3t YJz Y33 Y34 Z31 Z32 Z33 Z34 Y4t Y42 Y43 Y44 Z41 z42 Z43 Z44 (3.35) The preprocessing analytical method is the simple substrate noise coupling technique that can be developed in preprocessing stage. It is used in the extraction process to evaluate point-to-point impedances rapidly. This approach requires to be computed only once for a given process because the resulting data can be stored in libraries and then used in the real-extraction of different integrated circuit again. On the other hand, only the ports that connect the substrate to the wells, contacts, or devices are necessarily discretized so that the resulting matrix in the network is much smaller. The computation of this approach is faster than the Finite Difference Mesh Method and Boundary Element Method. The trade-off of this approach is that the accuracy is relatively low. 3.10.4. Simple Resistive Macromodel Method: Recently, some journals have explored a similar idea of a scalable marcomodel for substrate noise coupling in heavily doped substrates [Sama02]. It is called the Simple Resistive Marcomodel method. Based on a physical understanding of the current flow 86 paths, this approach reqmres only four parameters which can be extracted from simulations or measurements. The Simple Resistive Macromodel method is a simple and accurate method, and can provide a clear picture about the substrate noise coupling to IC designers in the early stages of the design. Wl, W2: Width of Source and Drain Respectively GlA, GlB: Resistance to Ground at node A and B G2- Gate Resistance GlA Back plane = GND Fig.3.21: Marcomodel for the Substrate when the Back Plane is Ground According to current flow lines between a source point and a sensor point from a device simulator, a typical heavily doped substrate can be modeled as a resistive network as depicted in Fig.3.21. In this circuit, G2 (= 1/R2) is the cross coupling conductance, while G1A (= 1/RlA) and GlB (= 1/RlB) are conductances from the source and the sensor, respectively. From the experimental results, R2 decreases as the separations between the source and the sensor decreases; otherwise, R2 increases rapidly for larger separations. 87 R 1A and R18 are independent of the separation and remain constant. Note that the back plane is either grounded, connected to ground through an impedance, or left floating. In order to obtain a Y -parameter matrix for the equivalent circuit of the heavily doped substrate, an ac voltage is applied at one port and the currents are measured with other port connected to ground. Assume that sizes and shapes of the contacts are the same, then it gives: G2 = G1A = GIB. The following two-port Y-parameters for the substrate macromodel is shown: (3.36) In order to determine G1 and G2, a Z-parameter matrix is used, and it gives: (3.37) Let~= (Gl + 2G1G2) be the determinant of theY-parameter matrix. zn is a constant~ because it is the impedance of contact one to the substrate, with all other contacts flowing. Thus, the constant ~ can be extracted from simulations. This gives (3.38) Rearranging the above equation, (3.39) where G1 and G2 can be determined from simulators and measurements, and they are dependent of the separations between the source and sensors. Based on the linear 88 dependence on the semi-plot of G2, it provides a relationship between Gz and the separation x. (3.40) where a and ~ are constants determined from simulations and measured data. Consequently, there are only two contact points required to obtain relatively accurate results, so the accuracy of a and ~ can be improved with more data and a nonlinear least- square fit. The main shortcoming of this method is that it can only be used on the heavily doped substrate. Moreover, the operating frequency must be below 2-3GHz because the substrate can only be modeled as the equivalent circuit as illustrated in Fig.3.21. In general, the Simple Resistive Marcomodels Method is a simple technique and provide fairly accurate results. Significantly, it can provide good insights regarding the substrate noise coupling to IC designers in the early stages of the design. 3.10.5. Summary and Trade-off of Substrate Noise Coupling Technique: Different substrate coupling techniques are compared in terms of accuracy, computational complexity, simulation time, procedure stage, generality and assumption time. 89 Table 3.2. The summary and trade-off between advantages and limitations in different substrate noise coupling techniques Finite Good Hard Long Post- lightly and 1) substrate Difference 1)depends 1) large mesh 1) huge layout heavily consisting of Mesh highly on matrix size matrix extraction doped purely Method the sparse size substrate resistive resolution mesh of 2) ignoring discretizati the magnetic field Boundary Hard Quite Post- lightly and 1) constant Element 1) within 1) cumber- Long layout heavily current Method 10% of the some 1) matrix extraction doped density across (using actual mathematics size 1) substrate a port Green's answer 2) requiring relatively optimizes 2) normal function) 2) offers millions of smaller the layout field must be accurate floating point than Finite to zero at the verification multiplications Difference minimize top and edges of designs 2)DCT the of substrate up to can be substrate boundaries approximat used as an effect 3) substrate is ely 2000 efficient purely devices) solver. resistive and lossy- dielectric Preproces Relatively Simple Short Pre- lightly and 1) equi- sing low 1) computed processing heavily potential port Analytical only once for a doped 2) uniform Method given process substrate current density across ports 3) a homo- geneous substrate 4) ignoring the effects of the chip Simple Relative Simple Short Pre-layout heavily !)treated as a Resistive Good 1) only 3 1) can be doped resistive Macromo 1) parameters (a, utilized to substrate network dels improved [3, s) required guide the 2)for low Method by more from3 placement frequency input data different of 3)back plane simulations componen connected ts before to ground layout extraction 90 3.11. Substrate Noise Coupling Reduction Techniques: Brief descriptions of some design techniques and guidelines for noise-aware physical design, in order to reduce substrate noise coupling effects are provided. In order to minimize the coupling of substrate noise, three different aspects should be taken into account. I) the amount of noise generated in the digital circuitry, II) the sensitivity of the analog circuitry to noise, and Ill) the transfer of the noise from the digital portion of the chip into the analog section [CharOl]. By minimizing these three areas, the substrate noise can be reduced. There are four common methods to achieve the above three specifications. 3.11.1. Guard Ring: The guard ring is commonly utilized in the prevention of the substrate noise in the IC design [TakaOl]. The ring is a surface region heavily doped /Bands~ with the majority-carrier dopant and is intended to form a Faraday shield around any Digital Noise___ ..., Analog sensitive devices, which need to be protected Circuit from the substrate noise. A typical layout of guard bands is shown in Fig.3.22. The ~ Guard Ring structures of the guard ring are around the Fig. 3.22: Guard Bands Layout noisy and sensitive circuitry, and usually separate the digital circuits from the analog circuits. 91 3.11.2. NWELL Trench: NWELL trenches can be used in between the noisy and sensitive circuitry to block the substrate current flowing near the surface of the substrate. 3.11.3. Supply Bounce Reduction: A cross section of a package cavity with bond wires connecting the chip to the package traces is depicted in Fig.3.23. This inductance of the package and bond wires can lead to Package Trace supply bounce. The supply bounce can cause the voltage drop between the board supply and the chip so that the digital power and ground can be very noisy. There are two methods to PACKAGE minimize this bad effect: i) a separate power Fig.3.23: On-chip Supply Bounce Due and ground are used in the analog portion of to the Voltage Drop Across Bond-Wire Package Inductance the chip to isolate the more sensitive analog circuitry from the digital supply noise. ii) lower package parasitic inductance can be accomplished through multiple or shorter bond wire connections. This is a very effective solution, but it is expensive due to the extra package costs. 92 3.11.4. Floorplanning: When the space in the circuit is available, careful floorplanning can be used to reduce the effect of the substrate noise coupling. During floorplanning, Low amplitude Medium amplitude analogue circuits analogue circuits specific well-isolated areas can be allocated to noisy circuits as illustrated in Fig.3.24. It means that the High Amplitude analogue further the sensitive and noisy circuits are apart, the circuits Low speed less substrate noise coupling can affect the \ P+ Guard digital Rings circuits performance of the circuit. Minimum distance \ 111gn ~ speed digital requirements can be computed based on the overall circuits Digital Output Buffers noise spectral energy produced by such circuits and Fig.3.24: Good Floorplanning to the maximum levels of spurious energy tolerated by Reduce the Effect of the Substrate Noise Coupling sensitive circuits [Sing99]. As with design trade-off, modifying a design to obtain better noise rejection may have an associated cost due to extra die areas, more package pins, and more expensive packages. 3.12. Inductance noise fundamentals: Inductance effects in on-chip interconnect structures have become increasingly significant due to longer metal interconnects, reductions in wire resistance (as a result of copper interconnects and wider upper-layer metal lines) and higher frequency operation [BlaaOO]. These effects are particularly significant for global interconnect lines such as those in clock distribution networks, signal buses, and power grids for high-performance 93 microprocessors. On-chip inductance impacts these in terms of delay variations, degradation of signal integrity due to overshoots/oscillations, aggravation of signal crosstalk, and increased power grid noise. When a current is passed through a conductor it creates a magnetic field around that conductor [Deut97]. That magnetic field in tum resists any change in current flow in the conductor. The measure of this property is called inductance (Fig.3.25). Direction of Current Direction of Magnetic Field Fig 3.25. Selflnductance When the magnetic field influences the current flow on another signal, that effect is measured by mutual inductance (Fig.3.26). 94 Direction of Current Direction of Magnetic Field Fig 3.26. Mutual Inductance The impact of the inductance on the circuit performance is primarily dependent on the conductor geometry, which affects the resistance, and the frequency of operation. If the conductor is narrow as in today's DSM technologies, the resistance will be high in comparison to the inductance value. Then, the frequency at which inductance will show a significant effect will be very high, many giga-hertz in some cases. As the conductor width gets wider, the resistance drops rapidly and the frequency at which inductance shows a significant effect can be lowered to the operating frequencies of today' s high performance circuits. Self inductance can wreak havoc with delays and mutual inductance can cause noise, crosstalk and other signal integrity problems. Inductance effects have become more and more significant mainly because [Lin02]: • For performance considerations, some global signal and clock wires are routed with large widths and thicknesses at the top levels of the metal to minimize delays. This decreases the resistance of the wires, hence making the wire impedance due to inductance comparable to that due to resistance. 95 • As the clock frequency increases and the rise times decrease, electrical signals comprise more and more high frequency components, making the inductance effects more significant. • With the increase of chip size, it is fairly typical that many wires are long and run in parallel, which increases the inductive cross-talks between them. • With the push of performance, some low resistivity metals have been explored to replace AI in order to minimize wire RC delays. 3.13. Inductance analysis: The main difficulty in the extraction and simulation of on-chip inductance is the fact that inductance is a function of a closed current loop. Therefore, it is required that both the current through a signal net and the return currents be considered simultaneously instead of being analyzed in isolation. Most of the return currents flow through the power grid, but some can also flow in other signal nets or through the substrate. The current distribution in the entire circuit, including the grid, must be known in order to obtain a correct estimate of loop inductance. Two analysis methods have been proposed to handle this issue. They are Partial Equivalent Elements Circuit (PEEC) method, based on partial inductances and simplified loop inductance model. 96 3.13.1. Partial Equivalent Elements Circuit (PEEC) model: A typical circuit topology consists of two supply grids (power, ground) and signal lines laid out over multiple metal layers [GalaO 1]. The gates draw power from the lowest metal layer, while external power and ground are supplied via pads to the uppermost layer. Figure 3.27 shows the proposed partial inductance based circuit model for the study of on-chip inductance effects. The PEEC circuit model consists of • Resistance, partial self-inductance and grounded capacitance (RLC-p) model for each metal segment. • Mutual inductances between all pairs of parallel segments. • Coupling capacitance between all pairs of adjacent lines. • Via resistances between adjacent metal layers. • Resistance and decoupling capacitance (to model non-switching gates) • Time-varying current sources (to model switching gates) • Pad resistances and inductances. 97 V dd - Input Voltage Cdevice - Device Capacitance (a) (b) 98 (c) Fig 3.27 (a) Short Circuit Current (b) Charging Current From Capacitance to Ground (c) Currents in Driver-Reciever-Grid Topology Interconnect RLC: Each segment of the topology is modeled as an RLC-n circuit. The resistance is frequency independent and is computed as a function of geometry and sheet resistance. The ground and coupling capacitances for interconnect are computed using commercial extraction tools. The partial self and mutual inductances are computed using analytical formulae. 99 Device Decoupling Capacitance: During normal chip operation, approximately 10-20% of the gates switch while the remaining 80-90% remain static. The parasitic device capacitance of these non-switching gates results in a significant decoupling capacitance effect, which reduces IR-drop and changes current distribution by allowing current to jump from one grid to the other. This capacitance is estimated by using a statistical model that can be applied at both pre and post layout stages. The estimation is done via small signal analysis of representative circuit blocks. The capacitance values of one block can be easily translated to other circuit blocks based on the relative circuit sizes (total transistor widths) of the blocks. Current Sources: In addition to the signal of interest, other signals switch simultaneously. Those gates draw current from the power grid and inject it into the ground grid, causing voltage fluctuations and affecting current distribution. This effect is modeled by using time varying current sources connected at random locations on the lowest metal later. The current value changes with time during the simulation, to account for different parts of the chip switching at different times. Pad/Package Models: External power and ground are routed to a chip via package leads and pads. The parasitic inductances associated with the package must be modeled, since they affect on-chip behavior significantly. The package is modeled as a bar, including the pad and a via 100 between the pad and package. More detailed package models can also be accommodated in the PEEC model. Acceleration/S parsification: Since the PEEC model includes mutual inductances between every pair of conductors, the resulting circuit matrix is very dense. The simplest approach to sparsifying the inductance matrix is to discard all mutual coupling terms falling below a certain threshold. This translates to removing entries from the partial inductance matrix, thus making it sparse and faster to process. However, the resulting matrix can become non- positive definite, and the sparsified system becomes active and can generate energy. Since there is no guarantee on either the degree of sparsity or stability, truncation is not a feasible solution. This is in contrast to the capacitance matrix, which can be truncated without passivity problems. 2. Loop Inductance Approach: \id;l \ I ~,;m:l 'f~~~~~~-~~--~r----~--~ (a) 101 G.t"J "J G.. (b) (c) (d) Fig. 3.28 (a) Single Signal Net for Lumped RLC Model (b) Circuit Model for Lumped RLC (c) Single Signal Net for Distributed RLC Model (d) Circuit Model for Distributed RLC Fig.3.28. shows a typical signal net and its neighboring ground grid [Zhu03]. The loop 102 inductance model defines a port at the driver side of the signal line and shorts the receiver side (which actually sees a capacitive load) to the local ground, since inductance extraction is performed independent of capacitance. Typically, an extraction tool such as FastHenry [Kamo94] is used to obtain the impedance over a frequency range, as shown in Figure 3.28.a. A netlist is then constructed with the resistance and loop inductance of the signal and ground grid, at one frequency, as shown in Figure 3.28.b.All the interconnect and load capacitance is modeled as a lumped capacitance at the receiver end of the signal interconnect. A ladder circuit is constructed to model the frequency dependence of resistance and inductance. The loop impedance is extracted at two frequencies, and the parameters Ro ,Lo ,R1 and L1 used in the ladder circuit in Figure 3.28 are computed. The lumped RLC circuit representation can be improved by increasing the number of RLC-7t segments. After the interconnect model is constructed, driver and receiver gates are connected and the complete circuit can be simulated in SPICE. 3.14. Design issues and guidelines: Since inductance is directly related to interconnect length, short/ medium length wires show resistive behavior, while long and wide wires exhibit inductive behavior. Inductance increases with the area of the current loop, hence inductive effects are reduced by the use of closer power/ground return paths. Inductive coupling noise and crosstalk can be minimized by controlling the overlap of the magnetic fields for parallel wires. Below, we have listed a number of common design techniques for reducing inductance. 103 3.14.1. Shielding: Capacitive coupling can be reduced by increasing the spacing between two metal lines. On the other hand, loop inductance can be reduced by sandwiching a signal line between ground return lines or guard traces. This forces the high-frequency current return paths to be close to the signal line, thus minimizing inductance. Fig 3.29 shows the clock signal shielded by ground planes. I N D u c T L A N c E s GND SPACING Fig 3.29. Shielding 3.14.2. Twisted-bundle layout structures: A twisted-bundle layout structure is a recent approach proposed for minimizing inductive coupling noise [ZhonOO]. The chip is divided into several routing regions and the routing of nets is reordered in each of these regions. This is done to create complementary and opposite current loops in the twisted bundle layout structure, such that the magnetic fluxes arising from any signal net within a twisted group cancel each other in the current loop of a net of interest. Fig 3.30 shows a snapshot of a parallel bundle layout and twisted bundle layout. 104 0,1,2,3 -Interconnects PARALLEL BUNDLE 02 ...... ______... _ 3 ------TWISTED BUNDLE ~ -----.::~------Jt:~------::;~...... Fig 3.30. Twisted Bundle Layout 3.14.3. Staggered inverter patterns: By using patterns of staggered inverters, the coupling capacitance and inductance effects can be reduced. The length of the overlapping portion between adjacent wires is reduced, thus reducing the amount of capacitive and inductive coupling. Also, the signal polarities alternate with each inverter, and hence the impact of the coupling tend to cancel out. Fig 3.31 shows the snapshot of layout with and without staggered inverters. b NON-STAGGERED D ~ ~ Inverter \::::an STAGGERED ~ ~ ~ ~ t> Fig 3.31. Staggered Inverters 105 3.14.4. Inter-digitated wires Wider wires can be split into multiple thinner wires with shields in between [Mass98]. Such inter-digitizing reduces self-inductance, increases resistance and capacitance. However, it increases the amount of metallization used for the interconnect. Fig 3.32 shows the snapshot of conventional wiring and inter-digitated wiring. G-Ground CLOCK 10 ..... @] CLOCK @] CLOCK @] ...... 2 ~ s ,...... ;...... __,....___ s_...,..,...... l .... Fig 3.32. Inter-Digitated Wires 3.14.5. Shield insertion and net ordering Coupling noise can be reduced by simultaneously inserting shields and ordering nets, subject to constraints on area, and bounds on inductive and capacitive noise [HeOO]. This optimization problem was solved by algorithms based on greedy approaches or simulated annealing. 3.14.6. Dedicated ground planes Dedicated ground planes or meshes in the layers above and below the signal line can be used to reduce inductance. Although they do not significantly lower the inductive effect 106 at low frequencies, since resistance dominates and currents take wide return paths, at high frequencies, the ground planes provide excellent return paths for the signal current, thus reducing inductive behavior. I WITH GROUND PLANES GROUND N D u WITH SHIELDS c L v T t--+-...._JII"' A \.. N __ c GROUND E FREQUENCY Fig.3.33. Ground Planes 3.15: Table 3.3. Summary of Signal Integrity Effects, Analysis Models and Reduction Techniques 107 (tV (tV (Csw) (Csw) Time Time sw) sw) (V (V Fall Fall & & Ordering Ordering Level Level Rings Rings (it) (it) Voltage Voltage Capacitance Capacitance Net Net attems attems P P Planes Planes LayoutStructure LayoutStructure and and Time Time Reduction Reduction Signaling Signaling Wires Wires Shielding Shielding Reference Reference Capacitors Capacitors Skewing Skewing Rise Rise Sizing Sizing Ground Ground Inverter Inverter Supply Supply Switching Switching Switching Switching Logic Logic Tecludques Tecludques Supply/Guard Supply/Guard Bundle Bundle Trench Trench Cosine Cosine Insertion Insertion Rings Rings Supply Supply Insertion Insertion Ordering Ordering 1d 1d coupling coupling Power Power Intentional Intentional Buffer Buffer Routing Routing Reducing Raised Raised De De Guard Guard Dynamic Dynamic N-Wen N-Wen Regulated Regulated Dedicated Dedicated Shielding Shielding Reducing Reducing Separate Separate Increasing Increasing SupplyBounce SupplyBounce Staggered Staggered Inter-digitated Inter-digitated Shie Shie Wire Wire Floorplanning Floorplanning Transistor Transistor Transmitting Transmitting Twisted Twisted 1. 1. 1. 1. 1. 1. Reduction Reduction 1. 1. 7. 7. 4. 4. 6. 6. 5. 5. 4. 4. 2. 2. 3. 3. 3. 3. 2. 2. 7. 7. 6. 6. 4. 4. 5. 5. 8. 8. 2. 2. 2. 2. 3. 3. 4. 4. 6. 6. 5. 5. 3. 3. Method Method Elements Elements Model Model Mesh Mesh (PEEC) (PEEC) Analytical Analytical Method Method Model Model Model Model Element Element Analysis Analysis RC RC RC RC Resistive Resistive Method Method Models Models Electrornigration Electrornigration Equivalent Equivalent model model Analysis Analysis Difference Difference Inductance Inductance DevganModel DevganModel Lumped Lumped Preprocessing Preprocessing Dynamic Dynamic Simple Simple Loop Loop Partial Partial Signal Signal Circuit Circuit Static Static Boundary Boundary The The Two-Pi Two-Pi Macro Macro Analysis Analysis Method Method Method Method 1. 1. l.Finite l.Finite 1. 1. 1. 1. Analysis Analysis 2. 2. 3. 3. 3. 3. 4. 4. 2. 2. 2. 2. 3. 3. 2. 2. Wires Wires Delay Delay Margins Margins Path Path Noise Noise Degradation Degradation in in gradation gradation Delay Delay Glitch Glitch Neighboring Neighboring Degradation Degradation de de Glitches Glitches Glitches Glitches Critical Critical in in Skew Skew Circuits Circuits Crosstalk Crosstalk Crosstalk Crosstalk Reduction Reduction Open Open Shorts Shorts Causes Causes Clock Clock Causes Causes Timing Timing Timing Timing 1. 1. 1. 1. Effects Effects l.Causes l.Causes 1. 1. 2. 2. 2. 2. 3. 3. 4. 4. 2. 2. 2. 2. 3. 3. t t Noise Noise Noise Noise Noise Noise IIJleC IIJleC Grid Grid tance tance Integrity Integrity Crosstalk Crosstalk Issues Issues Drop Drop Interco Interco Substrate Substrate Electromigration Electromigration Indue Indue Power Power Signal Signal * * *IR *IR 00 00 0 0 - Chapter 4 Signal Integrity Management in Physical Design Flows 4.1. Introduction: Designers agree that they must address signal integrity when using a 0.13-micron process or below. But less clear is just how and where in the design flow signal integrity should be dealt with. Even though there are various Engineering Design Automation (EDA) tools that allow designers to improve design noise immunity, such as its ability to function and perform as expected, it is not always obvious where and when to deploy those tools [Mcca02]. All solutions to signal integrity problems involve design trade-offs in terms of design productivity, performance, power, cost, yield and reliability. In some cases a signal integrity solution is an overkill and results in unnecessary design iterations. In other cases, it is even more catastrophic: The solution misses a critical problem that requires an costly silicon re-spin to resolve. The key to designing successfully in 0.13 micron or below is to develop a comprehensive signal integrity methodology so that the correct trade-offs to manage signal integrity are made at each step of the design process. No single methodology is the correct approach for all designs. In determining the one to use, it is important to understand the choices 109 available and to tune methodologies based on design's market requirements. For example, in a graphics chip a signal integrity error that sometimes causes a few pixels to be displayed incorrectly may be tolerable, but a flaw in the arithmetic unit of a microprocessor would not be. Another important step in defining a signal integrity methodology involves selecting the noise sources that must be managed and those that can be safely ignored or designed out [Tunc02]. This is a function of design style, process technology, and clock frequency. However, before deciding to ignore certain noise sources, safeguards must be put in place to ensure that these assumptions are valid. For example, if charge-sharing noise (noise created by the redistribution of charge when a signal is not being actively driven) is not being considered, then the use of dynamic logic should be prohibited or severely limited. Creating design restrictions that minimize or eliminate certain noise sources before implementation will greatly enhance design productivity but it typically comes at the expense of performance and area [HallOl]. 4.2. Early Signal Integrity Design Planning: Though signal integrity problems arise due to the electrical interactions created by a chip's final physical design implementation, some design choices can be made in the early chip-planning phase that can help create noise-immune designs. Chips are typically created from a mixture of existing cores, macros, standard cells and newly designed blocks. For each pre-designed subcomponent, an out-of-context analysis can be performed to determine whether the component is potentially noise sensitive, a major noise source or both. Knowing this information up front can help determine the correct strategy for utilizing that component within the design. Early analysis can be performed 110 for all known blocks such as memories, standard cells and J!Os [Roet03]. If a block is a potential noise source, then various techniques can be used to minimize its impact on its neighboring circuitry, such as adding guard rings, spacing, shielding or selecting a different implementation of the same function. Special attention should be paid to key chip-level signals such as power buses, clocks, chip-level routes (especially buses) and even reset, enable and scan lines. Power buses have to be wide enough to minimize voltage drop but not so wide that they waste valuable chip area. It is very difficult to repair the power routing after the design is assembled, so early work using worst-case estimates of switching behavior and power consumption should be used to safeguard against excessive voltage drop. For this early analysis, an IR drop tolerance for the chip can be determined and used as a generic bound for all the remaining design implementation and analysis tasks. As the implementation of the design progresses this bound can be relaxed. Clocks are very sensitive to signal integrity, particularly crosstalk. Double clocking can occur when crosstalk causes a clock to cross its switching threshold more than once during a single transition. Only a small amount of crosstalk is required to create a double transition if the noise glitch occurs just as the clock's active edge is reaching its trip point. Double clocking can be particularly troublesome for counters, state machines and on-chip clock dividers, which rely on the fidelity of the clock signal. In addition, clocks can be major noise sources, as they are high-speed switching signals that traverse much of the chip. The simplest solution to these problems is to shield the clock so that it is neither a 111 crosstalk victim nor a crosstalk aggressor. The complete clock signal or critical portions of the clock can be shielded. In addition, the use of gated clocks where certain clocks and associated logic can be deactivated during certain chip operations will not only help reduce power but also help improve signal integrity by reducing unnecessary switching. • ldertifY Sl issues to be expliclly addressed iWld ______..., those to be designed aromd, based on dl-)"s m.-.tret requi"emelu • Decide how to manage Sl for critical global si~1als (Power, Clod(, Buses, etc.) • Take Sl into accomt when selecti1g IP blocks (cells, cores, memories, etc) • Select Sl prevention strategyfor each block • Perform full d1ip Sl analysis wlh special attention to crlical global signals • Repai" any remaini1g Sl viol Fig 4.1: Signal Integrity Management throughout IC Design Flow Reset, enable and scan lines are typically not given much design attention as they are not timing critical. However, for the same reason they will tend to be weakly driven long lines with many fast switching neighbors and, consequently, be likely crosstalk victims. If a significant crosstalk glitch occurs on the reset line, the likely outcome is an asynchronous reset and a functional design failure. Similarly, scan signals are also vulnerable to crosstalk. Major chip-level buses typically need special attention because 112 they tend to consist of multiple wires routed adjacent to each other on the same metal layer. A number of techniques can be used to manage signal integrity on buses, including the use of wide wire widths; wider spacing between wires; repeaters to break up wire lengths; different routing layers for adjacent wires; interleaving power and ground lines at regular intervals amongst the bus signals, or using specialized design knowledge to control the order in which the buses' bits are routed. For very high-speed buses, inductive coupling effects may need to be analyzed. This is very challenging, time consuming and costly. One alternative is to determine the design parameters under which inductive effects can be ignored and adjust the design accordingly. For example, inductance can be ignored on short wires (due to fast slew rates) and long wires (due to being resistance dominated) where the values for long and short can be calculated based on expected slew rates and process parameters. By enforcing all wires to be either short or long the need for inductance extraction and analysis can be eliminated. All the signal integrity methodology choices can be made early. They all involve tradeoffs in terms of area, performance and engineering schedule. They can be implemented through design methodology restrictions or by using tools that will enforce the decisions in a correct-by-construction fashion. 113 4.3. Signal integrity Management: Physical implementation for large designs is typically a two-step process. The first involves creating a full-chip physical prototype or floor plan; the second involves detailed block implementation [Bece02]. How much signal integrity prevention can be used in this early phase is a function of how close the initial plan or prototype correlates to the final physical implementation. If the prototype bears a close resemblance to the final routing, early analysis can pinpoint potential problems and save wasted iterations in the detailed block implementation. Most block implementation tools support options for reducing signal integrity during placement and routing. In the placement phase, for example, weakly driven nets can be identified and upsized to improve their noise immunity. Other prevention techniques are to restrict the routing length of adjacent signals to a certain distance, or to use switching times of signals so that adjacent signals do not switch simultaneously. Often, the design determines how effective these prevention heuristics are. For example, using switching times of signals will not be effective in designs that use many asynchronous clocks. Also becoming available are routers that analyze and correct for signal integrity problems as they route. As noise immunity is dominated mostly by interconnect effects, this is a logical place in the design flow to focus on signal integrity prevention. Block verification of signal integrity involves performing a detailed 3-D extraction and signal integrity analysis of final layout. This should be done on each block as it is completed so that repairs can be made prior to chip assembly. The output from block-level signal integrity 114 analysis should be a list of potential failures and a list of fixes to automate the repair of those failures. A signal integrity failure is very tool-dependent - a true failure is one that causes a problem in silicon. However, in order to safeguard against costly silicon failure, all signal integrity analysis tools take a pessimistic view. They will try to determine the worst possible combination of plausible noise events that could potentially happen on every net and will check the aggregate of these events against some predefined failure criteria. There is pessimism in both the noise calculation and the failure criteria. The worst-case noise combination may not occur because of the timing and logical relationships of signals and, furthermore, the failure criteria may be overly conservative. The important thing to remember is that signal integrity analysis tools will report false failures and some tools are a lot better than others at filtering these failures. If you do not have a tool to filter these false alarms, then there are two options: apply design resources to examine each failure in detail or blindly fix the false violations. The former is very design intensive while the later can cause so much chum to the design that the fix-and-repair process will never converge. The fixes that can be automated include inserting repeaters on victim wires or upsizing victim drivers to better defend against attacks. Other techniques include spacing wires, shielding wires, widening wires or rerouting wires. 4.4. Signal Integrity sign-off: Once the final chip is assembled and before tapeout, the design should go through final signal integrity sign-off to validate that the completed design would function and perform 115 as expected. Full-chip validation can be performed either hierarchically using abstract block-based signal integrity models, or it can be done flat. The later approach takes longer but accounts for the subtle interactions between chip-level routes and the overlying blocks. The former is faster, but it is harder to manage. The final signal integrity sign-off analysis should not only be thorough and accurate, but able to handle full-chip capacity with full-chip elements such as 1/0s, analog blocks, IP cores and memories, as well as standard cell elements. 4.5. Signal Integrity Aware Methodologies for Physical Design: 4.5.1. Early Functional and Delay Noise Analysis Methodology: Physical design methodology includes signal integrity management through nmse analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved [Bece03]. The methodology addresses both functional and delay noise problems in the design and is targeted for block, platform, and chip level physical design of Deep Sub-Micron (DSM) designs. crosstalk noise a critical design and verification challenge for large, high-performance DSM designs. Analysis and verification challenges are due to the tremendous amount of victim aggressor pairs in most designs, along with millions of distributed parasitic devices. While pessimistic assumptions result in an impractical number of false failures to deal with, detailed analysis of all coupled nets in the design is impossible. Several noise analysis techniques have been developed by employing electrical, logical and temporal isolation techniques to reduce the problem space into the significant and realizable cases. 116 Such methods also use reduced order modeling techniques to reduce the interconnect complexity and increase speed. It may first seem that fixing both functional and delay noise problems would take twice as much effort as fixing one of them. However, since the underlying causes for both problems are the same, Such as weak victim drivers, strong aggressors, large coupling, light loading, etc., there is a very high degree of correlation between occurrences of these two problems for the same net. Likewise, there is a strong correlation between the magnitude of functional noise glitch and the change in delay due to noise for a net. These correlations suggest that fixing one problem should often alleviate the other problem as well, if not completely eliminate. Though a small amount of noise may not be harmful functionally, the resulting, although small, delay variation can still contribute to large timing errors since net delays contribute cumulatively to path delays. The consequence is that a design that is free of functional noise can yet have timing issues due to noise and apparently the number of delay noise problems one has to tackle is much larger than the number of functional noise problems. However, note that much of the delay noise problems that remain after all the functional noise problems (and the accompanying delay noise problems) are fixed, come from fairly small delay noise violations accumulating to a significant quantity on critical and near critical paths. The positive side of this is that a significantly large number of small delay noise violations that are occurring on non-critical paths need not be tackled. This 117 observation suggests an effective Signal Integrity management strategy wherein the delay noise problems are addressed only after all the functional noise problems are addressed. At early design stages (before functional noise problems are addressed), a large number of nets will have noise and a significant number of them also will have large amounts of noise. Since nets are shared by many paths, a large number of delay violations (based on path delays) will be reported and it will not be easy to manage such a large number of violations. It is rather convenient to address the problems initially for the shorter list of violators in the functional noise category. Since fixing each net fixes also the delay noise on many paths, the number of delay noise violations will drastically decrease after the functional failures are corrected. The relative noise magnitudes from a functional noise analysis can be utilized to arrive at an efficient order of applying certain noise repair measures such as victim/aggressor driver sizing so that faster noise convergence is achieved. Ordering the repair measures based on a delay noise report is somewhat convoluted since the severity of noise violation is determined in part by the criticality of the path on which the net lies. Moreover, the glitch voltage metric, available from functional noise analysis, is more convenient to use in determining repair measures, rather than the delta delay metric available from a delay noise analysis. Functional failures are analyzed and repaired first at pre-route and post-route stages, and the delay noise analysis and repair are done only in the post-routing stage and after all the functional noise violations have been repaired. Noise analysis and repair is done in 3 118 phases: an early prevention phase, a post-route functional repair phase, and a post-route noise aware timing analysis and repair phase; the last two following detailed routing. Synthesized & Placed Design .--t I I Fig 4.2: SI Management Methodology from Block Level, Platform Level and Chip Level Flow Noise Prevention Methodology: It is desirable that some design resources be invested early in the design cycle to prevent potential noise problems. There are a number of design techniques which can be applied for this purpose. These techniques can be applied to all nets in a pre-emptive manner or to selected noise-prone nets. Early noise analysis may be used to identify such nets based on floorplan/ placement data and estimated routing. Our noise prevention methodology 119 adopts the following four techniques; the first three being related to physical design and the last to pre-route circuit optimization. • Limiting the distance neighboring wires can travel in parallel: This prevents long parallel runs which create large coupling to dominant aggressors. • Shielding: This technique is applied for structured routing topology, such as bus nets that are likely to experience noise problems from long parallel neighboring nets. Depending on the capability of routing tools, full or partial shielding is considered. • Routing with extra spacing: This technique is also applied for structured routing topology, such as bus nets. • Pre-route slew optimization: Slow slew rate at the receiVmg ends of a net indicates that the net is weakly driven and/or highly resistive, which makes the net susceptible to noise. With driver sizing or buffer (i.e. repeater) insertion, slew rate at the receiver inputs is improved. Although applying slew optimization globally results in stronger aggressor drivers, its benefit on overall noise due to the prevention ofunacceptablyweak victim drivers is greater. While the parallel wire length and slew optimization techniques are applied globally to all the nets, shielding and extra spacing are applied only to nets with structured routing 120 topology which are likely to experience noise problems. Determining specific settings for these techniques requires a few trials of routing and noise analysis since routing characteristics, such as mutability and congestion, vary from design to design. For example, limiting parallel wire length is an effective way to reduce overall noise level. When set too aggressive, however, it results in problems in meeting timing requirement and mutability by forcing wire routes to go through excessive turns and layer changes. Functional Noise Analysis: Typical designs may include more than millions of nets that need to be considered for noise. Since noise analysis needs to be done not only as design sign-off but following each noise avoidance/repair iteration, the tum-around time of noise analysis is of concern. In most practical settings, run time of no more than a few hours is expected for a design with about a million nets. To achieve such high speed during analysis, it is necessary to quickly filter out non-problematic nets which often constitute majority of the nets in the design. Such filtering is achieved through the use of a simplified analysis model, such as reduced-order interconnect model. At the same time, filtering is performed in a conservative manner to prevent missing real noise problems. It is shown that a well designed noise filter can screen out more than 80% of the nets. For the nets which are identified as potential noise violations during the filtering step, an accurate detailed noise analysis is performed. The challenge in repairing noise problems is, in so doing without causing problem for timing closure and physical design closure (mutability and design rules conformance). 121 This problem is compounded when the tool implementing a chosen noise repair action (e.g. buffer insertion, gate resizing, wide spacing, etc.) is not timing aware. That is when the repair tool does not have the required timing capability to determine the effect of noise repair on circuit timing. A loose integration between the noise repair tool and a Static Timing Analysis (STA) tool may partially offset this problem, but the run time of iterations would become prohibitively expensive. This is so because the changes in the circuit need to be communicated to the Static Timing Analysis (STA) tool and likewise the revised timing information to the repair tool. Failed Nets Fig 4.3: Post -route Functional Noise Repair The above constraints may limit the number of options easily usable for correcting a given set of noisy nets in a given design situation. Flexible methodology for functional noise repair is shown above in Fig. 4.3. Although the proposed methodology supports four repair methods, viz. driver sizing, buffer insertion, double spacing of nets, and shielding of nets; it does not enforce any particular order in which these options are to be 122 used or even using every one of them. The following guidelines dictate which of the available actions will be used in a given design situation: • Routing changes are to be preferred over sizing and buffering for fixing noise at the chip integration stage. This assumes that all blocks are timing-clean, and long global nets are already buffered in the previous timing optimization phase. • While both driver sizing and buffering can be used for block level noise fixing, driver sizing is not to be preferred at the chip level since the drivers reside in the blocks that are being integrated. However, gates in the sea-of-gates can be resized at the chip level, since they are legalized and routed at the chip level. 4.5.2. Custom Wire Load Model: This uses an iterative flow between gate-level synthesis and place-and-route. After place and-route, if the constraints are not met, the netlist is back-annotated with the actual wire load and re-synthesized [Keut98]. Signal integrity problems are usually handled at the detailed routing level. Place and route data are necessary to determine the timing. Extracting net capacitances after place and route and feeding them back to synthesis in an attempt to seed synthesis with more realistic capacitance estimations is not practical. This often results in a different netlist, thus a different placement and routing, thus different wire loads, thus a different timing. There is no guarantee that this iterative process will converge. Moreover, expecting the backend tools to fix problems that are recognized late in the flow is unrealistic, since the latitude for what can be done at that level is limited. This short-term solution breaks down at 0.18 pm technologies and below. 123 4.5.3. Design Small Blocks, Then Assemble Them: This is based on the idea that a statistical wire load model can still be used for small blocks of logic. The netlist is divided into blocks such that the intra-block interconnect delay can be neglected or roughly estimated, which enables synthesis to predict the overall delay. Then the blocks are assembled. There are several problems here. First, this requires time budgeting, and there is no scientific method to come up with an accurate budgeting that can be met both at the block level and at the chip level. This results in a sub-optimal or infeasible netlist. Second, assembly must respect the physical boundaries of the blocks, so that the intra-block delays are preserved. This constrains the placement so much that timing and/or congestion problems cannot be addressed easily. Third, it is virtually impossible to estimate the inter-block delays, since long interconnects depend on the relative placement of the blocks. Fourth, statistical wire load models may still fail to predict timing accurately, even for small blocks, due to routing congestion. If routes in the block are forced to meander in congested areas, the net capacitances increase substantially. Since congestion impacts wire load model predictability, the overall connectivity of the netlist must be considered, which is no longer a local block level property. 4.5.4. Constant Delay Synthesis: The delay through a logic stage (i.e., a gate and the net it drives) is expressed as a linear function of the gain, which is the ratio of the capacitance driven by the gate to its input pin capacitance. Fixing the delay consists of fixing the gain. A fixed delay (i.e., fixed gain) is assigned on every logical stage so that timing constraints are met. Then these 124 gams are preserved as the netlist is placed and routed. Constant delay synthesis is attractive because of its elegance and simplicity, which enables fast synthesis. RTL-to gate synthesis has been proven to be a good application of constant delay synthesis [Coud02]. However, this elegance is obtained at the cost of ignoring the reality of physical design aspects. Delay models must be input slope dependent and distinguish between rising and falling signals. Such a simple model cannot capture the propagation of a waveform in a net. The gains can be kept constant by adapting the net capacitances and the gate sizes within limited ranges. In practice, this means that the netlist must be changed to accommodate the placement/routing/timing constraints (e.g., re-buffering), which means that delays must be re-assigned. Constant delay synthesis assumes continuous sizing. Mapping the resulting solution onto a real discrete library can result in a sub-optimal netlist. Also constant delay synthesis assumes convex input pin capacitance, which is often not true for real-life libraries. This technology is often referred to as physical synthesis. 4.5.5. Placement Aware Synthesis: Gluing synthesis and placement together does not help if routing information is not sufficient, or if the interaction between synthesis and placement is not under control. For example, synthesis may locally increase the area to fix a timing problem, thus creating an overfilled area, to which placement will react by spreading gates around, which will create new timing problems. Making this flow converge is a major problem. Moreover, synthesis and placement working together is clearly not sufficient if it does not account for congestion and signal integrity issues, which require an understanding of routing and 125 physical aspects. In other words, this approach does not go far enough in the integration of the logical and physical domains. 4.6. Tool Driven Physical Design Flows (From Signal Integrity Perspective): 4.6.1. Cadence Design Systems: Fig. 4.4 shows the Cadence's complete RTL to GDSII design flow based on an underlying, integrated database technology and a unified user interface. Build Gates & Physically Knowledgeable Synthesis (PKS) allows Synthesis, Scan Insertion and Initial Static Timing Analysis (ST A). First Encounter provides hierarchical partitioning, floorplanning and global timing management. Silicon Ensemble provides detailed placement and route [Cade02a]. Celtic Crosstalk analysis engine provides early analysis of crosstalk effects. Fire & Ice QX allows three-dimensional RC extraction. Signal Storm, Voltage Storm and Clock Strom allows detailed croostalk, IR drop, power grid electromigration and clock mesh analysis. 126 Synthesis Scan Insertion Initial STA 1+----*1 Data Bases Signal Integrity JD RC Extraction Fig 4.4: Cadence RTL - GDSII Design Flow 4.6.2. Synopsys Inc: Synopsys Static Timing and Signal Integrity solution flow consists of Primetime, Primetime SI and Path Mill [Sequ02a]. Primetime and Primetime SI provide signoff solutions for gate level designs. Primetime provides Static Timing Analysis (STA), where as Primetime SI analyzes crosstalk delay, noise (glitch) and IR drop effects. Path Mill provides transistor level static timing analysis. Primetime SI and Primetime target 127 synthesis-based gate-level designs, while Path Mill targets transistor-level custom designs. Fig 4.5. Synopsys Timing and Signal Integrity Analysis Flow 4.6.3. Sequence Design Inc: Starting with top-level RTL code (Verilog or VHDL), Power Theatre accounts for both static and dynamic power consumption. Power Theatre can analyze peak and time varying power and can help identify power reduction opportunities (Sequ03c]. After Logic Synthesis, Power Theatre can be used to insert power gating logic and to plan and design the power grid. Physical Studio can then be used to perform low power clock tree 128 synthesis. After placement, Physical Studio can perform pre-route timing optimization, power distribution, and signal integrity optimization by adjusting the placement for avoidance of these problems. A common static timing analyzer (STA) uses timing windows and dynamic coupling compensation coefficients to model cross-talk delay, glitch, and IR drop effects [Moxo03]. After routing, Physical Studio can perform corrections for signal integrity problems, based on a set of 3D topology transformations. Finally, Power Theatre and the ShowTime timing analyzer can be used on the completed design to perform validation of power, timing, noise and reliability requirements. Decreasing Power, Heat RTL Power &Noise Optimization Logic Synthesis Power Gating Grid Design Detailed Routing IR Drop Analysis Thermal Analysis Verification Increasing level of Design VerifY Power, Detail Timing, Noise, Reliability Fig 4.6.Sequence NanoCool Design Flow 129 4.6.4. Monterey Design Systems: Monterey's flow includes IC Wizard, a hierarchical design planning tool; Sonar, a physical prototyping tool; and Dolphin, a complete physical design system [Mont02]. IC Wizard is employed to perform automatic timing driven block placement, shaping, and port placement based upon system-level constraints and connectivity using a gate level netlist along with any hard macros. IC Wizard includes a global router used for congestion driven port placement, routing channel sizing, feed-through insertion, and buffer insertion. The integrated extraction engine of IC Wizard provides interconnect wire RC values based on the results obtained from the global router. An integrated Timing Engine and Delay calculator is used to budget the system timing requirements into partitioned block constraints. Sonar is a physical prototyping tool that enables early exploration, optimization, and analysis of design timing, mutability, clock distribution, power distribution, and signal integrity. The Sonar tool shifts many of the detailed physical implementation tasks upstream, providing a physical prototype that is accurate enough to make design decisions without the extended runtimes necessary for a completed physical layout. Dolphin is a highly integrated physical design system that allows for the optimization of many different design parameters simultaneously. With modules for logic optimization, placement, signal routing, power routing, clock tree synthesis/routing, extraction, static timing analysis, signal integrity analysis and repair, Dolphin simultaneously optimizes the design to meet all the outstanding design constraints. 130 Placement Logic Optimization Rebuffering Clock Tree Synthesis Power & Clock Router Detailed Router RC Extractor Static Timing Fig 4.7. Monterey's "Global Design Technology" Flow 4.6.5. Magma Design Automation: Magma Design Automation hierarchical RTL to GDSII flow is based on a single unified in-memory data model [Magm03]. Blast RTL is Magma's gain-based synthesis tool, and can synthesize a design without estimating cell sizing or fixing the implementation; this is left to be done after global routing, when more accurate load data is known. Blast RTL maps to the best topology 131 required to implement the logic structure defined in the RTL. Blast Plan is used for hierarchical design planning and floorplanning, and can partition large designs into more manageable-sized blocks. Blast Fusion IS a complete netlist-to-GDSII chip implementation system that includes logic optimization, place and route, skew clock generation, floorplanning and power planning, RC extraction, and an incremental timing analyzer. Diamond SI is a verification system for sign-off verification of signal integrity problems such as crosstalk noise and delay, IR drop, and electromigration on signal nets and power rails. Diamond SI includes a 3D parasitic extraction engine as well as an embedded static timing analysis engine. Gain Bases Synthesis Partition Floorplan Time Budget Placement Scan Design Clock Design Fig 4.8. Magma's Hierarchical RTL to GDSII Flow 132 4.7. Summary: This chapter starts with a brief introduction of a need for signal integrity centric physical design methodology. A detailed early integrity design planning methodology is provided. Several industry wide accepted conventional physical design flows are discussed. Finally, several signal integrity design methodologies from EDA vendors such as Cadence Design Systems, Sequence Design, Synopsys Inc., etc. are provided. 133 Chapter 5 Tools for Signal Integrity 5.1. Introduction: The importance of effective electronic planning tools has increased as electronic products have become more complex and the competition among manufacturers has increased. There is, however, an inherent loose-tight constraint in creating such tools. On one hand, the tools should be easy to use, the simulation methods should be fast and comprehensive, and the results should be accurate and clear. On the other hand, the system should be flexible enough to cope with the messiness of reality. Most simulation tools available fail to address the actual needs of the professional designer. Typically, several simulation methods are needed to design an electronic device. Results from one simulation, in turn, become the input for the next. If various programs are used in design work, time-consuming manipulation of result data from one format to another may be needed. Designers are further burdened by learning to use each tool effectively. Clearly, a tool package with many simulation features makes life simpler. Another trend in contemporary electronic design is 'automation'. This involves 134 finding ways to allow the user to define complex design tasks with automatic optimization and parameter variations. Once this is possible, the user can at virtually no cost make thousands of circuit adjustments to find an optimal design. Signal Integrity analysis plays a vital role in designing efficient chips in deep sub-micron technology. Several tools help in achieving this. They analyze the designs and provide with timing reports, router control directives and ECO reports. This chapter provides an overview on signal integrity analyzers from five EDA companies. Ideas in this report are based on Industry reports from several EDA magazines and EDA seminars. 5.2. Sequence Design Inc. 5.2.1. Physical Studio: Physical Studio is the design closure tool from Sequence Design Inc. It predicts and corrects chip timing, signal integrity, power, and voltage drop issues concurrently, before and after routing [Sequ03d]. Physical Studio integrates into popular third-party routing tools to enable existing physical flows. Physical Studio has two modes of operation, pre-route and post-route optimization. In post-route mode, Physical Studio works on exact parasitics and on exact physical locations. An extraction tool can generate output file with parasitic information. The parasitics file (with coordinates) enables Physical Studio to calculate crosstalk -aware delay and noise and to make netlist and placement changes with minimal disturbance of one's layout. It can figure timing violation due to large coupling capacitance on a net which can be fixed by just putting a buffer in the middle of the net. Physical Studio 135 automatically places the buffer at an optimal location as it knows the wire segments associated with the capacitance. Finally an ECO router can be used to reconnect the segments and drop vias to the pins of the buffer. Crosstalk-based STAin Physical Studio: Conventional crosstalk timing analysis is based on the min-max time window concept. (For example, Primetime-SI, Mantle, Pearl, etc.) A min-max time window is the interval between the earliest and the latest possible arrival time of a signal within a clock cycle. If the min-max time windows of two signals overlap and there is a coupling capacitance between them, they are subjected to crosstalk. In contrast, Physical Studio supports multiple time windows within a clock cycle. For example, signal A may switch either very early or very late, and signal B may switch in the middle. Therefore, the min-max time windows of A and B do overlap, but the actual time windows do not. These high resolution time windows enable a more accurate crosstalk analysis. Non-overlapping signals are ruled out, and the aggressor alignment for overlapping signals is known with more certainty. On the other hand, any analysis based on min-max time windows must make a pessimistic assumption that the aggressor alignment is always worst. Another differentiator for Physical Studio STA is that it supports the Advanced Library Format (ALF). ALF allows us to put more accurate data into timing and SI libraries than other library formats, so that our STA results correlate much better with SPICE runs and internal delay calculator [Goer02]. 136 Pre-Route Timing and Signal Integrity Optimization: Traditional placement-based optimization uses boolean-based methods that focus only on the timing violators themselves, thereby generating massive downstream netlist changes. Physical Studio's placement-based optimization works concurrently with incremental timing, power, and signal integrity analysis as well as the actual placement. It hardens the edges around violators, performs a ''what-if' analysis to examine the down-stream change impact and regenerates new constraints until convergence. Timing optimization techniques include placement modification, gate resizing, buffer insertion and deletion, and routing directives. In addition, automatic logic restructuring is performed on select critical paths. Signal integrity optimization techniques hinge on identifying real culprit nets with cross-talk delay and glitch susceptibility from a very large set of victim aggressor pairs and immunizing them by taking preventive action. The example in figure 5.1 shows a driver cell at the top (indicated by a red circle) fanning out to 6 receivers on the same net. The critical path, before optimization, has a worst negative-slack of- 0.5 ns. After placement-based optimization by Physical Studio, the critical path has a positive slack of+ 0.3 ns. The combination of transformations used to reduce slack and prevent signal integrity effects are highlighted in green boxes. 137 Fig 5.1: Pre-route mode [Sequ03d] Post-Route Timing and Signal Integrity Optimization: Physical Studio also supports "along-the-route" correction for timing and signal integrity after detailed routing. At this stage, the full 3D coupling capacitance effects and loading of interconnect are known. Physical Studio uses Full Context algorithm for precise surgical corrections to all timing and signal integrity violations, while maintaining the topology of the final routing. This eliminates the need for further iteration. The full context post-route optimization methodology is fully integrated into the pre-route timing and signal integrity analysis engine. A powerful set of 3D topology-based transformations enables Physical Studio to identify "high-return" targets along the route. It then proceeds to fix the worst-negative-slack, total-negative-slack, hold time, and design rule violations as well as apply final corrections for cross-talk induced delay and glitch. 138 In Figure 5.2, the routed circuit in Fig 5.1 introduces an unexpected route on the critical path, causing a glitch error and additional cross-talk induced delay. As a result, the critical path has a worst-negative-slack of- 0.8 ns. With full visibility to the real 3D RCs and routes, Physical Studio performs a precise set of transformations (highlighted in green boxes) that reduces the critical path slack down to+ 0.2 ns and corrects the signal integrity violations, while maintaining the overall routing. Fig.5.2: Post-route Mode Strengths: • Physical Studio allows concurrent optimization for Timing, Signal Integrity and power • Physical Studio has built in 3-D extraction 139 • Accuracy of Physical Studio is good with .lib and excellent with Adavanced Library Format (ALF) • Physical Studio fits perfectly with third party tools Weaknesses: • Physical Studio requires and external router to complete Engineering Change Order (ECO). This shows a strong dependency between Physical Studio and external tools [Deep02] • Standard Description Format (SDF) extraction file misses some nets when parasitics are extracted on some complex designs • Physical Studio has problems with its placer. This allows dependency on an external placer [Data02] 5.3. Synopsys Inc. 5.3.1. Prime Time SI: Prime Time SI is the Signal Integrity analysis tool from Synopsys Inc. Primetime SI is a full-chip, gate-level signal integrity (SI) analysis and sign-off tool. It extends the capabilities of Synopsys's Static Timing Analyzer (STA) Prime Time to identify timing and noise (glitch) problems caused by crosstalk and IR drop. Prime Time SI performs simultaneous min and max analysis. Prime Time SI introduces a new approach termed as static crosstalk analysis. In static crosstalk analysis, static-timing analysis (STA) is fully integrated with crosstalk analysis. 140 This integrated approach delivers the performance and capacity needed for full-chip crosstalk analysis of multimillion-gate designs [Syno03]. Prime Time SI is integrated into the current Static Timing Analyzer (STA) Primetime and produces two reports analyzing the delta delay (noise induced crosstalk delay) and "bump" voltages on the victim nets. Features: • Data Setup: To enable static crosstalk analysis, Prime Time SI reqmres accurate layout-extracted parasitic data, that allows for integration with all parasitic extraction tools adhering to strict standards. Standard-cell libraries are also needed. For best results, the methodology should be compatible with an established sign-off-quality static-timing solution. It also accepts Synopsys Binary Parasitic Format (SBPF) • Intelligent Aggressor Filtering: Prime Time SI has an built in intelligent aggressor filtering, required to ensure that the coupled (aggressor) nets with no impact on timing can be excluded, allowing for the analysis of larger designs and improving overall runtime performance • Crosstalk Delay Calculation and STA: Since not all changes in signal timing (slow-downs or speed-ups) are indicative of crosstalk-induced timing violations, it is important to calculate the delays on nets using an iterative process. Through this process, the nets with truly crosstalk-induced violations will be discovered by Prime Time SI 141 • Generate timing reports: After the delays have been accurately computed, intuitive timing reports should be generated Primetime SI also offers an efficient binary RC interface and the powerful crosstalk aware Interface Logic Model (ILM) capabilities to further improve performance and capacity in bottom-up hierarchical flows [Dutt03]. Signal integrity effects are interdependent and need to be analyzed in the context of timing. Primetime SI includes an integrated delay calculation engine and Primetime static timing analysis to accurately model and compute timing deviation due to crosstalk and IR drop delay. Primetime SI also uses the comprehensive noise modeling information in Synopsys Binary Parasitic Format (SBPF) to perform accurate noise calculation, detection and propagation on large designs. Primetime SI provides a graphical analysis environment for debugging crosstalk delay, noise and IR drop problems. Primetime SI provides a signal integrity debug GUI that provides users the capability to closely examine details of each victim net and its corresponding aggressor nets. Interface Logic Models (ILM) preserve interface logic for a block. They remove the logic not associated with the block. Back annotation and constraint files for interface logic are generated along with the netlist [Land03]. They are accurate as the interface logic is not abstracted. Synopsys Binary Parasitic Format (SBPF) represents RC network for all nets in the design. 142 Update Timing Done Fig 5.3. Prime Time SI Crosstalk Analysis Flow [HoltOl] Strengths: • Prime Time SI has hierarchical signal integrity analysis capabilities using Interface Logic Models (ILM) • Prime Time SI is suitable for final verification • Easily adoptable into Prime Time flow Weaknesses: • Prime Time SI doesn't perform detailed IR drop analysis [Data02]. 143 • Traditional Standard Description Format (SDF) files won't be enough Because the delay of the net depends on the timing of the nets switching nearby, Standard Parasitic Extraction Format (SPEF) files are required [Syno03] • Prime time SI requires improvement in Graphical User Interface (GUI) to perform design debug 5.4. Cadence Design Systems 5.4.1. CeltiC: CeltiC is the signal integrity solution from cadence design systems. CeltiC analyzes a design to ensure that it correctly functions in the presence of noise. CeltiC analyzes a design to report the delay uncertainty on switching signals in the presence of noise. The delay uncertainty can be fed back into a static-timing tool to calculate worst case min or max path delays in the presence of noise. CeltiC analyzes all nets in a digital integrated circuit for noise effects [Cade02b]. There are five main components of crosstalk analysis in CeltiC: • Characterize the cell library for noise • Calculate crosstalk noise caused by interconnect coupling • Filter out false noise failures • Calculate crosstalk-induced delay and slew changes for Static Timing Analysis • Generate ECO repairs for optimization 144 CeltiC employs a static noise analysis technique. Each cell instance in the design is analyzed from primary inputs to primary outputs. This static noise analysis technique enables practical checking of crosstalk effects on a chip-wide basis. The analysis of cell instances is based on calculating the worst-case noise waveforms on each primary input and cell instance output node. The noise immunity of a cell instance is verified given the noise waveforms appearing at each cell instance input. CeltiC assumes all worst-case crosstalk scenarios are possible unless prohibited by logic or timing constraints. CeltiC accepts logic constraints (relationships between signals) and timing constraints (timing windows during which signals can switch) as inputs. CeltiC performs a static noise-on delay analysis to compute both min and max delay changes. These delay changes can speed up or slow down signals leading to either hold violations on the early paths or setup violations on the late paths. The delay uncertainty analysis performed by CeltiC is dependent on the arrival times and slew rates of signals it gets from the Static Timing Analyzer (STA). The integration of CTE (Common Timing Engine) allows CeltiC to obtain the arrival time and slew rate information internally and eliminates the need to go to an external STA. To obtain a correct analysis of a circuit's timing behavior, noise on delay effects must be incorporated into STA's timing analysis. To solve this mutual dependency, iterations are needed between crosstalk and timing analysis engines. In addition, CeltiC uses timing windows (arrival times) from STA to disallow specific simultaneous switching scenarios between victim and aggressor nets. The aggressor timing adjustments are checked against their respective timing windows and the victim's timing window for timing orthogonality. Each overlapping aggressor subset determined from this mechanism is further filtered by logic constraints. CeltiC automatically 145 recognizes and propagates constants, inverters and buffers through the entire circuit CeltiC lumps the delay uncertainty caused by coupling noise into the interconnect delay. CeltiC derives its accuracy from: • Internal Spice-like simulation engine that handles fully distributed parasitics or reduced parasitics model, as well as transistor models • Aggressor slew degradation is implicitly considered by including the aggressor distributed network in the simulation • Non-linear driver is modeled directly by the transistor level netlist of the driving gate • Peak alignment of aggressor induced noise effect to ensure conservative analysis result • Timing orthogonality checks considering timing windows of aggressors and victims, and the delay adjustment between aggressor and victim for peak alignment 146 CeltiC Data Flow: Optional Optional Noise Library Netlist Run Script TWF UDNIECHO IRDrop File Repair Noise Report Delay Report ECHOs Commands Optional Fig 5.4. Celtic Data Flow CeltiC Inputs: • Noise Library: The makecdB utility analyzes the transistor-level netlist of a cell for noise effects as seen from its input and output ports. It encapsulates the essential information inside a cell for noise analysis. Resistances, capacitances, and noise tolerance characteristics for each cell are taken into account. The resultant cell library (. cdB file) generated by the mak:ecdB utility contains a cell-level view and a transistor-level view. 147 • Netlist: A circuit netlist in SPEF, Verilog, or Detailed Standard Parasitic Format (DSPF). CeltiC reads the DSPF instance section and the parasitics (Rs and Cs) to build the netlist. • Run Script: A run script, which is a series of CeltiC or Tel commands, typically in a file or a series of files. • Timing Window File (TWF): The timing window file contains timing windows and slew information. Timing Window File can be generated using CeltiC's common timing engine (CTE) or from a static timing analysis tool, such as Physically Knowledgeable Synthesis (PKS), Pearl, or Primetime. Optional Inputs: • User Defined Noise (UDN) (Optional): CeltiC optionally allows user-defined noise (UDN) input models, used to model incomplete blocks or analog circuitry. • IR Drop File: The IR drop data file can be generated by Voltage Storm. 148 Celtic Outputs: • Noise Report: The primary output from CeltiC is a noise report, which is a collection of files in HTML noise format detailing the noise found on every node. This report can be sorted by peak noise, sensitivity or delay uncertainty. • Delay Report: Similar to the nmse report only that it reports on delay uncertainty information. • Repair Commands: The ECO output file contains place-and-route commands to fix noise and delay violations. Supported place-and-route tools are Silicon Ensemble (SE), Physically Knowledgeable Synthesis (PKS), First Encounter (FE) and NanoRoute, Appollo. • ECHOs: An abstract noise model of a block that you can automatically create. ECHO abstraction may be employed for a block in which extracted parasitic netlist view data is available. • Slew Changes: CeltiC can generate noisy slew information directly as Primetime Tel commands. This file can then be read into Primetime to account for slew changes due to noise. 149 Optional Output: • Standard Description Format (SDF): CeltiC can output an incremental SDF that contains negative and positive incremental interconnect delays for minimum and maximum timing-path analyses, respectively [Cade02c]. Strengths: • CeltiC Crosstalk Analyzer accurately models the impact of noise on delay and slew for feedback to static timing analysis • CeltiC automates noise library creation for cells, memories, I!Os, and custom macros [Deep02] • CeltiC Integrates easily into any cell- based design flow 5.4.2. Voltage Storm: Voltage Storm is the power integrity solution from Cadence design Systems. It utilizes power grid views and enables hierarchical power integrity verification of large designs. Voltage Storm can be used at any stage of the physical design and verification process including Floorplanning, Cell and block design, Post-placement, pre-signal route, Full chip power integrity sign-off Voltage Storm also outputs many graphical plots to help debug any power integrity issues. While the main outputs are IR drop and current density, Voltage Storm also shows how the power is distributed throughout the design and how the current flows through the power networks. This information is critical in understanding the causes and potential fixes of these power integrity issues. Figure 5.5. 150 below shows typical IR drop output showing concentric rings of increasing voltage drop towards the center of the chip. Fig 5.5. IR Drop Analysis [Wilt02] During the early floorplanning stage, block implementation details are typically unknown, so Voltage Storm uses floorplan power grid views that represent the planned block power network. Since most designs include custom cells or hard IP blocks, power grids of these elements are verified at the transistor level before instantiating them in the design. Catching cell- and block-level issues including de-coupling capacitance and power consumption problems early in a hierarchical methodology save tremendous time and effort. Power integrity analysis can be particularly valuable after cell placement, but 151 prior to detailed signal routing. Using Voltage Storm to verify the integrity of power grid before signal routing allows to eliminate needless over-design, gain flexibility for signal routing, and optimize your power networks. IR drop impact on design timing can be observed and accounted for by outputting instance-based IR drop data from Voltage Storm to CeltiC, or third delay calculation and timing verification solution. This is a vital addition, since IR drop can have a significant impact on setup times, hold times, and clock skew. Voltage Storm allows various levels of abstraction. As the design becomes more complete, power grid views also become more detailed and complex. Final full-chip power integrity verification should be completed only using the most accurate power grid views. Voltage Storm can mix and match interconnect layers from DEF and GDSII input. For example, if you are designing a flip-chip, and your redistribution layer (RDL) contains 45 degree routes, Voltage Storm can accurately combine the design data and RDL layer to enable complete power integrity verification. Finally, just prior to tapeout, it is possible that you only have the complete design available in GDSII data, due to last minute custom edits. Voltage Storm can also do a final, full-chip, transistor-level verification, using the hierarchical GDSII data and existing power grid views. The best feature of Voltage Storm is, it contains PowerMeter for accurate power consumption analysis. PowerMeter statistically propagate node activity throughout a design and provide vectorless power consumption. Because it does not rely on vectors, PowerMeter is scalable as design sizes grow and is efficient for use at both the pre- and post-detailed routing stages of a design. Gates and memories are automatically recognizable and use clock domain information to generate the power distribution of a 152 design, with dynamic accuracy. PowerMeter calculates and reports three types of power consumption data: switching power, internal power and state-dependent leakage. It has been designed to accommodate custom IP blocks and multiple clock domains [VoSt02]. The graphical interface displays the distribution of power though a design and enables the user to specify power consumption for specific blocks or regions of the design. While most competitive solutions focus on power analysis for ASIC design styles, Voltage Storm provides a comprehensive solution that includes power integrity verification for all design types, including custom digital designs, IP, and analog blocks. For custom digital blocks, Voltage Storm provides a multimillion-transistor solution that reads GDSII input data and can be used to perform static, activity-based, or true dynamic power integrity verification. Voltage Storm transistor-level analysis extracts the power interconnect down to the transistors of the design, then performs power integrity verification using your transistor models to calculate the current loading on the power networks. Static and activity-based analyses enable high capacity and fast runtimes, but this analysis depends on an assumption of sufficient de-coupling capacitance. Dynamic analysis must be used to validate that the right amount of de-coupling capacitance is added to smooth out the power transients. Unlike some competing solutions, Voltage Storm checks for both IR drop and power net electromigration (EM) in a single pass. Voltage Storm validates current density in the power networks against foundry-supplied limits. A key prerequisite of accurate EM verification is accurate parasitic extraction of the power networks. The embedded extraction within Voltage Storm uses the proven parasitic modeling using parasitic 153 extractors , which includes all of the process manufacturing effects necessary to support copper processes at and below 130 nm [Cade03c]. Voltage Storm includes Black's equation, which enables to verify the projected lifetime of the design. 5.4.3. SeismiC: SeismiC is a substrate no1se analyzer for mixed-signal ICs from Cadence Design Systems. It identifies the significant noise contributors that affect key analog devices and allows designers to focus on reducing the contributions of these major noise sources. Noise can propagate to both the digital and analog portions of the design. While digital circuits can usually defend themselves against substrate noise, their analog counterparts are very sensitive and can easily malfunction. Noise caused by substrate coupling is a key reason for inexplicable design failures and poor yields of mixed-signal designs. SeismiC uses a unique adaptive modeling technique that permits substrate noise analysis of large designs [Cade03d]. SeismiC automatically refines its calculations based on the sensitivity of each transistor to noise, focusing highly-detailed analysis only on key sensitive areas. The tool then calculates the substrate noise levels at every transistor, the noise contributions from major contributors and displays the results directly on the layout. SeismiC examines the effectiveness of design, layout, process, or package changes on reducing noise. For key analog devices, SeismiC calculates the sensitivity of noise to different changes and helps in selecting the correct noise avoidance strategy. 154 SeismiC Data Flow: Process Layout Netlist Package Technology (GDSII) (SPICE) Simulator Noise Sensitivity Noise Waveforms Noise Layout Rer>ort (SPICE) Display Fig 5.6. SeismiC Data Flow SeismiC, which is integrated into the Cadence analog design environment, uses the following input [Cade03e]: • Technology file that describes the substrate process variables • Netlist that contains package parasitics, including bond-wire and package pin inductances SeismiC also works in other existing design flows, where SeismiC uses the following inputs: • GDSII stream file • Corresponding netlist for the entire chip • Technology file that describes the substrate process variable 155 • Signal toggle file from standard logic circuit or timing simulation tools • Netlist that contains package parasitics, including bond-wire and package pin inductances. If the package parasitics are not provided, SeismiC assumes default values for the package and pin inductance SeismiC produces the following output: • Waveforms and spectral components of substrate noise at sensitive analog components in the design The significant contributors to noise at these sensitive components and their contribution levels are highlighted on the layout display • List of recommended design changes to reduce noise at sensitive components • Highlights on the layout display that represent equipotential noise contours across the chip surface caused by switching noise sources Strengths: • Full-chip substrate modeling for a variety of processes, including BiCMOS, twin well, triple well, SiGe, and standard CMOS • Noise-sensitivity analysis to determine major nmse contributors attacking sensitive analog components • Visual display of noise voltage waveforms at the substrate of noise-sensitive components • Generation of circuit models to represent substrate noise or spectral components of substrate noise for sensitive devices for use in circuit simulations 156 • Visual display of noise contours on the layout that shows noise distribution across the chip surface caused by switching noise sources • Comprehensive reports to advice and aid the designer on the impact of design, layout, process, and package changes to reduce substrate noise 5.5. Monterey Design Systems: 5.5.1. Dolphin: Dolphin is the Signal Integrity Analyzer from Monterey design. Instrumental to Monterey's cross-talk solution is Dolphin's integrated and incremental static timing analyzer that understands crosstalk based on an accurate built-in cross-coupling RC extractor. Dolphin generates the switching timing window and slew for each net which are used to assess the crosstalk interaction between signals. Dolphin has two key enablers that allow the construction of an effective SI solution [Mont02a]. First is the concept of Global Design Technology™ which is the set of patented and highly innovative algorithms that simultaneously explores, analyzes and optimizes all aspects of design implementation. Second is the process of Continuous Model Refinement™, where the placement, routing, timing, congestion, and other key design parameters are continuously refined from the start of physical implementation until the completion of the design. The Dolphin system provides solutions to electromigration issues during the automatic layout process by calculating the required width of the interconnect wires as they are placed and routed. The current through each interconnect per transition is captured with the waveform calculator within Dolphin. Using the correct capacitance loading of the nets provides an accurate measurement of the current flow. The average or Root Mean Square 157 (RMS) current through interconnects can then be used to perform electromigration analysis. For IR drop analysis, the currents in the cells within a bin or region are accumulated and represented as a current source to the power grid. A fast IR drop analyzer within Dolphin is used to evaluate the IR drop so that the power structure can be automatically or interactively adjusted. Static Timing Analysis Using Physical Information: Dolphin physical synthesis uses a progressive refinement algorithm, in which all steps (placement, routing, and logic optimization) are performed simultaneously at increasingly finer levels of detail. Depending on the level of accuracy, Dolphin analysis can be used to investigate timing, power, and mutability at any stage in the implementation process [Mont03]. Problems discovered during analysis can be corrected without leaving Dolphin. Then Dolphin incremental analysis can be used to verify your changes. Power Routing and Clock Tree Synthesis: For greater accuracy, power rails should be routed before physical synthesis usmg Dolphin. Dolphin's power router can be used for routing. Because of the impact routing congestion has on timing, Dolphin requires the power routing so it can model congestion accurately. Congestion impacts timing because wires in congested regions will be longer than their minimum manhattan distance and typically have higher parasitic loads than wires in lightly congested areas. 158 Congestion Analysis: Dolphin analyzes routing congestion and interactively resolves any congestion problems. Congestion problems must be analyzed before proceeding to detailed routing. Overly congested designs may be impossible to route cleanly (without design rule violations) and can take longer than necessary to complete. It also has built-in congestion avoidance, which will eliminate most problems automatically. Voltage Drop: Dolphin's voltage drop calculations are based on circuit activity information. Dolphin considers power consumption from static leakage power, dynamic switching power, and short circuit power. Dolphin features, voltage drop analysis is performed incrementally so that you can reanalyze designs very quickly after making changes. Physical Synthesis: Dolphin physical synthesis uses the Monterey Progressive Multi-objective Refinement algorithm, in which all steps (placement, routing, and logic optimization) are performed simultaneously at increasingly finer levels of detail. These physical synthesis capabilities include full logic restructuring, technology remapping, logic collapse and cloning, and pin reordering along with basic optimization functions, such as buffering and sizing. Dolphin provides total design closure. The Dolphin physical synthesis algorithm simultaneously improves timing; reduces area, utilization, and congestion; reduces power consumption; and minimizes leakage current. 159 Routing: The Dolphin router is flexible, fast, and powerful. It uses a shape based algorithm to enable efficient gridless connections, handle routes with variable width and spacing, and provide for the shortest overall wire length with the minimum number of vias. Crosstalk A voidance: Crosstalk has a significant effect on timing. For increased accuracy, the Dolphin Static Timing Analysis (STA) engine includes the effects of crosstalk during analysis. To address crosstalk problems, Dolphin provides both crosstalk avoidance and repair. Dolphin avoids crosstalk problems by providing extra space between interfering signals during routing. To repair any crosstalk problems that remain, Dolphin resizes existing buffers and even adds new buffers if required. Electro migration: Dolphin also provides electromigration avoidance. Dolphin calculates current density automatically using built-in analysis and selectively widens wires and adds via arrays to avoid electromigration. It interactively analyzes and repairs electromigration rule violations and prevents them automatically. Dolphin will avoid electromigration violations on every signal net in the design, as well as the clock and power nets. Strengths: • Dolphin is easy to use, and due to its TCL interface, it's easily customized 160 • Dolphin's clock-tree-synthesis engine is efficient when compared to other tools. Dolphin provides a very good interface to path tracing, and creates "critical-path schematic" which allows cross-probing into layout • Dolphin read standard formats (LEF, DEF, SDC constraints etc.). It supports the concept of "checkpointing", which allows to "snap-shot" a solution at any given point in design. All the necessary files (netlist, floorplan, constraints etc.) are encrypted and put in a separate directory for a given checkpoint Weaknesses: • The Dolphin router is relatively slow • Dolphin's GUI has troubles selecting dense/overlapped geometries while clicking • Dolphin's abstract generator (LEF generation) creates extra pins for some shapes near the boundaries during block abstraction [Data02] • Dolphin consumes more memory when compared to other signal integrity analyzers. Extra features such as terminal maps for IR Drop are not precise enough 5.6. Magma Design Automation: 5.6.1. Blast Noise: Blast Noise is a crosstalk analyzer from magma Design Automation. It analyzes and adjust a chip design to avoid crosstalk noise, crosstalk delay and electromigration (EM) problems. Blast Noise signal integrity analysis engine uses Fixed Timing Methodology® 161 to analyze and adjust the design to eliminate these problems while at he same time maintaining optimal timing. Magma flow is built on a single unified data model. This means all the tools in the RTL GDSII flow share a common data structure. All the tools directly run on that. All the design data lives "in core" during the flow, attached to the data structure. This data model is resident in the memory and contains all design data, enabling the signal integrity analysis engines to get immediate access to continuously updated logical, physical, timing and other design information [Blno02]. This enables Blast Noise to address signal integrity problems automatically and without iterations. Blast Noise automatically selects the best available metrics at every point in the flow to achieve the required accuracy at that point. This incremental approach uses predictive models early in the design flow to achieve fast, yet conservative, estimates. Later, when more accurate parasitic and delay information becomes available, the flow uses more precise models for analysis. These adaptive, design flow-dependent models are used extensively to represent cross-coupling capacitances. The flow also uses unique filtering algorithms to eliminate false errors. The result is an efficient and consistent flow that achieves rapid convergence on the analysis and correction. 162 Analysis and Adjustment: Crosstalk noise and delay problems are modeled using the highly accurate, 2Pi model. Accumulation models are used to account for multiple aggressors on a given net. The flow uses intelligent filtering that looks at both DC and AC noise margins to filter out potential false errors. It computes the Miller capacitances based on either a static model or a slew-based dynamic model. The Miller-adjusted cross-coupling capacitances are then applied to static timing analysis to account for crosstalk delay . ..r Aggressor net Fig 5.7: Magma Crosstalk Analysis, Two Pi- RC Modeling Blast Noise automatically adjusts the design to eliminate the crosstalk problems. This is achieved by reordering the track routes based on overlapping victim and aggressor net timing windows. Wide space routing and shielding is also used to eliminate this problem. Blast Noise addresses the signal electromigration problems by computing the average, Root Mean Square (RMS) and peak currents for each layer and via based on the current 163 capabilities on the driver cell. It then uses the current density limits to automatically compute and enforce the new wire widths required to handle the computed currents. Techniques such as via doubling are used to reduce via resistivity. -- Cload Fig 5.8. Magma's Signal Electromigration (EM) Analysis Strengths: • Crosstalk and delay problems are modeled using 2-Pi analysis model • It has the capability of automatically adjusting the design to eliminate the crosstalk problems • Dolphin addresses signal electromigration problems by computing the average, root mean square and peak current for each layer and via 5.6.2. Diamond SI: Sign-off Verification-level SI Diamond SI is a sign-off verification level signal integrity analysis tool from magma Design Automation. Diamond SI uses a highly sophisticated SI engine that accounts for high-order effects using transistor-level dynamic analysis. It works with standard formats and interfaces and fits into existing implementation flows. It handles today's multi- 164 million gate designs in a timely manner. The Signal Integrity Analysis engine efficiently filters out non-problem areas without missing any violations. It supports hierarchical design flows. It provides the modeling capability necessary to support the integration of third-party IP (memory blocks, hard macros, cores). Diamond SI uses a distributed parasitic model just like Blast Noise, which takes edge-rate degradation into account. It uses a sophisticated multi-aggressor model that takes full account of overlapping timing windows to filter non-problems and identify worst-case problems (this includes the ability to account for variations in the holding resistance of the gate driving the victim net). It considers non-pessimistic glitch analysis that takes account of the width of pulses as well as their height. Diamond SI has ability to concurrently consider crosstalk (both noise and timing), voltage drop (IR drop), and electromigration and their interrelationships. Open-system standard interface format allows Diamond SI to be integrated into existing flows [Magm03a]. It is tightly integrated into Magma's IC implementation flow (including sharing the same unified data model). Sophisticated Multi-Aggressor Model: Diamond SI employs a sophisticated multi-aggressor model that takes full account of overlapping timing windows to filter non-problems and identify worst-case problems. Knowing the timing windows when the aggressor nets may switch allows Diamond SI to determine when the worse case crosstalk may occur. Worse case scenarios will involve both aggressors switching simultaneously, and Diamond SI will use this information to evaluate potential glitches (overshoot, undershoot, noise) and timing ramifications (delays or speedups causing setup or hold violations, respectively). 165 Non-pessimistic Glitch Analysis: Diamond SI uses "AC noise margin" technique that calculates the transfer characteristic of the load gate and takes account of both the height and width associated with a pulse. This produces more accurate results, which reduces pessimism in the form of false errors. Voltage Drop Analysis: Diamond SI performs the final voltage drop analysis on the post-layout design. At this stage, accurate RC parasitic values can be extracted and used to test the robustness of the local and global power grids. The process starts with the automatic extraction of the power grid network in a form suitable for voltage drop analysis. Fig 5.9. The Resistive Power Grid Network Diamond SI characterizes the way this noise propagates itself onto the signal lines in terms of increased delays and increased susceptibility to crosstalk effects. 166 Concurrent Evaluation to Analyze Interdependent SI Effects: Diamond SI treats effects like crosstalk, voltage drop, and electromigration concurrently and also analyzes their impact on timing by running the embedded timing analysis engine. Tight Integration with the Magma IC Implementation Flow: Diamond SI supports standard interface formats such as GDSII, LEF, DEF, SDF, SPEF, SDC, VCD, .lib, etc. However, Diamond SI is most powerful when used in conjunction with Magma's implementation tool suite. Diamond SI takes full advantage of Magma's unified data model, and shares such data as signal slews, critical paths, timing data, parasitic data, design netlist/layout, characterized libraries, and process comers with all of the other implementation and analysis engines. Diamond SI generates the simulation vectors required to perform the SI analysis and back-annotates the resulting delays to static timing analysis tools to locate any critical paths. Furthermore, results from Diamond SI can be fed back to Blast Fusion and Blast Noise and used in conjunction with the other implementation and analysis engines to perform incremental updates and fine-tune the design for efficiency and correctness. 5.7: Table 5.1. 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Summary: This chapter starts with a brief discussion on the need for signal integrity tools. Signal Integrity analysis and reduction tools from five major EDA vendors namely, Cadence Design Systems, Synopsys Inc., Sequence Design, Monterey Corp., Magma Design Automation are discussed in detail. A comparative analysis on these tools is provided with feedback reports from several user groups and industry reports. 171 Chapter 6 Discussion The main contributors to deterioration of signal integrity are identified as interconnect crosstalk, power grid noise, substrate coupling and inductance effects. Designers are already seeing the effects of interconnect crosstalk and power grid noise. Analog circuits have experienced substrate coupling effects. Designers started looking into reducing the substrate coupling effects in digital designs. Our study on several analysis and reduction techniques allowed us to compare the methods. We provide the results on the basis of different contributors to signal integrity effects. 6.1. Crosstalk: Crosstalk is defined as the deviation from the ideal signal waveform propagation in a interconnect due to the influence of signal transitions in other wires in the neighborhood. The net experiencing crosstalk is termed as victim. The net imposing the effects is termed as aggressor. 172 The three analysis main analysis methods proposed for crosstalk analysis are: • Devgan's Model • Lumped RC Model • Distributed Two - 1t RC Model Devgan's model is the initial model proposed for crosstalk analysis. It models victim aggressors as RC trees. Computations are complex. Lumped RC model is being used in most EDA vendor tools for analyzing crosstalk. As the capacitance is lumped resistance becomes an important factor for calculating the width of the glitch on the victim net. Two - 1t RC model is considered to be the efficient model than compared to Devgan's model and Lumped RC model. It models the effect of, not only the adjacent aggressors but also distant aggressors on the victim net unlike other models. The first commercial version of this model is introduced by Magma Design Automation. Several reduction techniques were proposed for crosstalk reduction. They are: • Routing • Wire ordering • Buffer insertion • Intentional skewing • Transistor sizing • Power supply shielding • Raised cosine signaling 173 Several reduction techniques are compared in terms of effectiveness, delay and area 6.1.1. Routing: 6.1.1.a. Grid-less routing model- Wire Spacing: Medium Effectiveness - Crosstalk is indirectly proportional to the spacing between wires. Therefore, increase spacing between wires can significantly reduce crosstalk. Unfortunately, in order to satisfy realistic area constraint, there is usually not much room for spacing, and this results in less effectiveness. Also at times, if area is fixed, increasing space between 2 wires leads to decreasing space between another pair of wires. The effectiveness of coupling reduction cancels out in such case. Obviously, if no area limitation is enforced, then spacing is a very effective solution. Low Delay - Increasing wire separation and therefore routing distance can potentially introduce a minor routing delay. Low Area - Generally, spacing is done while keeping the total chip area the same. Therefore, overall area does not suffer from spacing algorithms, as it merely tries to determine how to use unoccupied area resources. 6.1.l.b. Gridded routing model- Channel Routing: Medium Effectiveness - Given the high density of the chip today, it is very difficult to avoid crosstalk for the majority of the chip through channel routing. In a confined space, moving a wire to reduce an overlap with a targeted wire will lead to increasing overlap 174 with another wire. In the rare case that routing resources vs. transistor count is more than sufficient, then channel routing can be effective. Low Delay - Routing can introduce delay through routing capacitance. For instance, if a wire had to be routed through a longer path, then the wire capacitance could dominate the total capacitance. However, channel routing is done post-layout, where a traditional routing algorithm had already been applied. Post-layout routing only utilizes the extra track or layer resources to reduce long wire overlaps, so the increase in wire length is not significant. Also, because channel routing is typically applied to a small region at a time (divide-and-conquer), long wire path will typically not be of concern. Low Area - Generally, channel routing tries to re-route wires through unemployed neighboring layers and/or tracks. Therefore, the area increase is minimal. 6.1.2 Wire Ordering: Low Effectiveness - Wire ordering uses the traveling salesman heuristics to determine an appropriate wire ordering. The number of wires to be routed is significant, this solution does not look promising. Low Delay - The delay should not be a factor. The reordered wire delay is insignificant. Low Area- The area should not be much different, since reordering will use relatively the same amount of resources available for routing. between wires, buffer insertion will 175 become less useful as technology advances. Even if buffer is inserted, smaller segments can still have dominant coupling capacitance due to their distance. 6.1.3. Buffer insertion: Low Effectiveness - Adding buffers can reduce the parallel overlap effect, but it cannot resolve the spacing influence. Buffer insertion will become less useful as technology advances. Even if buffer is inserted, smaller segments can still have dominant coupling capacitance due to their distance. Low Delay - The delay through a buffer is small compared to the bottleneck of a system. Low Area - Buffers are just inverters, so buffer insertion technique will not increase the size of a chip dramatically. 6.1.4. Intentional Skewing: Low Effectiveness - Although skewing takes care of the simultaneous switching event, skewing alone will not remove the coupling capacitance between two overlapping wires. Crosstalk is still significant even if non-simultaneous switching occurs. Low Delay - Inverter chain that enforces the skewing will not incur much delay. Low Area - Inverter chain does not occupy much area. 176 6.1.5. Transistor Sizing: High Effectiveness - Sizing can determine a gate's noise margin as well as the driver strength. Through sizing, the receiver can withstand certain noise disturbance level, or the driver (sender) can maintain a steady voltage even in the presence of noise. The downside of this solution is that the effectiveness is inversely proportional to the area. Sizing also can impact the delay. Therefore, although sizing is effective, it will impact other parameters so much that usually the sizing amount is limited. Medium Delay - The delay through sizing should remain relatively the same, sometimes even faster due to larger gate size and therefore stronger current drive. However, sizing can lead to a larger gate capacitance, which can increase the RC delay on the wire and slow down the signal speed. Medium Area - Effective sizing will need to be applied to many gates. When all these gates are sized up, this will inflict an area penalty. 6.1.6. Power Supply Shielding: High Effectiveness - By isolating the wires from each other, the coupling capacitance can be effectively minimized. This is due to the fact that transitioning wires do not neighboring each other anymore and no simultaneous transition can take place. In order to implement power supply shielding, there must be enough space in between wires to insert the shield. However, this is not always the case. 177 Low Delay- Shielding will cause wires to be placed further apart, which can possibly lead to minor routing delay. High Area - Inserting shields between every wire can result in significantly more area. Implementing partial shielding could lessen the area penalty, but then the effectiveness will decrease. 6.1.7. Raised Cosine Signaling: Low Effectiveness - Crosstalk noise caused by high frequency signals are eliminated, but the lower-frequency components will still induce crosstalk. Because crosstalk is more dependent on spacing and overlap than on the operating frequency, this scheme will not be as effective as the others. Low Delay- Small delay is incurred, as the signal needs to go through some type of transmitter in order to be converted into RCA pulses. There is also a de-conversion delay, but this delay is minor as well. Low Area- the transmitter and the receiver circuitry of the RCA do not take up much area. 178 Etfediveaess Delay Area \Vire Spacing Medium Low Low Channel Routing Medium Low Low Wire Ordering Low Low Low Buffer Insertion Low Low Low Intentional Skewing Low Low Low Transistor Siziag High Medium Medium Power Supply High Low High Shielding Raised-Cosine Low Low Low Signaling I Table 6.1. Comparison of Crosstalk Reduction Techniques 6.2. Power Grid Noise: Computations in integrated circuits are driven by the energy from a DC power supply. The two main concerns in the design of the power grid and the long term reliability of the interconnects in the power grid. Power grid analysis is performed in two phases: • Static Approach • Dynamic Approach 179 A static approach to calculate the currents is useful as a first step in power grid analysis. Static calculation is performed by considering the amount of charge drawn from power grid during each clock cycle on the switching activity at the gate level. Dynamic analysis considers parasitic data unlike static approach while performing IR drop analysis. Dynamic analysis also provides average current values for electromigation analysis. Several reduction techniques for power grid noise were proposed: • Circuit Techniques ~ Increasing rise time and fall time ~ Reducing Switching Voltage ~ Reducing Switching Capacitance • Improved Noise Immunity ~ Dynamic Logic ~ Regulated Supply ~ Differential Signaling ~ Substrate Referencing • Power Grid Noise Suppression ~ Separate Supply/Guard Rings ~ Electromigration reduction 180 Making arrival time or fall time process independent is one popular technique for power grid noise reduction. Reducing switching voltage lower signal swing but at the same time makes the receiver more sensitive to noise. Switching capacitance is reduced by making the two adjacent interconnects not to switch at the same time. This technique introduces a delay on time shifted wires. Dynamic logic can be significantly increased by providing weak feedback to dynamic nodes. However, weak feedback does not prevent delay failures. Supplying stable on-chip voltage is termed as regulated supply. The problem with this technique is that it fails ifumegulated supply is varying beyond a certain limit. Differential signaling allows external noise appear as common mode range on the receiver. This technique fails if the noise on the signal exceeds common mode range on the receiver. Substrate referencing uses substrate on chip as the only reference level. Separate supply/guard rings can be used to reduce power grid noise. This technique increase area. Decoupling capacitors can be used to reduce power grid noise by intentionally adding capacitance. Electromigration problems are reduced by wire spacing. 6.3. Substrate Noise: The parasitic material of substrate influences the behavior of a circuit. The capacitance of the substrate delays signal transmissions to different locations of the device. There are four main analysis techniques for substrate noise coupling. They are: • Finite Difference Mesh Method • Boundary Element Method • Preprocessing Analytical Method 181 • Simple Resistive Macromodel Method Finite difference mesh method is the first analysis method proposed for substrate noise. It depends highly on the resolution of discretization. It is used for post-layout extraction. The RC mesh matrix is large. Boundary element method uses green's function for analyzing substrate noise. It is an efficient post-layout analysis method. Preprocessing analytical method gives a priori insight about substrate noise to the designer. The trade of this method is that the accuracy is very low. Simple resistive macromodel method is based on a physical understanding of the current flow paths. This method is simple and accurate. Several reduction techniques for substrate noise are proposed. They are: • Guard rings • Nwell trench • Supply bounce reduction • Floorplanning The guard rings is commonly utilized in the prevention of the substrate noise in the IC design. The guard rings are placed around the noisy and sensitive circuitry. Nwell trenches can be used in between the noisy and sensitive circuitry to block the substrate current flowing near the surface of the substrate. Inductance of the package and bond wires can lead to supply bounce. The supply bounce cause voltage drop. This supply bounce is solved multiple or shorter bond wire connections. This is very expensive due to extra package costs. Efficient floorplanning helps in reducing substrate noise. 182 6.4. Inductance Noise: Inductance effects are particularly significant for global interconnect lines such as those in clock distribution networks, signal buses, and power grids for high performance integrated circuits. Two analysis methods were proposed for modeling inductance. They are: • Loop inductance model • Partial Elements Equivalent Circuit (PEEC) model Loop inductance model does not consider capacitance for extracting inductance. The capacitance is modeled as a lumped capacitance. A RLC ladder circuit is constructed and solved. This models assumes the current return path as power grid, which is not the case in always. Partial Equivalent Elements Circuit (PEEC) model allows extraction of partial inductances. Analytical formulae are used for calculating self and mutual inductances. Several inductance noise reduction techniques were proposed. They are: • Shielding • Twisted - bundle layout structures • Staggered inverter patterns • Inter - digitated wires • Shield insertion and net ordering Inductance can be reduced by shielding, which sandwiches a signal line between ground return lines or guard traces. A twisted bundle layout structure is a recent approach 183 proposed for minimizing inductive coupling noise. This technique uses complimentary and opposite current loops in the twisted bundle layout structure. This allows cancellation of magnetic fluxes arising from any signal net within a twisted group. Staggered inverter patterns reduce inductance by reducing the length of overlapping portion between adjacent wires. Inter-digitated wires is based on splitting wider wires into multiple thinner wires with shields in between. This technique increases the amount of metallization used for interconnect. Shield insertion and net ordering techniques are used based on efficient algorithms for reducing inductance noise. 6.5. Recommendations Based On Our Survey: Recommendations are provided for analysis techniques, reduction techniques and EDA vendor tools for factors affecting signal integrity in integrated circuits, based our survey. 184 Table 6. 2. Recommendation based on survey of Analysis methods, reduction techniques and EDA vendor tools for signal integrity in integrated circuit design Factors :affecti.Jig Analysis Method Reduction Tecludques Tools Signal Integrity Transistor Sizing Physical Studio Power Supply Shielding DiamondS! Crosstalk Two 1t RC Model Wire Spacing CeltiC Channel Routing Reducing Switching Physical Studio Power Grid Noise Dynamic Analysis Capacitance (Csw) Voltage Storm Separate Supply/ Guard Rings Dec oupling Capacitors Simple Resistive Macromodel (Pre- Layout) Guard Rings Substrate Noise Boundary Flo orplanning Substrate Storm Elements Method (Post-Layout) Inductance Noise Partial Equivalent Shielding Elements Method Inter-Digitated Wires FastHeruy (PEEC) Twisted Bundle Layout (Extraction only) 185 Chapter 7 Conclusions Our work titled "Survey of Design Techniques for Signal Integrity" explains factors contributing to deterioration of signal integrity in integrated circuit design, analysis methods, reduction techniques, methodologies and EDA vendor tools. Our first objective was to develop a methodology that considers the inter-relation between different contributors to signal integrity effects and utilizes this methodology in analyzing and reducing the effects. Our second objective was to aid in developing a high - level methodology that monitors signal integrity effects. Our initial work started with identification of factors affecting signal integrity with decreasing feature size. The factors identified are interconnect crosstalk, power grid noise, substrate noise and inductance effects. Today's Integrated Circuit (IC) designers are already dealing with interconnect crosstalk, power grid issues. Substrate coupling has been around in analog designs for quiet sometime. Digital designers are slowly seeing the effects on the designs. Digital designers started working on reducing the substrate 186 coupling effects. With frequencies runmng into Giga-Hertz ranges inductance is becoming a bottleneck. Industry and academia proposed several analysis and reduction methodologies but efficient tools are yet to evolve. So, we started working towards identifying analysis models and reduction techniques for factors affecting signal integrity. Several proposed analysis models and reduction techniques were summarized. While working on identifying analysis models and reduction methods, we started doing some ground work on the feasibility to these analysis models and reduction methods in present methodologies and tools for deep sub-micron designs. This led to our work towards signal integrity centric design methodologies that are followed by chip designers. We also summarized tool-driven design methodologies from several Engineering Design Automation (EDA) vendors. Several tool flows were analyzed from Cadence Design Systems, Synopsys Inc., Sequence Design, etc. One major bottleneck is the dataflow between different tools in physical design flow. We also noticed stringent constraints on third party tool support between different physical design flows ofEDA vendors. We also noticed present design methodologies consider contributors to signal integrity effects as individual contributors even though they have similar effects. So we noticed the need for a methodology that considers the inter-relation between different contributors to signal integrity effect and utilize this relation in analyzing and reducing the effects. Our work on nOise reduction and tolerance stressed on the need for a high-level methodology for analysis of signal integrity effects. This methodology considers the transactions between different elements at high-level still considering the circuit level 187 effects that contributes to noise such as coupling capacitance. This early analysis data can later be used at placement and routing stages for a complete detailed analysis. Our goal here is to reduce the production cost and design time. This high -level methodology reduces silicon respins. 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