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Full Screen View SURVEY OF DESIGN TECHNIQUES FOR SIGNAL INTEGRITY by Raghuveer Karnati A Thesis Submitted to the Faculty of The College ofEngineering in Partial Fulfillment of the Requirements for the Degree of Master of Science Florida Atlantic University Boca Raton, Florida December 2003 SURVEY OF DESIGN TECHNIQUES FOR SIGNAL INTEGRITY by Raghuveer Kamati This thesis was prepared under the direction of the candidate's thesis advisor, Dr. Ravi Shankar, Department of Computer Science and Engineering, and has been approved by the members of his supervisory committee. It was submitted to the faculty of The College of Engineering and was accepted in partial fulfillment of the requirements for the degree of Master of Science. SUPERVISORY COMMITTEE: Po_:~ Thesis Advisor Dr. Zvi Roth Dr. Sam Hsu rman, Department of Computer S tence and engineering ~ZL~ Dean, College of Engineering Division of Research and Graduate Studies Date 11 ACKNOWLEDGEMENTS I take this opportunity to extend my whole - hearted thankfulness to my thesis advisor and mentor Dr. Ravi Shankar, whose vision and commitment got me here from the basics of a transistor to Signal Integrity in Deep Sub-Micron designs. I thank my committee members Dr. Sam Hsu and Dr. Zvi Roth for going through my manuscript and for their valuable comments. I extend my thanks to my friend Ghaiyyur Quraishi, Application Engineer, Mentor Graphics Corporation, for his help with parasitic extractors and his strong support. I thank Dr.Khoman Phang and Vincent Mui for giving access to their work on Substrate Coupling Noise. I extend my thanks to Vanitha Siva Subramanyam for her help with conclusions and figures of my thesis and Anbuselvan Kuppuswamy for helping me with concepts of signal integrity in RF and PCB designs. I appreciate Haritha Jillelllamudi for her support and help with arranging my thesis. I also thank Dr. Surya Prasad Jayadevappa for his valuable suggestions. I thank Soham Soni for being my partner in Assura Evaluation project. I thank my colleagues at CVSI, Gaurav Shah and Alok Seth for patiently listening to my ideas for my thesis. I thank Jigisha Goswami and Abhijit Ajmera for lll helping me with system problems. I thank my Uncle, Aunt and Vineet for their support through out this work. I also thank Dr. Tarun Prasad for his cooperation. I extend my gratitude to my family, who always gave me the motivation to succeed. Last but not least, I thank Lord Raghavendhra for his blessings, which gave me the strength and courage to complete this work successfully. IV ABSTRACT Author: Raghuveer Karnati Title: Survey of Design Techniques for Signal Integrity Institution: Florida Atlantic University Advisor: Dr. Ravi Shankar Degree: Master of Science Year: 2003 Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems that effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction. v LIST OF CONTENTS List of Figures .....................................................................................xiii List of Tables ....................................................................................... xvii Glossary ................................................................................................ xviii 1. INTRODUCTION .............................................................................. 1 1.1. Introduction .............................................................................. 1 1.2. Deep Submicron Design ............................................................... 1 1.3. Approach Used for Literature Search, Analysis and Synthesis .................. 6 1.4. What is Signal Integrity .............................................................. 10 1.5. Introduction to Common Signal Integrity .......................................... 13 1.6. How signal Integrity Effects Affect DSM Designs ............................... 17 1. 7. Overview of this Report .............................................................. 19 1.8. Summary ............................................................................... 20 2. SIGNAL INTEGRITY ISSUES AT ABSTRACT IP LEVEL. ••.••..............•••. 21 2.1. Introduction ............................................................................21 2.2. Signal Integrity Issues at Abstract IP Level.. ......................................24 2.2.1. A Designers Perspective ofSI Issues ................................... .25 vi 2.2.2. I P Authors Perspective ofSI Issues .................................... 29 2.2.3. I P Block Integrators Perspective of SI Issues ......................... 32 2.2.4. General Techniques for Solving SI Issues in SoC Designs ......... .34 2.3. Overview of Signal Integrity Specs for IP Blocks ............................... .34 2.4. Summary ...................................................................................... 36 3. SIGNAL INTEGRITY ISSUES AT IMPLEMENTATION LEVEL ............................................................................................37 3.1. Introduction ............................................................................ 37 3.2. Interconnect Noise Fundamentals ................................................... 38 3.3. Crosstalk Analysis ....................................................................40 3.3.1. Devgan Model. .............................................................41 3.3.2. Lumped RC Model. ...................................................... .42 3.3.3. Distributed Two Pi RC Model.. .........................................43 3.4. Crosstalk Reduction ................................................................. .44 3 .4.1. Routing ......................................................................44 3.4.1.a. Grid -Less Routing Mode- Wire Spacing ................. .45 3.4.1.b. Gridded Routing Model- Channel Routing ............... .46 3 .4.2. Wire Ordering ..............................................................48 3.4.3. Buffer Insertion ............................................................ 48 3 .4.4. Intentional Skewing ...................................................... .49 3.4.5. Transistor Sizing ........................................................... 50 3.4.6. Power supply Shielding ................................................... 50 Vll 3.4.7. Raised cosine Signaling ................................................... 51 3.5. Comparative Study of Crosstalk Reduction Techniques ........................ 52 3.6. Power Grid Noise Fundamentals ................................................... 53 3.7. Power Grid Analysis .................................................................. 56 3.7.1. Static Approach ............................................................ 57 3.7.2. Dynamic Approach ........................................................ 58 3.7.3. Analyzing Power Grid Data ..............................................60 3.7.4. Electromigration Analysis ................................................61 3.8. Power Grid Noise Reduction Techniques ......................................... 62 3.8.1. Circuit Techniques ......................................................... 62 3.8.1.a. Increasing Fall Time (tf) or Rise Time (ta) .................. 62 3.8.1.b. Reducing Switching Voltage (Vsw) ......................... 63 3.8.l.c. Reducing Switching Capacitance (Csw) ..................... 63 3.8.2. Improved Noise Immunity ................................................ 63 3.8.2.a. Dynamic Logic .................................................. 63 3.8.2.b. Regulated Supply ............................................... 64 3.8.2.c. Differential Signaling .......................................... 64 3.8.2.d. Transmitting Reference Level. ................................ 65 3.8.2.e. Substrate Referencing .......................................... 65 3.8.3. Power Grid Noise Suppression .......................................... 66 3.8.3.a. Separate Supply/Guard Rings ................................. 66 3.8.3.b. Decoupling Capacitance ....................................... 66 3.8.4. Reducing Electromigration Problems ................................... 67 Vlll 3.9. Substrate Noise Fundamentals ...................................................... 68 3.9.1. Parasitic Effect ofSubstrate .............................................. 68 3.9.2. Substrate Noise Coupling Effects in Mixed Signal Integrated Circuits ......................................................... 70 3.10. Modeling Techniques for Substrate Noise Coupling ........................... 72 3.10.1. Finite Difference Mesh Method ........................................ 72 3.10.2. Boundary Elements Method ............................................ 76 3.10.3. Preprocessing Analytical Method ...................................... 83 3.1 0.4. Simple Resistive Macromodel Method ...............................
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