IEEE Standard A2Z 1 4/3/2019
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Prostep Ivip CPO Statement Template
CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of -
Digital Systems Modeling Chapter 2 VHDL-Based Design
Digital Systems Modeling Chapter 2 VHDL-Based Design Alain Vachoux Microelectronic Systems Laboratory [email protected] Digital Systems Modeling Chapter 2: VHDL-Based Design Chapter 2: Table of contents ♦ VHDL overview ♦ Synthesis with VHDL ♦ Test bench models & verification techniques A. Vachoux, 2004-2005 Digital Systems Modeling Chapter 2: VHDL-Based Design - 2 A. Vachoux 2004-2005 2-2 Digital Systems Modeling Chapter 2: VHDL-Based Design VHDL highlights (1/2) ♦ Hardware description language • Digital hardware systems • Modeling, simulation, synthesis, documentation • IEEE standard 1076 (1987, 1993, 2002) ♦ Originally created for simulation • IEEE standards 1164 (STD_LOGIC) and 1076.4 (VITAL) ♦ Further adapted to synthesis • Language subset • IEEE standards 1076.3 (packages) and 1076.6 (RTL semantics) A. Vachoux, 2004-2005 Digital Systems Modeling Chapter 2: VHDL-Based Design - 3 A. Vachoux 2004-2005 2-3 Digital Systems Modeling Chapter 2: VHDL-Based Design VHDL highlights (2/2) ♦ Application domain (abstraction levels): Functional -> logic ♦ Modularity • 5 design entities: entity, architecture, package declaration and body, configuration • Separation of interface from implementation • Separate compilation ♦ Strong typing • Every object has a type • Type compatibility checked at compile time ♦ Extensibility: User-defined types ♦ Model of time • Discrete time, integer multiple of some MRT (Minimum Resolvable Time) ♦ Event-driven simulation semantics A. Vachoux, 2004-2005 Digital Systems Modeling Chapter 2: VHDL-Based Design - 4 A. Vachoux 2004-2005 2-4 Digital Systems Modeling Chapter 2: VHDL-Based Design VHDL-based design flow Editor (text or graphic) Test bench models VHDL packages RTL model Logic simulation Logic/RTL Constraints synthesis (area, timing, power) VHDL VITAL standard cell Gate-level modeld netlist Standard cell library SDF file Place & route Delay Layout extraction A. -
650 Series ANSI DNP3 Communication Protocol Manual
Relion® Protection and Control 650 series ANSI DNP3 Communication Protocol Manual Document ID: 1MRK 511 257-UUS Issued: June 2012 Revision: A Product version: 1.2 © Copyright 2012 ABB. All rights reserved Copyright This document and parts thereof must not be reproduced or copied without written permission from ABB, and the contents thereof must not be imparted to a third party, nor used for any unauthorized purpose. The software and hardware described in this document is furnished under a license and may be used or disclosed only in accordance with the terms of such license. Trademarks ABB and Relion are registered trademarks of the ABB Group. All other brand or product names mentioned in this document may be trademarks or registered trademarks of their respective holders. Warranty Please inquire about the terms of warranty from your nearest ABB representative. ABB Inc. 1021 Main Campus Drive Raleigh, NC 27606, USA Toll Free: 1-800-HELP-365, menu option #8 ABB Inc. 3450 Harvester Road Burlington, ON L7N 3W5, Canada Toll Free: 1-800-HELP-365, menu option #8 ABB Mexico S.A. de C.V. Paseo de las Americas No. 31 Lomas Verdes 3a secc. 53125, Naucalpan, Estado De Mexico, MEXICO Phone: (+1) 440-585-7804, menu option #8 Disclaimer The data, examples and diagrams in this manual are included solely for the concept or product description and are not to be deemed as a statement of guaranteed properties. All persons responsible for applying the equipment addressed in this manual must satisfy themselves that each intended application is suitable and acceptable, including that any applicable safety or other operational requirements are complied with. -
Multi-Processor Digital Control System NDC/P39814
Multi-Processor Digital Control System NDC/P39814 Our digital control system enables success in modern reactive power compensation. The ultimate parallel processing power of the system tops even the most demanding requirements. In the heart of SVC control or Series Capacitor protection, there is no room for errors. Instant response of the system is always based on accurate data measurement and reliable real-time calculations. NDC supports a high order of redundancy with a hot-swapable secondary system. Both systems, primary and secondary, are always up to date with the latest system events and measurements. They are also both synchronised with a common system time with TrueTime GPS. High reliability and performance of our control system ensures maximum availability for your investment. Technical data • Up to four parallel CPUs, 2310 MIPS/CPU • CPU card: MVME5500 • MPC7455 PowerPC® processor 1GHz • 512MB 133 MHz SDRAM • 32MB and 8MB Flash memory • Dual independent 64-bit 66 MHz PCI buses and PMC sites • VME bus • Gigabit Ethernet interface • 10/100BaseTX Ethernet interface • GPS Clock Synchronisation • Fast I/O: - Programmable digital inputs and outputs - AD: 64 x 16 bit @ 10 kHz - DA: 8 x 16 bit @ 10 kHz • Parallel HMI PC units • Data Concentrator / SCADA Gateway • Device Protocols • NDC SW Tool Chain: - INTERBUS - Compiler - EtherCAT - Configurator - IRIG-B - Simulator - IEC-60870-5-101 - System Debugger - IEC-60870-5-104 - Runtime - DNP3.0 - HMI RAD Tool Competence at your service Competence Map • Project Management • Electrical Engineering -
PREVENT DER CHAOS: a Guide to Selecting the Right Communications Protocols for DER Management
PREVENT DER CHAOS: A Guide to Selecting the Right Communications Protocols for DER Management Published January 2020 DISCLAIMERS Why QualityLogic’s Recommendations QualityLogic occupies a unique role in the development and implementation of communications protocols for DER management by vendors and utilities. Developing and supporting test tools for DER protocols provides an unparalleled knowledge of both the technologies and eco-systems working with the technologies. We have the privilege of advising utilities, vendors, alliances, research labs and regulators on the capabilities and implementation of specific DER protocol standards. We are constantly asked for both training and recommendations for the selection of a standard for specific applications. The increasing interest in the monitoring and management of DER resources begs for the type of analysis and guidance QualityLogic provides in this Guide. These Recommendations are a Starting Point The recommendations contained in this guide are those of QualityLogic and do not represent any other organization, alliance, company or government entity. The Recommendations should be viewed as a starting point and are based on models for use cases and deployment strategies. For specific applications an independent analysis should be conducted which may yield different results. The Recommendations also use a “snapshot” of the current state and adoption of protocols which is subject to change over time and may lead to different results than included here. To find out more about how recommendations were developed, or how to conduct an analyis for your situation contact us at [email protected]. ACKNOWLEDGEMENT QualityLogic would like to thank our long-time associate, Mark T. Osborn, for his major contribution to this white paper. -
Xilinx Synthesis and Verification Design Guide
Synthesis and Simulation Design Guide 8.1i R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. -
Powerplay Power Analysis 8 2013.11.04
PowerPlay Power Analysis 8 2013.11.04 QII53013 Subscribe Send Feedback The PowerPlay Power Analysis tools allow you to estimate device power consumption accurately. As designs grow larger and process technology continues to shrink, power becomes an increasingly important design consideration. When designing a PCB, you must estimate the power consumption of a device accurately to develop an appropriate power budget, and to design the power supplies, voltage regulators, heat sink, and cooling system. The following figure shows the PowerPlay Power Analysis tools ability to estimate power consumption from early design concept through design implementation. Figure 8-1: PowerPlay Power Analysis From Design Concept Through Design Implementation PowerPlay Early Power Estimator Quartus II PowerPlay Power Analyzer Higher Placement and Simulation Routing Results Results Accuracy Quartus II Design Profile User Input Estimation Design Concept Design Implementation Lower PowerPlay Power Analysis Input For the majority of the designs, the PowerPlay Power Analyzer and the PowerPlay EPE spreadsheet have the following accuracy after the power models are final: • PowerPlay Power Analyzer—±20% from silicon, assuming that the PowerPlay Power Analyzer uses the Value Change Dump File (.vcd) generated toggle rates. • PowerPlay EPE spreadsheet— ±20% from the PowerPlay Power Analyzer results using .vcd generated toggle rates. 90% of EPE designs (using .vcd generated toggle rates exported from PPPA) are within ±30% silicon. The toggle rates are derived using the PowerPlay Power Analyzer with a .vcd file generated from a gate level simulation representative of the system operation. © 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. -
Interconnect Solutions Short Form Catalog
Interconnect Solutions Short Form Catalog How to Search this Catalog This digital catalog provides you with three quick ways to find the products and information you are looking for. Just point and click on the bookmarks to the left, the linked images on the next page or the labeled sections of the table of contents. You can also use the “search” function built into Adobe Acrobat to jump directly to any text reference in this document. Acrobat “Search” function instructions: 1. Press CONTROL + F 2. When the dialog box appears, type in the word or words you are looking for and press ENTER. 3. Depending on your version of Acrobat, it will either take you directly to the first instance found, or display a list of pages where the text can be found. In the latter, click on the link to the pages provided. Interconnect Solutions Short Form Catalog Complete Solutions for the Electronics Industry 3M Electronics offers a comprehensive range of Interconnect Solutions for the electronics industry with a product portfolio that includes connectors, cables, cable assemblies and assembly tooling for a wide variety of applications. 3M is dedicated to innovation, continually developing new products that become an important part of everyday life across many diverse markets. A number of 3M solution categories are based on custom-designed products for specialized applications. 3M Electronics can help you design, modify and customize your product as well as help you to seamlessly integrate our products into your manufacturing process on a global basis. RoHS Compliant Statement “RoHS compliant” means that the product or part does not contain any of the following substances in excess of the following maximum concentration values in any homogeneous material, unless the substance is in an application that is exempt under RoHS: (a) 0.1% (by weight) for lead, mercury, hexavalent chromium, polybrominated biphenyls or polybrominated diphenyl ethers; or (b) 0.01% (by weight) for cadmium. -
Publication Title 1-1962
publication_title print_identifier online_identifier publisher_name date_monograph_published_print 1-1962 - AIEE General Principles Upon Which Temperature 978-1-5044-0149-4 IEEE 1962 Limits Are Based in the rating of Electric Equipment 1-1969 - IEEE General Priniciples for Temperature Limits in the 978-1-5044-0150-0 IEEE 1968 Rating of Electric Equipment 1-1986 - IEEE Standard General Principles for Temperature Limits in the Rating of Electric Equipment and for the 978-0-7381-2985-3 IEEE 1986 Evaluation of Electrical Insulation 1-2000 - IEEE Recommended Practice - General Principles for Temperature Limits in the Rating of Electrical Equipment and 978-0-7381-2717-0 IEEE 2001 for the Evaluation of Electrical Insulation 100-2000 - The Authoritative Dictionary of IEEE Standards 978-0-7381-2601-2 IEEE 2000 Terms, Seventh Edition 1000-1987 - An American National Standard IEEE Standard for 0-7381-4593-9 IEEE 1988 Mechanical Core Specifications for Microcomputers 1000-1987 - IEEE Standard for an 8-Bit Backplane Interface: 978-0-7381-2756-9 IEEE 1988 STEbus 1001-1988 - IEEE Guide for Interfacing Dispersed Storage and 0-7381-4134-8 IEEE 1989 Generation Facilities With Electric Utility Systems 1002-1987 - IEEE Standard Taxonomy for Software Engineering 0-7381-0399-3 IEEE 1987 Standards 1003.0-1995 - Guide to the POSIX(R) Open System 978-0-7381-3138-2 IEEE 1994 Environment (OSE) 1003.1, 2004 Edition - IEEE Standard for Information Technology - Portable Operating System Interface (POSIX(R)) - 978-0-7381-4040-7 IEEE 2004 Base Definitions 1003.1, 2013 -
Chapter 1. Origins of Mac OS X
1 Chapter 1. Origins of Mac OS X "Most ideas come from previous ideas." Alan Curtis Kay The Mac OS X operating system represents a rather successful coming together of paradigms, ideologies, and technologies that have often resisted each other in the past. A good example is the cordial relationship that exists between the command-line and graphical interfaces in Mac OS X. The system is a result of the trials and tribulations of Apple and NeXT, as well as their user and developer communities. Mac OS X exemplifies how a capable system can result from the direct or indirect efforts of corporations, academic and research communities, the Open Source and Free Software movements, and, of course, individuals. Apple has been around since 1976, and many accounts of its history have been told. If the story of Apple as a company is fascinating, so is the technical history of Apple's operating systems. In this chapter,[1] we will trace the history of Mac OS X, discussing several technologies whose confluence eventually led to the modern-day Apple operating system. [1] This book's accompanying web site (www.osxbook.com) provides a more detailed technical history of all of Apple's operating systems. 1 2 2 1 1.1. Apple's Quest for the[2] Operating System [2] Whereas the word "the" is used here to designate prominence and desirability, it is an interesting coincidence that "THE" was the name of a multiprogramming system described by Edsger W. Dijkstra in a 1968 paper. It was March 1988. The Macintosh had been around for four years. -
XMOS for AVB Ethernet Based Networking for Audio/Video
Only a few years ago, computer networks were complex beasts tended by special acolytes and running on different standards. Today they have become commonplace in many homes and offices, simply plugged together using Ethernet technology. The same revolutionary change is coming for Audio/Video (AV) networking, as AVB (Audio XMOS for AVB: Video Bridging) products that run over the same network, Ethernet based networking begin to enter the market. for Audio/Video Putting together networks of AV equipment for professional and consumer use, or for use in How Ethernet Works vehicles, is about to become simpler while also Within Ethernet, data is transmitted between delivering better quality. No longer will devices (such as a computer and a printer) in specialist connectors and cables be needed to packets. Each packet carries one or more create a rats' nest of connectivity. Instead addresses for its destination. Like a postal packet traversing the postal system, the network has no Audio Video Bridging (AVB), a set of knowledge of what is in the packet, but uses the international standards, will make setting up address to pass the packet to the next point in the and managing networks almost as simple as network. just plugging together the different elements. In an Ethernet based network, each endpoint Sound and video sources will be mixed and (computer, storage element, printer etc.) is distributed to screens and speakers, with high identified by a unique address and has a single quality, low latency and tight synchronization. connection to the network, through an Ethernet Furthermore, the connectors and cables are switch. -
VM E Bus S Ingle -B Oard C Om Puter
DATASHEET KEY FEATURES 2eSST VMEbus protocol with The Motorola MVME6100 The promise of the VME 320MB/s transfer rate across series provides more than just Renaissance is innovation, the VMEbus faster VMEbus transfer rates; it performance and investment provides balanced performance protection. The MVME6100 MPC7457 PowerPC® processor from the processor, memory series from Motorola delivers running at up to 1.267 GHz subsystem, local buses and I/O on this promise. The innovative 128-bit AltiVec coprocessor for subsystems. Customers looking design of the MVME6100 parallel processing, ideal for for a technology refresh for their provides a high performance data-intensive applications application, while maintaining platform that allows customers backwards compatibility with to leverage their investment in Up to 2GB of on-board DDR their existing VMEbus infra- their VME infrastructure. ECC memory and 128MB of structure, can upgrade to the fl ash memory for demanding The MVME6100 series supports MVME6100 series and applications booting a variety of operating take advantage of its enhanced systems including a complete Two 33/66/100 MHz PMC-X performance features. range of real-time operating sites allow the addition of systems and kernels. A VxWorks industry-standard, application- board support package and specifi c modules Linux support are available for Dual Gigabit Ethernet interfaces the MVME6100 series. for high performance networking The MVME6100 series is the fi rst VMEbus single-board computer (SBC) designed with the Tundra Tsi148 VMEbus interface chip offering two edge source synchronous transfer (2eSST) VMEbus performance. The 2eSST protocol enables the VMEbus to run at a practical bandwidth of 320MB/s in most cases.