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X704 Technical Summary Advance Information Exponential X704TM RISC Microprocessor An Implementation of the PowerPCTM Architecture technical summary © Exponential Technology 1996 All rights reserved. No part of the contents of this document may be reproduced or transmitted in any form without the express written permission of Exponential Technology, Inc. This document contains information on a product which has not been commercially released, and may contain technical inaccuracies or typographical errors. Information in this document is subject to change without notice. Exponential makes no express or implied warranty of any kind and assumes no liability or responsibility for any errors or omissions in this document. PowerPC, PowerPC Architecture, POWER and POWER Architecture are trademarks of International Business Machines Corporation. Exponential and the Exponential logo are trademarks of Exponential Technology, Inc. All other trademarks and registered trademarks are the property of their respective owners. Contents Preface 1.Processor Overview. 5 1.1Processor Features . 5 1.2Processor Organization. 7 1.2.1Instruction Fetch Unit . 8 1.2.2Decode Unit . 10 1.2.3Branch Unit . 10 1.2.4Integer Execution Unit . 10 1.2.5Load/Store Unit. 11 1.2.6Floating-Point Execution Unit. 13 1.2.7Level 2 Cache . 14 1.2.8Bus Interface Unit . 15 2.PowerPC Architecture Compliance. 17 2.1X704 User Instruction Set Architecture (UISA) . 17 2.1.1Reserved Fields . 17 2.1.2Classes of Instructions . 17 2.1.2.1Defined Instruction Class . 17 2.1.2.2Illegal Instruction Class . 18 2.1.2.3Reserved Instruction Class . 18 2.1.3Exceptions. 19 2.1.4Branch Processor. 19 2.1.4.1Instruction Fetching . 19 III 2.1.4.2 Branch Prediction . 19 2.1.4.3 Invalid Branch Instruction Forms . 19 2.1.5 Fixed-Point Processor . 20 2.1.5.1 Load/Store Unit . 20 2.1.5.2 Invalid Load/Store Instruction Forms . 21 2.1.5.3 Reservation Granularity . 21 2.1.5.4 Synchronization Instruction . 21 2.1.5.5 Data Breakpoints . 21 2.1.6 Fixed-Point Unit . 22 2.1.6.1 Invalid Fixed-Point Instruction Forms . 22 2.1.7 Floating-Point Unit . 23 2.1.7.1 Conformance with IEEE Standard . 23 2.1.7.2 Floating-Point Load/Store Operations . 23 2.1.7.3 Floating-Point Arithmetic Instructions . 23 2.1.7.4 Floating-Point Status and Control Register Instructions . 24 2.1.7.5 Optional Instructions . 24 2.1.7.6 Denormalized Numbers . 24 2.1.7.7 Floating-Point Exceptions . 24 2.1.7.8 Invalid Floating-Point Instruction Forms . 25 2.2 X704 Virtual Environment Architecture (VEA) . 25 2.2.1 Storage Model . 25 2.2.1.1 Caches . 25 2.2.1.2 Storage Consistency . 27 2.2.2 Effect of Operand Placement on Performance . 27 2.2.3 Cache Management Instructions . 27 2.2.3.1 Instruction Cache Block Invalidate (icbi ) . 27 2.2.3.2 Instruction Synchronize (isync ) . 28 2.2.3.3 Data Cache Block Touch (dcbt ) . 28 2.2.3.4 Data Cache Block Touch for Store (dcbtst ) . 28 2.2.3.5 Data Cache Block Zero (dcbz ) . 29 2.2.3.6 Data Cache Block Store (dcbst ) . 29 2.2.3.7 Data Cache Block Flush (dcbf ) . 30 2.2.4 Additional Diagnostic Instructions. 30 2.2.5 Storage Access Ordering . 32 IV EXPONENTIAL X704 TECHNICAL SUMMARY 2.2.6 Executing Modified Code . 32 2.2.7 Atomic Update Primitives. 33 2.2.8 Timer Facilities . 33 2.3 X704 Operating Environment Architecture (OEA) . 33 2.3.1 Reserved Fields in Storage Tables . 33 2.3.2 Exceptions. 33 2.3.3 Branch Processor. 34 2.3.3.1 SRR0 and SRR1 . 34 2.3.3.2 MSR . 34 2.3.4 Fixed-Point Processor . 35 2.3.4.1 Software Use SPRs . 35 2.3.4.2 Processor Version Register . 35 2.3.4.3 Additional Special Purpose Registers . 35 2.3.4.4 TLB Miss Registers . 38 2.3.4.4.1 TLB Miss Address Register (MAR) . 38 2.3.4.4.2 TLB Miss Interrupt Status Register (MISR). 39 2.3.4.4.3 TLB Miss PTE Compare Register (CMP) . 39 2.3.4.4.4 TLB Miss PTEG Address Hash Registers (HASH1 and HASH2) . 40 2.3.4.4.5 TLB Miss Update LRU Registers (TLBLRU0 and TLBLRU1) . 40 2.3.4.4.6 TLB Miss Update MRF Register (TLBMRF) . 41 2.3.4.5 Debugging Registers . 41 2.3.4.5.1 Breakpoint Control Register (BPTCTL). 42 2.3.4.5.2 Instruction Address Breakpoint Register (IABR) . 44 2.3.4.5.3 Extended Data Address Breakpoint Register (XDABR). 44 2.3.4.5.4 Data Address Breakpoint Register (DABR) . 45 2.3.4.5.5 Event Register (EVENT) . 45 2.3.4.6 Processor Control Registers . 47 2.3.4.6.1 Modes Register (MODES) . 47 2.3.4.6.2 Machine Check Register (CHECK) . 48 2.3.4.6.3 L2/Bus Control Register (L2CTL) . 50 2.3.4.6.4 L2 Column Disable Register (L2CDR) . 52 2.3.4.7 Processor Identification Register (PIR) . 52 2.3.5 Storage Control. 53 2.3.5.1 Translation Lookaside Buffer (TLB) . 53 2.3.5.2 Block Address Translation . 54 2.3.5.3 Storage Access Modes . 54 2.3.5.4 Reference and Change Recording . 54 V 2.3.5.5 Storage Control Instructions . 54 2.3.5.5.1 Data Cache Block Invalidate (dcbi ) . ..
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