Xcell Journal Issue 42, Spring 2002

SU 2 PIG20 CL ORA XILINX, INC. XCELL JOURNAL ISSUE 42, SPRING 2002

Issue 42 Spring 2002 XcellXcelljournaljournal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS

PROGRAMMABLE WORLD 2002 Learn all about thethe newnew Virtex-II Pro FPGAs

TECHNOLOGY The PowerPC architecture: a programmer’s view Rocket I/O transceivers offer 3.125 Gbps capability SOFTWARE ISE 4.2i expands design productivity once again New tools for embedded processor software design NEWS Virtex-II receives Product of the Year award CoverCover StoryStory

AA revolutionaryrevolutionary breakthroughbreakthrough inin processingprocessing R andand systemsystem design,design, fromfrom XilinxXilinx andand IBMIBM LETTER FROM THE EDITOR Who Are You? What Did You Say?

any of you have taken the time to give us your very valuable feedback about how we can con- M tinue to improve this Xcell Journal. After all, it is your journal, and its only purpose is to make your job easier and more productive, while also providing insights into the trends and technologies that are shaping the future of logic design. The overwhelming majority of responses indicated that Xcell is a huge success, often read cover to cover, and then saved for later reference. Thank you! Here’s some of what we learned from our reader survey: • Most of you are design/development engineers (74%), doing digital logic design using FPGAs (88%) and CPLDs (76%), for industrial (38%), networking (35%), data processing (25%), and military (24%) applications, in companies of less than 500 employees (60%). • Your three most popular categories are technical (“how to”) articles, new product announcements, EDITOR IN CHIEF Carlis Collins [email protected] and the product reference guides. (You can bet these sections will grow fatter in future editions.) 408-879-4519 Your least popular category is Customer Success stories. MANAGING EDITOR Tom Durkin [email protected] • Most of you read Xcell Online and would still like to receive the printed journal, monthly – 530-271-0899 almost everyone wanted more information, more often. DESIGN & ILLUSTRATION Scott Blair Dan Teie More Information, More Often If you haven’t noticed, Xcell Online is a fast and efficient way to stay informed about Xilinx and its partners. And, it keeps getting better. As we develop the website, you will see many more articles Xcell journal about the topics that are important to you. And, you will find many valuable articles that we could Xilinx, Inc. not fit into the printed Xcell Journal (we receive far more content than we can print). You can see Xcell 2100 Logic Drive San Jose, CA 95124-3450 Online, and other Xilinx literature, at: www.xilinx.com/literature/. Phone: 408-559-7778 FAX: 408-879-4780 Virtex-II Pro and the New Programmable World 2002 ©2002 Xilinx Inc. All rights reserved. This issue of the Xcell Journal focuses not only on a new product, but also a revolutionary new Xcell is published quarterly. XILINX, the Xilinx logo, development paradigm. Our new Virtex-II Pro™ family of Platform FPGAs is truly unique and CoolRunner, Spartan, and Virtex are registered trademarks of Xilinx Inc. Alliance Series, Xilinx Foundation very powerful – it promises to change forever the way you approach system-level design. As this Series, AllianceCore, Foundation, IRL, LogiCORE, new technology quickly evolves, you will find the latest technical articles, online, as soon as we can SelectI/O, WebPACK, WebPOWERED, WebFITTER, QPro, XPERTS, XtremeDSP, CORE Generator, Rocket publish them, on Xcell Online. I/O, Fast Zero Power, SelectRAM, IP-Immersion, System ACE, ChipScope, and all XC-prefix products are You will also have the opportunity to hear the industry leaders discussing this new design paradigm, and trademarks, and The Programmable Logic Company is a service mark of Xilinx Inc. Other brand or product receive valuable training, at the Xilinx Programmable World 2002 event in April. Attend Programmable names are trademarks or registered trademarks of World 2002 either online or in person at various locations. See www.xilinx.com/pw2002 for details. their respective owners.

The articles, information, and other materials includ- Thanks again for your interest in Xilinx and Xcell. Our primary goal is to help you succeed, so please ed in this issue are provided solely for the conven- continue to send me your comments and suggestions. ience of our readers. Xilinx makes no warranties, express, implied, statutory, or otherwise, and accepts no liability with respect to any such articles, information, or other materials or their use, and any use thereof is solely at the risk of the user. Any person or entity using such information in any way releases and waives any claim it might have against Xilinx for any loss, damage, or expense caused thereby. Carlis Collins [email protected] View from the Top Page 4 Contents Spring 2002 Interesting Times at Xilinx Interesting Times at Xilinx ...... 4 Witness the worldwide, world-class debut of the Virtex-II Pro Platform FPGA solution for programmable systems. The New Era of Programmable Systems ...... 6

Virtex-II Pro: The Platform Has Arrived ...... 10 Cover Story Page 6 Virtex-II FPGAs – Product of the Year ...... 14

The New Era of Programmable Systems The PowerPC – A Programmer’s View ...... 16

The next breakthrough in processing and system design IBM’s PowerPC Strategy Road Map ...... 22 methodology from Xilinx and IBM. Rocket I/O Multi-Gigabit Transceivers ...... 24

Technical Focus Page 10 Best-of-Class Embedded Software Tools ...... 26

Virtex-II Pro FPGAs: The Platform for ISE 4.2i Expands Design Productivity ...... 30

Programmable Systems has Arrived New Config. Options for Virtex-II Pro ...... 32 The Virtex-II Pro solution heralds a paradigm shift in system architecture by moving design based on zones of programmability Platform FPGAs Take on ASIC SOCs ...... 35 to entire system-level programmability. Your Reconfiguration is in the E-mail ...... 40

Technical Focus Page 16 SignOnce and Break the IP Barrier ...... 44 The PowerPC Architecture: Bring on the Music – Take out the Noise ...... 46 A Programmer’s View Programmable Solutions for Set-Top Boxes ...... 48 An introduction to the PowerPC programming model. Low-cost Digital Video Reference Design ...... 53

Programmable Logic Enables Digital Displays ...... 54 Xilinx News Page 44 Digital Convergence Demands Reprogrammability ...... 60

SignOnce and Break the IP License Barrier The FlexBench Tool Suite ...... 64

Xilinx sponsors the Common License Consortium to streamline Modular Engineering Solutions Platform ...... 68 the IP licensing process and improve your time to market. Parallel Cable IV Connects Faster ...... 71

SCC-II Microsequencer ...... 72

Upgrade to Synopsys FPGA Compiler II ...... 76

Rocket I/O Multi-Gigabit Design Kit ...... 78 Subscribe to the Xilinx Xcell Journal at: www.xilinx.com/forms/literature.htm CoolRunner-II CPLD Development Kit ...... 80 There is no better way to keep up to date on the latest programmable logic technologies from Xilinx and its partners. Virtex-II Pro FPGA Data Sheet Overview ...... 82 Xilinx Product Reference Guide ...... 89

Visit Xcell Online for the latest news and information, as soon as it arrives. You can view and download the latest Xcell articles, and all up-to-date Xilinx literature, by visiting: www.xilinx.com/literature/index.htm. Xcell journal Viefromw the top InterestingInteresting TimesTimes

WitnessWitness thethe worldwide,worldwide, world-classworld-class debutdebut ofof thethe Virtex-IIVirtex-II ProPro PlatformPlatform FPGAFPGA solutionsolution atat XilinxXilinx forfor programmableprogrammable systems.systems.

4 Xcell Journal Spring 2002 View from the top

by Wim Roelandts Strategic Partnerships off as well. The Virtex-II Pro solution CEO, Xilinx comes with a complete set of Xilinx-specif- Xilinx, IBM®, and Conexant™ Systems ic embedded software tools for develop- There is an have been quietly working together to ment, simulation, and debugging. ancient curse: respond to the issues and challenges facing May you live in design teams and their corporations. The close alliance with our partners and the interesting times. Virtex-II Pro Platform FPGAs feature as tight integration of hardware and software No doubt, we many as four IBM PowerPC™ 405 in the Virtex-II Pro platform allows on- are living in processors immersed and embedded with- demand architectural synthesis with tremen- interesting times. I choose, however, to view in the FPGA fabric. Moreover, the Virtex- dous flexibility and scalability. You can effi- this as a blessing rather than a curse. True, II Pro devices connect to the outside ciently divide complex functions between competition is fierce and economic condi- high-speed implementation in hardware and tions are chaotic, but opportunities for high-flexibility implementation in software. growth and change in the programmable See for Yourself logic industry are limitless. In the process of delivering the Virtex-II Big drops in revenues and even the sudden Pro solution, Xilinx has had to change its disappearance of large customers have infrastructure to go beyond being a pro- forced us to revisit our strategies and redou- grammable logic supplier into becoming a ble our efforts. Preserving capital, maintain- programmable system provider. We knew ing time to market, coping with lower budg- that being a system-level provider didn’t ets, reducing unnecessary risks, and staying mean just innovation in silicon. It meant the course in the face of uncertain market acquisitions and alliances in areas of I/O conditions has tested the mettle of all of us. speed and connectivity, software develop- As we climb back up from the bottom of ment, design services – and preparing our this recession, we are bringing with us a entire workforce – from the experts in the new paradigm for Xilinx®. With the field to the experts in customer support – introduction of the Virtex-II Pro™ world via as many as 16 Rocket I/O™ to truly deliver a complete solution to our Platform FPGA, we have changed from a 3.125 multi-gigabit serial transceivers partners and customers. programmable logic supplier to a purvey- capable of interfacing with multiple paral- Talk is cheap. So, let us show you what the or of programmable systems. lel and serial protocols and standards. family of Virtex-II Pro Platform FPGAs What If? The Virtex-II Pro solution delivers both can do for you. I personally invite you and high-performance processing and high- your engineering design teams to Consider this: bandwidth connectivity all in one Programmable World 2002 to be • What if your corporation had access to device. And that’s not all. held April 17 in San Jose, an off-the-shelf, system-level product Xilinx XCITE™ digitally Boston, Paris – and more that allowed your design teams the max- controlled impedance sites to be announced later. imum flexibility at system level without technology removes hun- This worldwide exposi- the traditional inventory risks? dreds of termination tion and conference will resistors from the printed offer a general session and • What if this off-the-shelf product had all circuit board. Xilinx IP feature 16 presentations in the latest functionality they were look- Immersion and Active four technical tracks. ing for – and were way ahead of stan- Interconnect technologies dard cell technologies? Registration is mandatory, allow the PowerPC processors to seating is limited, but participa- • What if they could chose to never again bypass peripheral bus bottlenecks to tion is free. We, and our world-class part- deal with 0.13 micron silicon design connect directly with the FPGA logic and ners, want to train you for the next gener- issues or budget for huge NRE expenses? memory array. ation of embedded, system-level program- The what-ifs for this dream can go on and Our partnerships on the software side with mable devices. For more information, on – but this is not a dream. This is what Wind River Systems, The MathWorks, read this issue of Xcell Journal (including a Virtex-II Pro Platform FPGA solution Cadence Systems, Mentor Graphics, the back cover) and register online at can do for you right now. Synopsys, Synplicity, and more have paid www.xilinx.com/pw2002.

Spring 2002 Xcell Journal 5 Cover Story Programmable Systems The New Era of Programmable Systems The next breakthrough in processing and system design methodology comes from the merger of the most advanced technologies from Xilinx and IBM.

6 Xcell Journal Spring 2002 Cover Story Programmable Systems

by Babak Hedayati throughout multiple industries. Design sumer technologies that seem to pop up on Sr. Director of Product Solutions and Partnerships challenges associated with integration, a daily basis incorporating new features Xilinx, Inc. high speed interfacing, higher perform- from the digital revolution. They target [email protected] ance processing, and new design method- individual niche areas, compete, and often ologies must be solved, and the rapid rate become extinct, just as suddenly as they Over the course of the semiconductor of change in technology demands hard- were brought to market. This extinction is revolution, with the help of Moore’s Law, ware programmability – this time at the often caused by rapidly changing standards FPGAs have grown to densities of 10 system level. and requirements, or by competitive prod- million gates. They have consumed key ucts putting tremendous pressure on cor- Digital Convergence system-level functions such as block porations and their engineering teams. memory, clock management, digitally The convergence of voice, video, data pro- Moving Toward Total controlled impedance matching, embed- cessing, and packet processing both on the Cost Management ded multipliers, 844 Mbps LVDS I/Os, infrastructure equipment and consumer and many other functions. As the densi- products is putting immense pressure on Rapid product extinction makes executives ties increased so did the insatiable hunger corporations and their engineers. They question why their companies are spending for soft IP cores for simple functions, must now incorporate computing, net- so much capital on multi-million dollar complex DSP algorithms, networking working, wireless, and video imaging tech- ASIC NREs (Non-Recurring Engineering protocols, interfaces, and so on. nologies that previously existed stand-alone charges) and design automation contracts – in their respective markets. because today’s economic and technological The advantage gained by increased FPGA conditions often require design changes capabilities – sometimes unbelievable to This digital convergence has been an midway in the development process. Success some – has been adopted by thousands of inevitable reality since the early days of the in today’s marketplace is accomplished by design teams looking to improve their electronics industry, where specialized getting to market first, not by designing for time to market by targeting segments of equipment and devices demonstrated their high volumes and the lowest unit cost – their system to Virtex™-II FPGAs when- true potential as soon as they were con- spending immense amounts in advance on ever possible. Yet few could initially imag- nected with other devices. First came the creating custom ASICS, without a guaran- ine the possibilities of a “programmable telegraph, then the telephone, computers, teed future, is a recipe for failure. system” when Xilinx talked of immersing video, the Internet, storage, wireless, and 300 MHz IBM® PowerPC™ 405 proces- the infrastructure behind it all. Now the Many companies are faced with huge inven- sors into the Virtex-II FPGA fabric and world is incredibly crowded with new con- tories of ASICs and ASSPs that cannot be embedding high-speed multi-gigabit serial I/Os around it. Hundreds of Many immediately saw the value of Resistors Processor Processor ASSP integration for cost reduction, increased performance, and reliability. Others saw ASSP OC-192 the potential for its incredible flexibility POS Integrated FRAMER/ and scalablity for implementing special- Optics Quad MAPPER SSTL3 ized and high-speed interfaces. The idea Transceiver FPGA Translators of extreme hardware parallel processing, Quad and multiple processing on the same SDRAM Transceiver device, enticed many system designers to consider the great possibilities of such a solution. Many engineers expected the next break- Virtex-II Pro Cuts the BOM by > $200 ASSP through in processing and system design Saves 14 in2 Board Space... OC-192 ASSP methodology to come solely from the POS ...Plus the FRAMER/ XCITE masters of the microprocessor world and cost of a pile MAPPER RocketIO leading ASIC vendors – but the break- of devices through has come from the merger of the most advanced technologies from Xilinx Integrated Optics SDRAM and IBM. The need for high-speed communication and increased bandwidth has driven the rapid evolution of technology Figure 1 - Leading edge price/performance through integration and reduction of board size

Spring 2002 Xcell Journal 7 Cover Story Programmable Systems

re-targeted to multiple products to reduce Power PC 405s, XCITE™ controlled In the last two years companies like Xilinx, the risk. Though ASICs are often less expen- impedance technology, and other system- in partnership with Conexant (and the later sive for high volume designs, they incur level features, you get a smaller board size, acquisitions of companies such as much higher overall costs, higher risk, lower overall costs, and faster time to RocketChips), have discovered how to longer development cycles, and less time in market, as illustrated in Figure 1. implement mutli-gigabit serial I/Os in market. It’s time for corporations to evaluate CMOS technology, making it a cost effec- The Ultimate Connectivity Solution the total cost of their development strategy tive method of delivering point-to-point as a whole and avoid falling into the pitfalls For a long time, the original PCI bus was the serial switched interconnections. This means of separating capital investments, develop- industry standard. To increase the band- much higher performance without any side ment costs, production costs, obsolescence width, many designers began to use bridges, effects. Other companies in the silicon costs, and inventory management. continuing with the parallel, shared bus industry, such as ASSP companies and stan- strategy. Then the standard moved to 64-bit dards committees, are now quickly adopting The coming generation of computers and 66 MHz versions, and later to PCI-X run- this strategy to reduce cost, increase reliabil- telecommunications equipment is very dif- ning at 133 MHz. ity, and increase bandwidth, as shown in ferent from prior evolutions of information Figure 2 and Figure 3. technology because it is dramatically revers- The problems with continuing this strategy ing the age-old wisdom of creating specific are obvious. Wider busses require more pins The Processing Revolution devices for each application. Current sys- and higher cost, and moving to higher fre- The quest for higher performance process- tems are integrating computers, cell phones, quencies causes signal integrity issues. Plus, ing is evident in many applications. game systems, cameras, appliances, automo- the shared bus created more overhead and Companies have traditionally turned to biles, offices, and homes. Eventually, we will less bandwidth predictability. Although PCI “farms” of expensive high-performance likely have only a few types of super systems will be used for years to come, today’s per- processors to achieve the performance they remaining that synthesize and extend the formance-hungry applications have already need. In doing so, they have usually faced capabilities of all current systems. moved toward packet switched LVDS-based prohibitive costs along with the massive parallel methodologies such as POS PHY One of the key trends to reduce cost, efforts of managing and partitioning their Level 4, Flexbus 4, RapidIO, Hyper increase performance, and increase the reli- tasks throughout the processor farm. Transport, and others. This requires smarter ability of systems has been through integra- protocols and point-to-point interfacing Hardware oriented companies such as net- tion. However when designers integrated between devices and boards. The move was working, telecom, and wireless infrastructure their systems into custom ASICs, they welcomed because it increased bandwidth. developers have taken the lead by imple- increase inventory risks and require large However, it often resulted in increased clock menting parallel processing in hardware. For initial up front investments. Hence, com- skew and signal integrity issues. example, using Xilinx XtremeDSP™ solu- panies find it difficult to stop midway to change their designs. In addition, smaller companies or start ups find that they must commit the majority of their funding just to develop their platform – and sometimes they have a difficult time getting a large ASIC supplier to entertain their development. A fully integrated system-level solution such as the Virtex-II Pro™ family solves all of these problems. Offering multiple gigabit serial I/Os, the fastest FPGA solution in the world, up to four Figure 2 - The trend towards switched and distributed serial I/O

8 Xcell Journal Spring 2002 Cover Story Programmable Systems

can even make changes to their hardware and software in the field, after the product is in the customers’ hands, to fix bugs or implement new features. New business models can now be developed for programmable system design. The Virtex-II Pro solution provides a standard programmable system platform, fully supported by embedded development tool vendors such as Wind River Systems; EDA companies such as Cadence, Mentor Graphics, and Figure 3 - Virtex-II Pro FPGAs support all connectivity standards Synopsys; and system- level tools companies tions, with a single clock cycle they can what goes into hardware what gets imple- such as Celoxica and The Mathworks – all process massive amounts of multiply accu- mented as software code. This restriction industry leaders and strategic partners to mulate functions (over 600 billion MACs has been the cause of many delayed prod- Xilinx. These partnerships enable a new per second). On the other hand, when com- ucts and products that have been unsuccess- development paradigm for programmable panies have had to deal with multiple small- ful, because of the inability to make adjust- systems design. This overall solution of er tasks, they have devices, software, cores, and partnerships traditionally turned means that companies like yours can now to multiple proces- Types rest a little easier. sors, and optimized Very Large Single of Multiple Tasks Task Requires Parallel Challenges Welcome to the Programmable World the code for process- Processing ing each smaller Types Xilinx and its partners are taking the next task; a technique of step in the evolution of programmable logic Solutions often used in net- by creating a new event – Programmable work processors, as Parallel Processing Using Parallel Processing in Parallel Processors World 2002. Here, you will hear industry shown in Figure 4. Multiple Processors Hardware on Multiple Tasks leaders and visionaries discussing the latest • Complex partitioning • High performance • Specific task focus Now for the first • Significant overhead • Lower cost • Scalable Platform FPGA solutions, including • Low complexity time, through the • Very expensive detailed technical training for the PowerPC, Virtex-II Pro pro- Wind River tools, and others. From imple- grammable system, Figure 4 - Virtex-II Pro FPGAs provide higher performance processing mentation techniques for multi-gigabit seri- designers get both al I/Os to digital signal processing, you will high-performance processing and distributed hear experts from more than 50 companies processing through multiple PowerPC ments for new features or performance discussing this revolution in logic design. processors immersed in the FPGA fabric. optimizations during the design phase. Electronic design automation (EDA) com- Programmable World 2002 will be held With Virtex-II Pro FPGAs, the whole is simultaneously in multiple locations much more than the sum of the parts. panies have partially addressed the problem by developing system-level tools (such as throughout North America and Europe. Enabling a New System behavioral partitioning tools and so on) to You won’t need to travel, but if you do, it’s Development Paradigm make the system-level tradeoffs easier. all free with breakfast and lunch included. Design teams can now make system-level Now, with Xilinx technology, design teams April 17th you can see it all. To get the tradeoffs and optimization throughout the can make tradeoffs and optimizations full details, or to register for the technical design cycle. Traditionally, architecture- throughout the system design; creating a sessions, go to: www.xilinx.com/pw2002. level teams have had to make such tradeoffs more integrated system with higher per- Be sure to reserve your seat now; atten- early in system definition phase – deciding formance and faster time to market. They dance is limited.

Spring 2002 Xcell Journal 9 New Product Virtex-II Pro Platform FPGA Virtex-II Pro FPGAs: The Platform for Programmable The Virtex-II Pro solution heralds a paradigm shift in system architecture by moving design based on zones of Systems Has Arrived programmability to entire system-level programmability.

by Anil Telikepalli Marketing Manager, Worldwide Marketing To achieve that objective, circuit engineers processing systems. The new Virtex-II Pro Xilinx, Inc. and system architects from IBM, FPGAs come in five densities, seven pack- [email protected] Mindspeed, and Xilinx worked together to ages, and 15 combinations. develop this advanced Platform FPGA. At The curtains have been raised! The Virtex-II Virtex-II Pro FPGA Revealed the same time, engineering teams from top Pro™ Platform FPGA solution – the most embedded systems companies, including As a platform for programmable systems, sophisticated silicon and software product Wind River Systems and Celoxica, worked the Virtex-II Pro FPGA is both flexible and ever – is now available for programmable alongside Xilinx software teams to develop scalable throughout all aspects of system system design. Programmable systems repre- the systems software and IP solutions that architecture. By embedding processor cores sent flexible and scalable systems that are bring a new methodology to system design. within the FPGA fabric, the Virtex-II Pro programmable at the architectural level. The architecture provides tight coupling between goal in developing the Virtex-II Pro FPGA The result is the first Platform FPGA solu- high-performance processors and the high- was to revolutionize system architecture by tion capable of implementing ultra-high speed programmable logic. Together, the tightly integrating hardware and software bandwidth SOC (system-on-a-chip) designs two components enable the most optimal functions on a single platform with unprece- that were previously the exclusive domain of yet flexible partitioning of hardware and dented flexibility and scalability. custom ASICs. The Virtex-II Pro presents all software in a programmable system. The the advantages of ASICs – and still retains all Virtex-II Pro FPGA is built upon the lead- the flexibility and low developing Virtex-II™ FPGA architecture with ment cost of program- Rocket I/O™ multi-gigabit transceivers mable logic devices. and embedded IBM PowerPC™ proces- The Virtex-II Pro sors completely immersed into the FPGA solution enables fabric (Figure 1). high performance programmable systems specifically in the areas of wired and wireless networking, storage systems, professional broadcast, embedded systems, and digital signal

10 Xcell Journal Spring 2002 New Product Virtex-II Pro Platform FPGA

Rocket I/O Transceivers toward designing compact optical networking equipment (impossible if you Rocket I/O multi-gigabit transceivers must put in several heat sinks). (MGTs) are based on Mindspeed SkyRail™ CMOS technology. Each full- For example, four Rocket I/O blocks duplex transceiver runs from 622 Mbps to allow 16 printed circuit board (PCB) XC2VP50 3.125 Gbps baud rate and includes the traces to support full-duplex 10 Gbps entire transceiver support circuitry (Figure data rates. This is equivalent to 256 traces 2). The Rocket I/O blocks are the first of typical busses or 68 traces of a high- transceivers embedded in FPGAs to reach a speed parallel bus. Thus, the four Rocket baud rate of 3.125 Gbps. Up to 16 MGTs I/O blocks allow a 16X reduction of PCB can be bonded together to provide Figure 1 - The Virtex-II Pro XC2VP50 device an aggregate data features four IBM PowerPC 405 processors Transceiver Module and 16 Rocket I/O multi-gigabit transceivers rate of 40 Gbps for embedded in the FPGA fabric. Physical Coding Sublayer Physical Media Attachment each of transmitter (PCS) (PMA) and receiver. 32/16/8 bits C F TX+ TXDATA R 8B/10B I Serializer Transmit Encode F Buffer TX- Additionally, Virtex-II Pro Platform Well-designed seri- C O Transmitter FPGAs offer the following features: al transceivers have TX Clock Generator REFCLK Receiver two fundamental 40 – 156.25 MHz • Five family members with 3,168 to Channel Bonding 20X Multiplier requirements that and 50,832 logic cells, and 216 Kb to 3,888 Clock Correction

distinguish them Loop-back Kb of block RAM from others: CRC RX Clock Recovery • 0.13µ , 9-layer copper, low-k technology 32/16/8 bits • Ability to oper- RXDATA Elastic 8B/10B Deserializer Receive RX+ process Buffer Decode Comma Det. Buffer ate at multi-giga- RX- • 3.125 Gbps Rocket I/O multi-gigabit bit rates to sup- serial transceivers based on Mindspeed port emerging SkyRail™ technology, up to 16 per standards Figure 2 - Inside the Rocket I/O block device • Ability to bundle • 300+ MHz PowerPC embedded proces- multiple chan- sor cores based on IBM’s PowerPC 405 nels together for scalable data rate. traces over conventional parallel busses, processor, up to four per device resulting in significant reduction of PCB Each Rocket I/O transceiver consists of complexity and EMI system noise. In • Virtex-II IP-Immersion technology pow- both a digital Physical Coding Sublayer as short, Rocket I/O technology allows ered by system-level features: well as an analog Physical Media higher bandwidth systems than currently Attachment to provide a fully integrated - Flexible SelectI/O™-Ultra technology possible, with cost savings from faster serializer/deserializer function that enables supporting 840 Mbps LVDS I/Os time-to-market, reduced power consump- the entire functionality and performance of - Xilinx Controlled Impedance emerging serial standards (Table 1). Technology (XCITE) capability, Technology Line Speed Historically, serial transceivers have been providing built-in digital impedance analog components built using SiGe or 3GIO 2.5 Gbps matching on all single-ended I/Os GaAs processes. These transceivers gener- Serial ATA 1.5 Gbps - Embedded 18 Kb dual-port block ate enormous quantities of heat – and any InfiniBand 2.5 Gbps RAM resources integration of channels to increase the Gb Ethernet 1.25 Gbps - Embedded 18-bit x 18-bit multiplier data rate was out of the question. blocks However, Xilinx Rocket I/O transceivers 10 GE (XAUI) 3.125 Gbps not only provide multi-gigabit data rates, - DCM (digital clock manager) macros they can also be tied together to increase Serial RapidIO 1.25 Gbps support de-skew and frequency/phase the aggregate bandwidth by using the FibreChannel 1.06 Gbps manipulation built-in channel-bonding capability. This - Bitstream encryption (Triple-DES) for scalability is especially important as data Table 1 - Virtex-II Pro Platform FPGAs support these protocols and baud rates. design protection. rates increase and the industry moves

Spring 2002 Xcell Journal 11 New Product Virtex-II Pro Platform FPGA

tion, smaller PCB size, and ners or develop proprietary

lower component count Hundreds of peripherals of your own. (Figure 3). Resistors Processor Processor ASSP The CoreConnect bus architec- ASSP Ultimate Connectivity OC-192 ture has two main buses, called POS Integrated FRAMER/ the Processor Local Bus (PLB) Optics Quad Virtex-II Pro Platform MAPPER SSTL3 Transceiver FPGA Translators and the On-chip Peripheral Bus FPGAs, equipped with Quad (OPB). These buses can be used Rocket I/O MGTs, support SDRAM Transceiver for interfacing high-speed and emerging serial connectivity low-speed peripherals with the standards – and with Xilinx PowerPC processor respectively. SelectI/O™-Ultra technolo- Saves 14 in2 ASSP Additionally, a third Device OC-192 ASSP gy, these next-generation Board Space... POS

XCITE Control Register (DCR) bus is Platform FPGAs also support FRAMER/ MAPPER RocketIO used for transfers to and from today’s parallel connectivity Integrated general purpose peripheral standards (Table 2). Thus, the Optics SDRAM device registers. Virtex-II Pro FPGA serves as an ultimate connectivity plat- The Virtex-II Pro Platform form to bridge across various Figure 3 - The Virtex-II Pro advantage: reduced PCB board FPGA is also supported by a interface standards in chip-to- space with less complexity and fewer components complete set of embedded soft- chip, board-to-board, or even ware tools for development and The PowerPC 405 core has unique on-chip WAN/MAN/LAN networks. debug. Through an OEM agreement, memory (OCM) controllers that bypass Xilinx is able to provide software tools from In addition to these hardware physical the processor bus for fast, direct access to a Wind River Systems that are customized interface capabilities, the Virtex-II Pro fixed amount of instruction and data mem- for Virtex-II Pro FPGAs. These include: solution provides PowerPC processors and ory implemented in Xilinx SelectRAM™ soft intellectual property (IP) cores to make modules (Figure 4). This is especially useful • Diab™ XE (Xilinx Edition) compiler designing with any protocol easy. for data streaming applications. • SingleStep™ XE software debugger IBM PowerPC Processors The PowerPC processor is supported by • visionPROBE II XE JTAG run control Each IBM PowerPC processor runs at IBM CoreConnect™ technology – a high- hardware connection probe. 300+ MHz and 420 Dhrystone MIPS. bandwidth 64-bit bus architecture that In addition, a suite of GNU (open-code Even though the PowerPC 405 core occu- runs at 100 to 133 MHz. For maximum Linux) tools is also available. pies a small portion of the die area, it pro- flexibility, the CoreConnect architecture is vides tremendous system flexibility. Instead implemented as a soft IP within the Virtex- With the Virtex-II Pro solution, you can of attaching the PowerPC 405 processor II Pro FPGA fabric (Figure 5). You can add use the FPGA fabric for highly parallel pro- next to the FPGA with a bus interface (as CoreConnect peripherals from an extensive cessing and fixed algorithms. You can use certain vendors have attempted), the IP library from Xilinx and third-party part- the PowerPC processor for sequential com- Virtex-II Pro engineering team embedded the processor entirely within the FPGA fabric. Using Xilinx IP Immersion and LAN/MAN/WAN Board-to-Board Chip-to-Chip Active Interconnect technologies, hundreds 10/100 Ethernet PCI 32/33 RapidIO PCI 32/33 POS-PHY L3/L4 of processor nodes are directly connected • • • • • to the FPGA logic and memory array. • 1Gb Ethernet • PCI 64/66 • CSIX • PCI 64/66 • Flexbus 4 Such total immersion gives you the • 10Gb Ethernet • PCI-X 100 • HyperTransport • PCI-X66 & 100 • CSIX utmost flexibility in hardware/software • 1Gb Ethernet PHY • Serial RapidIO • InfiniBand • RapidIO • HyperTransport system architecture. You can efficiently 10GE XAUI Fibre Channel 3GIO 10GE XAUI 3GIO divide complex functions between high- • • • • • speed implementation in hardware and • SONET Standards* • 10GE XAUI high-flexibility implementation in software. This direct-connect configuration • Serial standards enabled by Rocket I/O technology – Virtex-II Pro FPGAs bypasses the bottleneck of using a bus to Table 2 - Virtex-II and • Parallel standards enabled by SelectI/O-Ultra technology – Virtex-II & Virtex-II Pro FPGAs Virtex-II Pro FPGAs offer * SONET compatible, supports data rate only interface between the FPGA and an multiprotocol connectivity. attached/external processor.

12 Xcell Journal Spring 2002 New Product Virtex-II Pro Platform FPGA

tecture, partitioned optimal- I-Side On-Chip Memory (OCM) Metal 9 FPGA Block RAM ly between hardware and Metal 8 software. Metal 7 Metal 6 I-Cache Fetch & Metal 5 (16KB) Decode Price & Performance Leader Timers Metal 4 Metal 4 and Debug Leading-edge systems need Metal 3 PowerPC Metal 3 MMU Logic Metal 2 Immersed Metal 2 (64 Entry TLB) high bandwidth serial I/O, into FPGA Metal 1 Metal 1 which has only been achiev- Poly Poly D-Cache Execution Unit (16KB) (32 x 32 GPR, JTAG able by interfacing an ALU, MAC) Processor Local Bus (PLB) Processor Instruction Trace FPGA to an external serial Silicon Substrate transceiver by means of D-Side On-Chip Memory (OCM) hundreds of pins. Similarly, FPGA Block RAM high-performance systems Figure 6 - Hard IP cores are deeply embedded and actively connected within Figure 4 - Inside the PowerPC 405 processor typically require one or the FPGA fabric more processors on the Memory High-Speed Low-Speed board, creating even more Interface Peripheral Peripheral cant benefits, specifically in software engi- connectivity problems and neering productivity: PCB complexity. Block I/O RAM Interfaces • Embedded processors can be used for By immersing multi-giga- PLB OPB rapid system pre-production to facilitate PowerPC bit transceiver blocks and accelerated software development. A pre-

OPB Bridge processor cores within PLB Arbiter OPB Arbiter liminary hardware platform can be built Hard-IP the FPGA fabric (Figure quickly by emulating a C-based algorithm Soft-IP 6), the Virtex-II Pro CoreConnect bus architecture using the embedded processors. This cre- Platform FPGA delivers ation of a preliminary hardware platform the best price and perform- Figure 5 - Hard and soft IP cores allows software development to start ance. Integrating proces- much earlier in the design process, com- sors and transceivers within puting, exception handling, and control pared to current practice. the FPGA fabric lowers costs and raises functions. The Rocket I/O serial trans- performance by: • Software debugging can be performed at ceivers and SelectI/O-Ultra parallel tech- hardware speeds while the hardware imple- nologies enable optimal data access into • Saving PCB space mentation continues to be speed-opti- and out of the Virtex-II Pro FPGA. • Simplifying PCB complexity mized. Xilinx ChipScope™ Pro on-chip On-Demand Architectural Synthesis • Requiring fewer components verification tools provide in-system observ- Architectural synthesis is a combination of ability into both the FPGA hardware and • Eliminating complex device interconnec- the processor bus transactions. tools and technologies that allows designers tivity issues to specify high-level requirements for design- Conclusion ing their systems. In other words, architec- • Reducing overall system power con- The Virtex-II Pro Platform FPGA solution tural synthesis is a tool-based partitioning of sumption encompasses the following: hardware and software. • Using XCITE digitally controlled impedance technology to do away with external • Rocket I/O transceivers and IBM In order for architectural synthesis to work, termination resistors PowerPC processors immersed and both the hardware and software components embedded into the high performance • Enabling optimal system partitioning of the system must be tightly integrated. Virtex-II Pro FPGA fabric Virtex-II Pro Platform FPGAs enable on- between hardware and software. demand architectural synthesis with tremen- • Intellectual property solutions, including A New Development Paradigm dously flexible, scalable, and high-bandwidth soft peripherals and connectivity cores features. You can perform architectural syn- By tightly integrating flexible and scalable • Complete design resources, including thesis anytime in the product cycle – during high-performance programmable logic development tools and kits system design and debug phases, or even with the PowerPC processor, the Virtex-II after the product has shipped. With abun- Pro Platform FPGA fundamentally To find out more about this revolutionary dant resources of hardware and software, changes the way systems are designed. The next-generation Platform FPGA for pro- Virtex-II Pro FPGAs give you the flexibility Virtex-II Pro solution facilitates a new par- grammable systems, go to www.xilinx.com/ and scalability for fine-tuned system archi- adigm in system development with signifi- virtex2pro.

Spring 2002 Xcell Journal 13 Xilinx News Product of the Year Virtex-II FPGAs – Product Of The Year Xilinx recently received the Product of the Year Award from Electronic Products magazine – and we were the only programmable logic supplier to receive this award.

by Xilinx Staff designers develop the next-generation of The Virtex-II family allows unlimited design complex high-performance digital appli- changes throughout the development and For 26 years, Electronic Products has held cations such as data communications and production phases for optical networks, giga- an annual contest to choose the most out- DSP systems. Characterized by high bit routers, wireless cellular base stations, standing products introduced each year. The logic integration, fast and complex rout- modem arrays, and video broadcast systems. editorial board at the magazine considers ing of wide buses, and extensive require- Capable of handling designs from 40,000 to thousands of product introductions based ments for pipeline and FIFO memory, 10 million system gates, Virtex Series FPGAs on significant advances in technology or its these new systems exceed the capabilities feature an interconnect architecture for opti- application, a decided innovation in design, of current programmable logic devices, mizing routing, and an advanced memory or a substantial gain in price-performance which lack the gate capacity, memory, array with up to 4.5 Mbits of on-chip mem- benefits. As usual, picking winners was routing resources, performance, and ory. An additional feature is the industry’s made difficult by the many impressive prod- architecture flexibility that is required to first digitally controlled impedance technolo- ucts announced during the year. fully support these designs. The gy, which maintains constant impedance Electronic Products’ editors judged that even with temperature and voltage fluctua- The Xilinx Virtex™-II FPGA family was the Xilinx Virtex-II series (see Electronic tions – eliminating hundreds of termination recognized as the FPGA platform to address Products, May 2001) also solves the resistors, saving board space, increasing relia- next-generation designs. “Programmable problems resulting from signal integrity, bility, and lowering costs. logic has heretofore been limited to relative- system timing, EMI, and security issues ly simple computational tasks and glue For more information on the winners, go to in these complex systems. logic functions,” said David Suchman, www.electronicproducts.com. Digital IC editor at Electronic Products. “Now, for the first time, a programmable “Programmable logic has heretofore been limited to relatively simple platform is available from Xilinx to enable rapid development of today’s technically computational tasks and glue logic functions. Now, for the first time, a programmable challenging applications.” platform is available from Xilinx to enable rapid development of today’s technically The ever-increasing requirements for higher performance and system-level fea- challenging applications.” David Suchman, Digital IC editor at Electronic Products. tures are bringing new challenges as –

14 Xcell Journal Spring 2002 DESIGN. TOGETHER.

At Cadence we offer a different perspective on the complex world of electronic design. It’s an approach that focuses all our resources—from industry-leading technologies and services to strong partnerships and open collaboration—toward complete customer success.

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Visit us at the Embedded Systems Conference and Xilinx Programmable World 2002 Product Focus PowerPC

by Anthony Marsala IBM The PowerPC™ Architecture is a Reduced Instruction Set Computer (RISC) architecture, with over two hundred defined instruc- TheThe PowerPC PowerPC tions. PowerPC is RISC in that most instructions execute in a single-cycle and typically perform a single operation (such as loading storage to a register, or storing a register to memory). This article will focus solely on 32- bit implementations, which are the most Architecture:Architecture: widely available today. The PowerPC architecture employs a layered approach, in that it is broken up into three levels or “books”. By segmenting the architecture in this way, code compatibility can be AA Programmer’sProgrammer’s ViewView maintained across implementations while leaving room for implementations to choose levels of complexity for price/performances tradeoffs. The three levels are broken up from An introduction to the PowerPC programming model. the most general and common across implementations to the most operating system specific. The levels are: • Book 1. User Instruction Set Architecture – This level defines the base set of instructions and registers that should be common to all PowerPC implementations. • Book 2. Virtual Environment Architecture – This level defines additional user-level functionality that is outside the normal application software requirements. Areas include cache management, atomic operations, and user-level timer support. • Book 3. Operating Environment Architecture – This level defines privileged operations typically required by an operating system. Areas include memory management, exception vector processing, privileged register access, and privileged timer access.

Editor’s note: This article is reprinted with permission from IBM. It was originally a two-part series that ran in the April, 2001, IBM PowerPC Processor News. You can view the original articles, and find other useful information at: www-3.ibm.com/chips/products/ powerpc/newsletter/apr2001/design-h-t.html.

16 Xcell Journal Spring 2002 Product Focus PowerPC

Deviations from the original PowerPC while the 400 family provides more robust certain privileged registers and instructions Architecture offer flexibility to allow for support for little endian storage. by placing itself in user (also called prob- enhancements that may come over time. In lem-state) mode. This protection limits Book E is endian-neutral, as the Book E addition, IBM has defined its own Virtual application code from being able to modify architecture fully supports both accessing Environment and Operating Environment global and sensitive resources, such as the method. levels for its PowerPC 400 family of caches, memory management system, and embedded controllers. Registers timers. Mode switching is controlled via the Machine State Register. Book E – A New Definition Classic PowerPC registers are broken into two classes: special-purpose registers (SPRs) • The Instruction Address Register (IAR) is A new PowerPC architecture update has and general-purpose registers (GPRs). IBM’s known to programmers as the program been developed. Called “Book E”, it com- PowerPC 400 family and Book E also define counter or instruction pointer. It is the bines the original three architecture levels a third class of registers, called device control address of the current instruction. This is into one new specification. This new spec- registers (DCRs), to address peripheral regis- really a pseudo-register, as it is not directly ification also streamlines the definition of ters outside of the processor core in an available to the user. The IAR is primarily 64-bit implementations and eliminates embedded controller implementation. The used by debuggers to show the next non-substantive differences between IBM three classes are explained below. instruction to be executed. and Motorola implementations. The new standard maintains 100% code compatibil- SPRs • The Processor Version Register (PVR) is ity with Book 1 instructions and registers, SPRs give status and control of resources useful for code common across multiple while formally defining software-based within the processor core. Table 1 shows dif- processors that must make decisions based memory management, a two-level inter- ferent types of SPRs and their purpose. on a specific processor. rupt hierarchy, and user-extendible instruc- Where a single register exists, the SPR name User-Mode SPRs tion space for auxiliary processors. All of is listed in parenthesis. these enhancements address the needs of There are four SPRs available in user-mode embedded systems. Supervisor vs User-Mode SPRs that are important to understand: To distinguish between the original architec- When the processor is first initialized, it is • The Link Register (LR) is a 32-bit register ture, the IBM embedded definitions, and in supervisor (also called privileged) mode. that contains the address to return to at the Book E, the original architecture will be In this mode, all processor resources, end of a function call. Certain branch referred to as the “classic” architecture for the including registers and instructions, are instructions can automatically load the LR remainder of this article. accessible. The processor can limit access to to the instruction following the branch. Storage Model SPR Register Type Access Mode Purpose The 32-bit PowerPC architecture has native support for byte, halfword (16-bits), and Count (CTR) User Branching and Loop Control word (32-bit) data types. Also, PowerPC Link (LR) User Subroutine Branching implementations can handle string operations for multi-byte strings up to 128 bytes Save/Restore Supervisor Interrupt Context Save in length. The 32-bit PowerPC implementa- Debug Supervisor On-chip Debug Capabilities tions support a 4 GB address space (232). All storage is byte addressable. For misaligned Timers User (read) Timing Facilities data accesses, alignment support varies by Supervisor (write) product family, with some taking exceptions Interrupt Vector Prefix Supervisor Locates Interrupt Addresses and others handling the access through mul- Exception Supervisor State information where exceptions occur tiple operations in hardware. Endianness Storage Attribute Control Supervisor Controls Storage Attributes (W,I,G,LE) Classic PowerPC and the IBM PowerPC Processor Version (PVR) Supervisor Identifies PowerPC Implementation 400 family are primarily big-endian General Purpose (SPRGn) Supervisor Used by Operating Systems machines, meaning that for halfword and Integer Exception (XER) User Carry Bit, Overflow, String Lengths word accesses, the most-significant byte (MSB) is at the lowest address. Support for MMU Supervisor Instruction/Data Translation Control little endian varies by implementation. Classic PowerPC had minimal support, Table 1: SPR registers

Spring 2002 Xcell Journal 17 Product Focus PowerPC

The blr instruction moves the program instruction with one exception: In certain Deciphering an Instruction counter to the address in the LR. instructions, GPR0 simply means “0” and For 32-bit implementations, all instruc- no lookup is done for GPR0’s contents. • The Fixed Point Exception Register tions are 32 bits (4 bytes) in length. Bit (XER) contains overflow information Instructions numberings for PowerPC are opposite of from fixed point arithmetic operations. It most other definitions; bit 0 is the most Table 2 lists different instruction cate- also contains carry input to arithmetic significant bit, and bit 31 is the least sig- gories, and the types of instructions that operations and the number of bytes to nificant bit. Instructions are first decoded exist in that category. transfer during load and store string instructions lswx and stswx. • The Count Register (CTR) contains a loop Instruction Category Base Instructions counter that is decremented on certain Data Movement load, store branch operations. Also, the conditional Arithmetic add, subtract, negate, multiply, divide branch instruction bcctrx branches to the value in the CTR. Logical and, or, xor, nand, nor, xnor, sign extension, count leading zeros, andc, orc • The Condition Register (CR) is grouped Comparison compare algebraic, compare logical, compare immediate into eight fields, where each field is 4 bits Branch branch, branch conditional, branch to LR, branch to CTR that signify the result of an instruction’s operation: Equal (EQ), Greater Than Condition rand, crnor, crxnor, crxor, crandc, crorc, crnand, cror, cr move (GT), Less Than (LT), and Summary Rotate/Shift rotate, rotate and mask, shift left, shift right Overflow (SO). Cache Control invalidate, touch, zero, flush, store, dcread, icread Machine State Register (MSR) Interrupt Control write to external interrupt enable bit, move to/from machine state register, MSRs represent the state of the machine. It return from interrupt, return from critical interrupt is accessed only in supervisor mode, and contains the settings for things such as Processor Management system call, synchronize, eieio, move to/from device control registers, memory translation, cache settings, inter- move to/from special purpose registers, mtcrf, mfcr, mtmsr, mfmsr rupt enables, user/privileged state, and MMU Control TLB search, TLB read, TLB write, TLB invalidate all, TLB synchronize floating point availability. Exact control bits vary by implementation. MAC Unit multiply low/high halfword and accumulate/subtract The MSR does not readily fit into the Table 2 - Instruction categories SPR/DCR/GPR classification, as it contains its own pair of instructions (mfmsr / by the upper 6 bits, in a mtmsr) to read and write the contents of AND OR Exclusive OR Rotate and Mask Shift Misc. the MSR into a GPR. field called the primary and or xor rlwimi slw cntlzw opcode. The remaining DCRs 26 bits contain operands and. or. xor. rlwimi. slw. cntlzw. DCRs are similar to SPRs in that they give and/or reserved fields. status and control information, but DCRs andi. ori xori rlwinm sraw Operands can be registers or immediate values. are for resources outside the processor core. andis. oris xoris rlwinm. sraw. extsb DCRs allow for memory-mapped I/O con- Arithmetic Instructions trol without using up portions of the 32-bit rlwnm srawi extsb. Many instructions exist memory address space. nand nor egv rlwnm srawi. for performing arith- GPRs nand. nor. egv. srw extsh metic operations, includ- The User Instruction Set Architecture srw. extsh. ing add, subtract, nega- (Level 1) specifies that all implementations tion, compare, multiply andc orc have 32 GPRs (GPR0 - GPR31). GPRs are and divide. Many forms the source and destination of all fixed-point andc. orc. exist for immediate val- operations and load/store operations. They ues, overflow detection, also provide access to SPRs and DCRs. and carry in and out. They are all available for use in every Table 3 - Power PC logical instructions Multiply and divide

18 Xcell Journal Spring 2002 Product Focus PowerPC

instruction performance varies among Synchronization Instructions context, such as memory translation, endi- implementations, as these are typically anness, cache coherency, etc. Instruction Commonly misunderstood PowerPC multi-cycle instructions. pipelines are flushed when an isync is per- instructions are those that perform synchro- formed, and the next instruction is fetched Logical Instructions nization. These instructions include: in the new context. This instruction is use- Table 3 lists PowerPC logical instructions. • Enforce In/Order Execution of I/O (eieio) ful for self-modifying code. – This instruction is for data accesses to Looking at the AND instruction, The “i” Memory Management form means that a 16-bit immediate is used guarantee that loads and stores complete for the AND, the “is” form means that a with respect to one another. Since Memory management is used to translate 16-bit immediate is used in the upper 16- PowerPC defines a weakly ordered storage logical (effective) addresses to physical (real) bits of the AND. For all “.” forms, the model in which loads and stores can com- addresses. Memory management units CR[CR0] is updated as previously plete out of order, this instruction exists to (MMUs) are also used to control storage described. PowerPC has the ability to per- guarantee ordering where necessary. attributes, such as cacheability, cache write- form a 32-bit rotate-and- though/write-back mode, memory coheren- combine with a mask in a cy, and guardedness. There are single cycle. In the miscella- two primary approaches; one neous column are instruc- defined by PowerPC classic in tions to count the leading the 600/700 family of proces- zeros in a register, and sign sors and another used by the extension instructions. 400 family and Book E specification. In both cases, the archi- Load/Store Instructions tecture defines a unified MMU, which has traditionally All loads/stores are per- been implemented as inde- formed using the GPRs. pendent instruction and data Instructions exist for byte, MMUs, enabled via the MSR halfword, and word sizes. [IR,DR] bits, respectively. Special instructions include: Below is an overview of the • Multiple-word load/stores two approaches. (lmw / stmw), which can PowerPC Classic MMU operate on up to 31, 32- bit words The PowerPC Classic MMU was designed primarily for • String instructions, which demand page operating sys- can operate on up to 128- tems such as UNIX or byte strings MacOS. There are two translation mechanisms, one for • Memory Synchronization block address translation, and instructions lwarx (Load another for page tables. Block Word and Reserve address translation is per- Indexed) and stwcx. • Synchronize (sync) – This instruction guar- formed using eight pairs (upper and lower) (Store Word Conditional Index) are used antees that the preceding instructions com- of address translation registers, four for to implement memory synchronization. plete before the sync completes. This instruction addresses (IBATU/L 0-3), and lwarx performs a load and sets a reserva- instruction is useful for guaranteeing four for data accesses (DBATU/L 0-3). The tion bit internal to the processor and hid- load/store access completion. For example, BAT registers define page sizes ranging from den from the programming model. The a sync may be used when writing memory 128KB to 16MB. associated store instruction stwcx. per- mapped I/O registers to a slow device forms a conditional store only if the reser- For systems requiring more translations than before making further access to the device. vation bit is set and thereafter clears the are found in the allocated BAT registers, page reservation bit. CR[CR0]EQ is set to the • Instruction Synchronize (isync) – This table translation is provided. A 32-bit effec- state of the reservation bit at the start of instruction provides ordering for all effects tive address is translated to a 52-bit virtual the instruction so that software can deter- of all instructions executed by the proces- address, and is then translated into a physical mine if the write was successful. sor. It is used to synchronize the instruction address. One of 16 segment registers (SR0-

Spring 2002 Xcell Journal 19 Product Focus PowerPC

SR15) provide virtual address and protection Register 0 (SRR0) is loaded with the interrupt vectors are possible – for the information. Page Table Entries (PTEs) pro- address of where processing should resume 400 family, the upper 16 bits of the vided physical address and page protection after the exception, and the machine state exception vector is contained in the information. The architecture allows for register is saved to SRR1. SRR0 may be Exception Vector Prefix Register (EVPR). implementations to provide translation- loaded with the current IAR or in some For Book E, all 16 exceptions can have lookaside buffers (TLBs) to speed the trans- cases the next instruction. Interrupt vec- the upper half of the exception vector lation process, but does not define them. The tors are located at either a high address mapped to a different location through page-tables are typically programmed by the (0xFFFn_nnnn if MSR[IP=1] or low the use of 16 Interrupt Vector Prefix operating system and their discussion is address (0x000n_nnnn if MSR[IP=0]), Registers (IVPR0-15). beyond the scope of this article. depending on the instruction prefix bit in Stack the MSR. The interrupt type determines 400 Family/Book E MMU the lower 5 bits of the vector. When pro- The PowerPC architecture has no notion of The Book E carries on the idea of a flexible cessing is completed, an rfi instruction is a stack for local storage. There are no push MMU structure for embedded systems. executed to restore the IAR and MSR to or pop instructions and no dedicated stack Page sizes are programmable; a page can be the saved values in SRR0 and SRR1. pointer register defined by the architecture. large (up to a terabyte in the Book E archi- However, there is a software standard used 400 Family and Book E Exception tecture) to simplify software and minimize for C/C++ programs called the Embedded Vector Processing the number of entries, or as small as 1KB, Application Binary Interface (EABI) which to avoid wasting memory space. In addi- Both the IBM 400 family and Book E defines register and memory conventions tion to normal protection and translation define a two-level interrupt hierarchy: a for a stack. The EABI reserves GPR1 for a mechanisms, endianness is defined by a non-critical interrupt class, and a critical stack pointer, GPR3-GPR7 for function page attribute. TLB misses result in an interrupt class. The non-critical class reg- argument passing and GPR3 for function exception; it is under software control to isters work as previously described for return values. Assembly language programs handle the page miss algorithm. A TLB PowerPC classic. For critical interrupts, wishing to interface to C/C++ code must search instruction, tlbsx, assists in search- the IAR and MSR are saved to separate follow the same standards to preserve the ing the entire TLB array in a single cycle. registers (SRR2 & SRR3, respectively for conventions. the 400 family, and CSSR0 & CSSR1 for Interrupts Caches Book E). When a critical exception is The PowerPC architecture provides a completed, an rfci instruction is executed The PowerPC architecture contains cache minimal hardware scheme for saving state to properly restore the machine. By hav- management instructions for both user- on interrupts. The only registers that are ing a dual-level interrupt scheme, level and supervisor-level cache accesses. saved are the IAR and MSR. Interrupt non-critical interrupts can be more Cache management instructions are found enable bits are disabled for the interrupt easily debugged. More than two sets of in Table 4 below. type that occurred in order to prevent a second interrupt from occurring before saving the context. Software must save all Instruction Mode Implementation Function necessary registers – these typically dcbf User All Flush Data Cache Line include all user-mode registers and possi- dcbi Supervisor All Invalidate Data Cache Line bly certain supervisor mode SPRs. Exception-state saving is typically per- dcbst User All Store Data Cache Line formed by an operating system, but note dcbt User All Touch Data Cache Line (for load) that for small exception vectors, time can be saved by only saving registers that dcbtst User All Touch Data Cache Line (for store) would otherwise be corrupted. Operating dcbz User All Zero Data Cache Line systems must take a more universal approach and save all registers that may be dccci Supervisor IBM 4xx Data Cache Congruence Class Invalidate necessary, even if some wind up not being icbi User All Invalidate Instruction Cache Line touched by a particular exception handler. icbt User 4xx / Book E Touch Instruction Cache Line PowerPC Classic Exception Vector Processing iccci Supervisor IBM 4xx Instruction Cache Congruence Class Invalidate A single interrupt hierarchy is defined. When an interrupt occurs, Save/Restore Table 4 - Cache management instructions

20 Xcell Journal Spring 2002 Product Focus PowerPC

Care should be taken when porting cache the 400 family) with an auto-reload boot up sequences and device drivers, manipulation code to a different capability, a fixed-interval timer (FIT), but also may include floating point PowerPC implementation. Although and a watchdog timer (WDT) for system code (including long long types). Keep cache instructions may be common across hang conditions. them well documented as to assump- different implementations, cache organi- tions and dependencies. Debug Facilities zation and size may likely change. For • Use the PVR, but only when appropri- example, code that makes assumptions Debug facilities vary greatly between ate. Common code across minor varia- about the cache size to perform a flush implementations. Original PowerPC 600 tions of implementations is good, and may need to be modified for other cache family parts had only one instruction the PVR can be used for decision mak- sizes. Also, cache initialization may vary address breakpoint. PowerPC 700 family ing. But in the case where major modifi- between implementations. Some provide parts have added a single data address cations are necessary (for example, 7xx hardware to automatically clear cache breakpoint. PowerPC 400 family parts versus 4xx MMU code), separate code tags, while others require software loop- have much more robust debug capabilities, bases are recommended. ing to invalidate cache tags. including multiple instruction address Self-Modifying Code breakpoints, data While it is not a recommended practice to address breakpoints, write self-modifying code, sometimes it is and data value com- absolutely necessary. The following pares. Other features sequence shows the instructions used to may include break- perform a code modification: point sequencing, counters, ranges, and 1. Store modified instruction. trace capabilities. 2. Issue dcbst instruction to force new Maintaining Code instruction to main store. Compatibility 3. Issue sync instruction to ensure DCBST PowerPC users who is completed. expect to program for 4. Issue icbi instruction to invalidate more than one imple- instruction cache line. mentation typically ask for tips on main- 5. Issue isync instruction to clear instruc- taining code compat- tion pipeline. ibility. The following 6. It is now OK to execute the modified are some suggestions instruction. to help minimize porting problems: Timers • Use C code when- Most implementations have provided a 64- ever possible. bit timebase that is readable via two 32-bit Today’s C compil- registers. The amount the timer increments ers can produce varies across families, as well as the SPR code that is compa- numbers and instructions to access the rable in perform- timebase. Therefore, care should be taken ance to hand- when porting timer code across implemen- assembly coding in tations. Additional timers may also vary, Summary many cases. C code, being Book I code, but most provide at least one kind of decre- will guarantee code portability. menting programmable timer. This completes an introduction to the • Also, try not to embed processor-specif- PowerPC programming model. IBM hopes Book E Timers ic assembly instructions in C, as they’ll you have found this of value, and that it Both the IBM 400 family and Book E be harder to find. Separate processor- adds to the success of your development define the following timers in addition to specific code that is known to contain programs. For more information, go to: the timebase: a 32-bit programmable device dependent registers or instruc- www-3.ibm.com/chips/products/powerpc/ decrementer (DEC in Book E, PIT for tions. These are typically things like newsletter/

Spring 2002 Xcell Journal 21 Perspective PowerPC IBM’s New PowerPC Strategy Roadmap It’s exactly what you’d expect from IBM.

Editor’s note: This article is reprinted with permission from IBM. It originally ran in the April, 2001, IBM PowerPC Processor News. You can view the original article at: http://www-3.ibm.com/chips/products/ powerpc/newsletter/apr2001/lead.html

by Kalpesh Gala and Mike Vowell Ethernet. The goal of this strategy is to ket opportunities evolve for higher per- IBM assure the continuation of a product portfo- formance and/or lower power devices, It is not by accident that ideal targets for lio heritage of being core-based, power-effi- IBM will be poised to address these seem- IBM PowerPC™ technology include wired cient, scaleable, and software transparent. ingly insatiable needs. and wireless networking, storage, and pervasive computing applications. It’s all part of a The RapidIO Interconnect Architecture, designed to be compatible with most popular integrated communication master strategy to focus both today’s and processors, host processors, and networking digital signal processors, is a high performance, packet-switched, tomorrow’s industry leading technology on PowerPC products – to meet the perform- interconnect technology. It addresses the high-performance embedded industry’s need for reliability, increased ance, power, and price needs of these ever- bandwidth, and faster bus speeds in an intra-system interconnect. The RapidIO interconnect allows chip-to-chip dynamic and diverse applications. and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond. The focus of IBM’s strategy centers upon both technology and design expertise. Underlying this focus is a strong and long- The melding of IBM’s advanced technol- IBM’s PowerPC cores, microprocessors, term commitment to leveraging the PowerPC ogy, PowerPC products, and SoC capabil- and integrated products meet the unique architecture and designing with standard ity will establish a hallmark in the battle needs of an increasingly diverse market- interfaces, such as RapidIO™, PCI/X, and for mindshare and marketshare. As mar- place. PowerPC chips offer state of the art

22 Xcell Journal Spring 2002 Perspective PowerPC

technology in a variety of configurations to bit capabilities, increase flexibility, and and power needs of next-generation appli- provide the optimal mix of performance, address the unique demands posed by cations. And nowhere will the infusion of power, functionality, and size. And because embedded systems. Book E is a new defi- new technology be more appreciated than of our core-based design philosophy, IBM nition of the PowerPC architecture, one in the relatively new “pervasive comput- customers can quickly and easily differenti- that maintains compatibility with appli- ing.” This includes handheld and embed- ate their products in the marketplace, and cations developed for the original ded products such as smart phones and still maintain flexibility and software trans- PowerPC architecture. Internet appliances for business profession- parency across generations of devices. als and consumers. In this arena, both What’s technology got to do with it? “high performance” and “low power con- Almost everything. It’s what boosts per- sumption” are of utmost importance. To IBM has been a leader in awarded patents formance... throttles power consumption... continue meeting this challenge, IBM is for many years, largely as a result of IBM and enables smaller devices. In a nutshell, focusing its technology resources on technology is a key ingredient to the ever- PowerPC embedded processors that will Microelectronics contributions. Among the more elusive faster, smaller, and cheaper semi- distinguish themselves by their enviable recent of these contributions are several dozen conductor solution. power/performance ratios as well as their high integration of critical IP. patents directly related to three chip breakthroughs Today’s copper process, silicon-on-insulator, and Low-K Dielectric technologies have fos- Conclusion – silicon germanium (SiGe), silicin-on-insulator tered higher levels of performance and lower As a chief architect of the PowerPC power dissipation than were previously (SOI), and Low-K Dielectric. Architecture, IBM has been at the forefront attainable. This elevation of performance is in the evolution of microprocessor design, currently being realized in IBM’s highest Just as IBM led the industry with its semiconductor technology, and SoC performance servers and workstations for advances in the industry. IBM likes its posi- copper process technology, these new process data processing and electronic commerce tion as a pioneer and industry leader – and through IBM’s stand-alone and system-on- technologies will be the catalyst for even has no desire to relinquish its position. You chip (SoC) processors. greater performance and low-power advances are invited to meet IBM at any of its mile- The application of new process technolo- stones, as it advances toward an ultrascalar, in the semiconductor industry. gies is crucial to the development of proces- 2+ GHz-processor engine. It’s exactly what sor engines that will meet the performance you would expect from IBM.

Key to enabling a high level of flexibility is the IBM CoreConnect™ on-chip bus IBM PowerPC Strategic Roadmap architecture, which is becoming a defacto Networking • Consumer • Server • Storage industry standard. CoreConnect provides a standardized method for assembling pieces 2+ GHz Ultrascalar of chip designs from diverse suppliers to Enhanced PowerPC Architecture Switched CoreConnect facilitate an open SoC design process that New High-Speed Interface 1+ GHz encourages the development of reusable IP. Multicore Superscalar SMP Capable Currently, this bus structure is licensed by 7xx Microprocessors Integrated SIMD Engine RapidIO tions n-way Crossbar CoreConnect over 40 IP providers, and is the basis for Solu numerous IBM standard, application spe- 4xx System-on-Chip Devices Up to 700 MHz Low-Power Superscalar On-chip 1.2 Cache cific, and custom devices. Forthcoming Crossbar CoreConnect enhancements include higher bandwidth Up to 500 MHz Superscalar Shipping PowerPC Book E – 32-bit and crossbar functionality, which will PCI-X – 64-bit/133 MHz Performance/Bandwidth CoreConnect – 128-bit/166 MHz Planned* marry well with our next-generation CPU DDR Support Up to 300 MHz cores and our planned addition of per- Scalar/Superscalar PowerPC – 32-bit Next Generation PCI – 32-bit/66 MHz formance-enhancing IP like RapidIO and CoreConnect – 64-bit Low-K – Dielectric .13 – .10 µm SDRAM Support high-speed serial ports. Silicon on Insulator .18 – .13 µm Copper .22 – .18 µm Enhancing IBM’s strategy is a commit- Aluminum .25 µm ment to the PowerPC architecture. The 1999 Process Technology Innovation 200X latest enhanced version, called PowerPC *Subject to change without notice Book E, has been refined to provide 64-

Spring 2002 Xcell Journal 23 New Products Development Tools

SPECCTRAQuest MGT Design Kit Pre-configured circuits in the design kits are ready to simulate for both typical MGT Get up to chip-to-chip and backplane PCB interfaces. There’s no time wasted hunting for models, testing and correlating them, or figuring out how to connect them together. It has all been done for you. And because the simulation Multi-Gigabit environment is graphical, adapting the circuits for your unique application is as simple as dragging and dropping. Better yet, the models of the active Rocket I/O MGT circuitry are transistor-level sili- Speed with the con models that have been correlated by Xilinx to match both the actual silicon design and empirical data. This ensures that your system implementation is designed with the most advanced and accurate mod- SPECCTRAQuest els available. Add to that fully coupled frequency-dependent lossy package, PCB trace, and connector models, and you’re ready to carefully characterize the signal integrity and degradation issues that are Design Kit inherent in this type of design. Figure 1 shows a pre-configured simulation drawing for chip-to-chip applications. Learn how to implement Rocket I/O multi-gigabit Although this is actually a 500+ node simulation, it has been simplified through the use serial transceivers in the new Virtex-II Pro Platform FPGA. of subcircuits and black box models so it can be more easily modified. Just point and click to change trace parameters, physical connections, or other aspects of the circuit. by Donald Telian high-speed FPGA into your system of Technologist When your simulations are done and it’s printed circuit boards (PCBs)? Cadence Design Systems time to layout your PCB, the MGT kit has [email protected] In an effort to avoid multi-gigabit sample footprints and constraint files to headaches, Xilinx and Cadence Design ensure a successful layout. It is essential to Mark Alexander Systems have assembled bind all high-speed constraints into your Product Application Engineer SPECCTRAQuest™ Xilinx, Inc. MGT Design Kits to [email protected] help you implement the With the introduction of the new Virtex-II new Rocket I/O MGTs Pro™ FPGAs, high-speed Rocket I/O™ effectively in your sys- serial transceivers are ready to find their tem. Whether you need to way into hundreds of new applications. Are craft a custom MGT interface you ready? What used to be confined to a and develop your own few exotic chips, laden with pages and PCB/backplane/cabling guide- pages of design and implementation guidelines, or you simply need to lines, is now available to everyone. Xilinx apply your MGTs in a stan- has made it possible to integrate multi- dard configuration, the kit gigabit transceivers (MGTs) into your gets you moving towards a Figure 1 - Example of FPGA, but how will you integrate that solution within minutes. chip-to-chip simulation topology

24 Xcell Journal Spring 2002 New Products Development Tools

MGT Design & Implementation Flow Obtain SPECCTRAQuest With both the SPECCTRAQuest software & Xilinx and MGT design kit in place, you’re ready to Design Kit exercise the advanced, high-speed design flow shown in Figure 2 to ensure your MGTs are Layout Constraint- implemented correctly. Pre-Route Post-Route Constraint Driven Simulation Simulation Derivation High-Speed The flow begins by configuring a simulation Analysis Verification & Capture PCB Layout of your unique application. Use the pre- configured topologies in the design kit as a starting point. Simulate your application Manufacture pre-route by sweeping through all the imple- Assemble mentation options and manufacturing Figure 2 - High-speed PCB design flow Test PCB tolerances to ensure that the multi-gigabit signals are transmitted and received within PCB database to automate and properly con- These measurements can be sorted so you tolerances. Use the test patterns and post-pro- strain the layout process. If you don’t bind can quickly select the best configuration. cessing tools in the kit to help with this phase. your constraints, your layout, post-layout After you have determined the best Once an acceptable solution is found, cap- simulation, and actual system behavior will implementation configuration, you can ture the layout constraints in electronic not be as clean as you would want. use Cadence’s powerful constraint man- topologies that can be bound into the layout To help you along the learning curve associ- agement (CM) tool to electronically cap- process. Once again, you can use the kit ated with designing multi-gigabit links, the ture and manage your layout constraints. examples to learn how. Perform constraint- kits also contain tutorial “movies” you can The CM tool interacts with the other driven layout, and then do post-layout sim- run on your PC to clearly illustrate how to Connected Team Design Tools (including ulation on the routed nets to verify that use the various aspects of the kit throughout Concept HDL, Allegro, SPECCTRA™, signal transmission is still within tolerance. your design process. and SPECCTRAQuest) to enable your If the layout constraints were applied and whole design team to work concurrently followed, this will be a simple verification SPECCTRAQuest’s Features and share data. step. If a problem is found, the differential SPECCTRAQuest is an integrated net can be extracted to an electrical view to design tool that allows you to include more easily identify the cause of failure, as both your MGT silicon models and shown in Figure 3. PCB databases in one simulation. You Conclusion can easily set up extensive “sweep” simulations to sweep circuit variables Although using MGTs in your through a range of values to test out dif- high-speed design can bring high- ferent implementation options. er performance to your FPGA Simulation of trace parameter varia- application, you must be careful tions (such as loss tangents, skin effect, in performing the implementa- dielectric constant, and other varia- tion. By correctly using the tions), crosstalk, power noise, deter- SPECCTRAQuest MGT Design ministic/random jitter, and other effects Kit assembled for this task, you are all included. can avoid common problems and shorten your design cycle. The kit Stimulate your circuit with pre-coded includes layout guidelines, con- 8b/10b pseudo-random bit sequence Figure 3 - Simulation from layout and extracting a differential net straints, topologies, scripts, and (PRBS) patterns to create inter-symbol utilities that will help you inte- interference (ISI) and study its effect on sig- SPECCTRAQuest has a unique way of grate Rocket I/O MGTs into your high-speed nal integrity. With the push of a button, you superimposing advanced simulation on top Virtex-II Pro designs. can plot the resulting waveform as an eye of high-speed PCB layout. For more infor- diagram so you can quickly quantify the sig- mation on the features available in The MGT design kit is available for free nal degradation from transmitter to receiver. SPECCTRAQuest and other Cadence PCB download from the Spice Suite at www.xil- SPECCTRAQuest also provides automated tools, please refer to www.specctraquest.com inx.com. Registration is required if you are measurements of each circuit’s performance. and pcb.cadence.com. not already a Xilinx customer

Spring 2002 Xcell Journal 25 Product Focus Third Party Software

by Jay Gould Embedded Partners Program Manager Xilinx, Inc. [email protected]

Xilinx Platform FPGAs introduce a Best-of-ClassBest-of-Class completely flexible and programmable platform for creating custom and upgradeable embedded solutions. However, using high-performance processor cores can be a challenge. To maximize your productivity, you need EmbeddedEmbedded best-of-class embedded software development tools.

Time-to-market pressures and product differentiation goals often create con- flicts with engineering schedules. That’s why more companies are moving away SoftwareSoftware from home-grown tool environments and their associated support problems. In this competitive climate, it’s usually better for you to use the best, commer- cially available tools – and focus your engineering resources on unique, value- DevelopmentDevelopment added product design. Virtex-II Pro Requires A compiler tuned for a specific Embedded Software Tools processor architecture automatically The term “embedded software tools” produces tight, fast code. most often applies to the tools required ToolsTools to create, edit, compile, link, load, and debug high-level language code (usually C/C++) for execution on a processor engine. The processor could be hard or soft; 8-, 16-, 32-, or 64-bit; high or low performance, and so on, but the basic development flow is generally the same. With Virtex-II Pro™, you can target design modules for either silicon hardware in FPGA logic gates, or as software applications run on processor engines like the embedded IBM PPC405 hard core. Since hardware engineers, software engineers, firmware engineers, system architects, and others may all target the Virtex-II Pro, Xilinx has a “market leader” tools strategy to appeal to these different camps. This strategy also has the added advantage of appealing to the largest installed base of embedded users.

26 Xcell Journal Spring 2002 Product Focus Third Party Software

Xilinx could have created new embedded commanding market share with their broad VxWorks, which is also the market leader. software tools from scratch, (in fact, we range of development tools, Real Time The Wind River OEM tools for Virtex-II employ more software engineers than most Operating Systems (RTOSs), and middle- Pro and PPC405 include: “software” companies), but instead Xilinx ware solutions. A specific Virtex-II Pro ver- chose to launch the Virtex-II Pro with sion of the Wind River tools (compiler, • Diab XE – compiler software debugger, and JTAG run control “Xilinx versions” of established third-party • SingleStep XE – software debugger tools. Therefore you don’t have to embrace hardware probe) have been created for completely new development methodolo- Xilinx distribution via an OEM agreement. • visionPROBE II XE – JTAG run control gies and you can port existing designs into hardware connection probe The Wind River tools are optimized for the Virtex-II Pro fabric. With tens of thou- the PPC405. The Virtex-II Pro versions of “XE” stands for “Xilinx Edition”. sands of engineers already using these tools, these tools are created with some basic using a complementary model is far more Optimized Compilers Provide design size limitations so that Xilinx can constructive than creating a new technology. High-Performance Code package a lower-price entry point tool For an embedded processor core to run suite through the Xilinx sales channel. You The Diab C/C++ Compiler consistently machine code, the algorithm must be scores high in the entered in an HLL (high level lan- annual market research guage) such as C or C++ rather than results for best compil- in an HDL (hardware description ers. The fact that Diab language). A compiler is used to is highly optimized for translate that HLL design into the PowerPC and has specific (PPC405) binary code long been a market that can be executed on that leader made it a perfect particular processor. fit for the Virtex-II Pro and embedded PPC405 Bad compilers produce core. poorly optimized, bloat- ed code that takes up a A compiler turns high lot of memory and level language into runs slowly. A best- machine executable code of-class compiler is for a processor. Providing one which has been fine grained control of the compiler options, Diab is a tuned for a specific Figure 1 - full featured product which processor architec- Software tool flow ture and automati- allows you to balance speed, cally produces tight, code size, and memory usage fast code. This saves memory for the for your applications. At the can buy the unrestricted versions (or design and spares you days of hand-opti- front end of the Diab product is a lan- upgrades) from the Wind River sales mizing, trying to manually accelerate your guage parser which creates a language- channel. Wind River already supports the code. For the integration and debugging independent representation of your code, PPC405 and will also offer numerous stages, a software debugger is run on a and this unleashes the power of the five other embedded tools. host computer or workstation, and con- different back-end optimizer stages of the trols the program execution of the embed- Wind River makes numerous tools them- compiler. Diab provides optimization for ded target over a hardware connection selves and have a huge partnership pro- global, code selector, code generator, peep- probe. With a Virtex-II Pro and the gram where third parties build other tools hole, and instruction scheduler stages as PPC405, this communicates directly with to integrate within the Wind River well as supporting architecture-specific the processor core using a JTAG port. Tornado IDE (integrated development features such as the SPRs/DCRs on the environment). This opens the market to IBM 405 processor. Partnering with Wind River Systems numerous other software tool suppliers Both the Diab Compiler and the Xilinx worked with Wind River Systems, who can specialize in niche areas, provid- SingleStep Software Debugger are consid- the market leader in the embedded software ing extra value to end users. Wind River ered “best of class” products in the PPC industry, to provide a robust set of software owns multiple Real Time Operating embedded domain. The Xilinx PowerPC tools for targeting the PPC405 in Virtex-II Systems (RTOSs), but their main market OEM software product is based on these Pro FPGAs. Wind River Systems has a focus is on an RTOS product called top-of-the-line products.

Spring 2002 Xcell Journal 27 Product Focus Third Party Software

Debugging Embedded For other more complex Software on applications, which have the Real Target tight requirements for Hardware fast interrupts, maximum uptime and minimum laten- SingleStep is a multi- cy, the PPC405 and a robust windowed and full fea- RTOS may be required. tured embedded software debugging tool Wind River – VxWorks that is far superior to command line tools. Due to the close partnership This product is ideally with Wind River, Xilinx will suited for board/hard- validate that the Virtex-II ware development, driv- Pro development boards, er/firmware develop- and our tools, will work ment, and software seamlessly with the Wind application debugging River VxWorks RTOS. In (thus reducing the fact, the entire support of the requirements from two Virtex-II Pro will be validat- or more possible tools to ed in the Wind River envi- just one). Software ronment, including the cer- Figure 2 - SingleStep software debugger debuggers need to pro- tification of a Xilinx “Board vide basic “run, start, Support Package” (BSP) between the SingleStep debugger on the stop” control to debug an embedded system, that matches with our reference board. host and the Virtex-II Pro target. This but SingleStep exceeds these expectations as The certification is a formal process product allows JTAG run control of the one of the most feature rich embedded that is target for system debugging and, via hard- debuggers available. executed ware caching logic, the visionPROBE II by Wind SingleStep supports real-time target con- can execute high-speed downloads up to River and through which they publicly trol, high-speed downloads, built-in hard- 400 KBps. acknowledge a working configuration of ware diagnostics and Flash memory pro- The probe facilitates register initialization, our tools, boards, and devices. gramming. It provides a unique processor- hardware diagnostics, Flash programming, specific register interface to enable config- Conclusion and hardware breakpoints. Additionally, uring and initializing integrated peripher- this one probe allows for FPGA If full programmable als, and a command line interface with image downloads and embedded system scripting language to automate testing. ChipScope™ design with the This debugger provides superior PPC405 operation on Virtex-II Pro is support through hardware breakpoints – the same target what you are after, including four hardware instruction without hav- adding the software address, two data instruction address and ing to add or development flow to two data value breakpoints – and a register change cables. Figure 3 - your FPGA logic tools is the window. In addition to on-chip trace, next step. Rather than create a new RTOS Validation visionPROBE II SingleStep provides visibility for instruc- methodology and introduce a new tool tion completion, branch taken, exception Xilinx will provide some validation sup- suite to a mature market, Xilinx has cho- taken, data address compare, and other port for Real Time Operating System sen to partner with the market leader to debug events. (RTOS) environments. Depending on the access the best-of-class tools for the complexity of your application, an embed- PowerPC. Proven and established tools Connect Software Tools to ded system design may or may not require allow you to focus on adding value to the Embedded Hardware a hard-real-time operating system. If you your product design, without learning the To download new FPGA images or run the are experimenting with a gate-consuming nuances of immature or un-optimized host debug software tools on the real protocol or algorithm, some simple C/C++ tools. Read more about the Xilinx embedded system, visionPROBE II pro- code targeted for a Xilinx MicroBlaze™ embedded software solutions at: vides a high-speed parallel connection soft processor may be all that is required. www.xilinx.com/processor

28 Xcell Journal Spring 2002 Three powerful reasons to make Wind River your embedded solutions partner.

Discover why Wind River’s unmatched experience, innovation, and vision provide the ideal roadmap for success. For nearly twenty years, Wind River’s embedded expertise has provided direction for advanced technology companies worldwide. Today, this experience has made us a leader in a variety of growing markets, offering exceptional performance, selection, and reliability. • End-to-end development solutions • Unequaled customer service and support • Excellent time to market • Industry-leading technology • Strong joint development programs • Complete life-cycle support and upgradability Let us show you the fastest route to superior embedded performance in your application. Visit us online for more information at www.windriver.com

See us at the Xilinx Programmable World 2002

NETWORKING AUTOMOTIVE CONSUMER ELECTRONICS INDUSTRIAL AEROSPACE/DEFENSE SERVICES

Linux ISE

ISE version 4.2i is the first version of Xilinx design software to run on the Linux operat- ISE 4.2i Expands ing system. Now, you can run Xilinx implementation tools on Linux Red Hat version 7.2, including the Wine windows application layer. With the addition of the Linux operating system, you now have one of the High-Powered widest choices possible in design system platforms and implementation tools for programmable logic design. Design Productivity Expanded Device Support ISE 4.2i includes the latest device support for all of the Xilinx families, including the ISE 4.2i extends its coverage to new Xilinx logic devices new Virtex-II Pro™ product line. • The Virtex-II Pro Platform FPGA is the and even greater design tool productivity. only programmable device available with 3.125 Gbps serial I/O – and anywhere from zero to four IBM PowerPC™ 405 microprocessors embedded in the device fabric. • ISE 4.2i comes ready to implement Virtex-II Pro functions, as well as those available in the recently announced CoolRunner™-II and Spartan™-IIE device families. • ISE 4.2i also includes the new “-6” speed grade for the industry’s fastest Virtex-II FPGAs. • By delivering FPGA and CPLD device support from a single design product line, ISE gives you an easy way to move up or down device families without having to load or relearn new software. High-Speed Design Support

With Virtex-II Pro Platform FPGAs, you by Lee Hansen can now drive design I/O at speeds up to Software Product Marketing Manager tages in particular to designers looking at 3.125 Gigabits per second – a first in pro- Xilinx, Inc. embedded logic systems and high-speed grammable logic. And ISE 4.2i comes [email protected] signal challenges: ready to help you realize that high-speed In February, Xilinx released Integrated • Linux ISE I/O potential quickly and easily. All of the Software Environment version 4.2i logic • Expanded device support implementation tools, the pin planner, design software. ISE 4.2i delivers several and timing and constraints editors in ISE new capabilities that make it the most • High-speed design support 4.2i have been enhanced to simplify the complete package available for program- • Partial reconfigurability implementation of the high-speed I/O of mable logic design. Building on the the Virtex-II Pro devices. And the synthe- • Streamlining XPower performance advances of ISE 4.1i, released this past sis tools can optimize the paths to and August, version 4.2i offers several advan- • MXE-II from the multi-gigabit transceivers

30 Xcell Journal Spring 2002 New Products ISE 4.2i

(MGTs), a capability unique to ISE 4.2i while the remainder of the FPGA contin- lation capacity and performance needed to design software. ues to run. Products can be updated for verify the ever-increasing repertoire of new functionality while still in the field, faster and denser programmable devices. The ISE 4.2i libraries also support instanti- and the product doesn’t have to be taken These additional capabilities are user-trans- ation of 1, 2, and 4-byte flavors of the high- offline while new functionality is loaded. parent, requiring no time-consuming speed I/O protocols supported by Xilinx. learning curves. In fact, MXE-II simula- Streamlining XPower Performance Xilinx and Cadence Design Systems have tion software requires less from the end jointly developed high-speed design kits. XPower, an ISE feature that estimates the user because of the integration with ISE’s These kits include software components power consumption of FPGAs and CPLDs, HDL Bencher™ graphical test bench gen- and design aids to help you use the Virtex- has also been streamlined for better per- eration environment. HDL Bencher wave- II Pro multi-gigabit transceivers. The kits formance. VCD simulation files now read in forms are automatically translated into also contain HSpice compatible models for much faster than previous versions, allowing VHDL or Verilog, simulated with MXE- analyzing PCB electrical trace effects com- for quick and accurate setup of input signal II, and the expected results can be ing off the high-speed Virtex-II Pro I/O activity. And XPower now supports the new back-annotated into the original wave- pins. By combining the new HSpice models CoolRunner-II family of CPLDs. forms. Discrepancies between expected for the Virtex-II Pro MGTs, IBIS models and actual results are also high- for all our FPGA device families lighted, expediting dynamic and SWIFT models describing the verification. behavior of the PowerPC™ Moreover, MXE-II includes microprocessor and multi-gigabit optimized libraries that deliver transceivers, Xilinx provides sup- faster simulation runtimes port for analyzing your FPGA, than competing technologies even after it’s been programmed for post-route non-timing/tim- and ready for the board. ing simulation. These libraries Partial Reconfigurability are available for all the device families supported in ISE. Continuing its long string of firsts These enhancements – coupled in the programmable logic indus- with a new, fully automated try, Xilinx has added a new capa- licensing process – significant- bility to both the ISE software ly expand MXE-II’s usefulness family, as well as the Virtex-E and to a broader set of PC-based Virtex-II product lines – Partial customers. Reconfigurability. Introduced in Figure 1 - XPower New Design Wizard ISE 4.2i, Partial Reconfigurability MXE-II performs 33% better allows either a Virtex-II or Virtex-E FPGA than its predecessors. That, plus the dou- XPower New Design Wizard to be partitioned so that part of the device bling of MXE-II’s capacity, makes it ideal can be reprogrammed, while the remainder Most important, in the ISE 4.2i version of for the verification of all types of Xilinx of the FPGA continues to run. XPower you will also find the “XPower devices, including the CoolRunner-II, New Design Wizard,” shown in Figure 1. Spartan-IIE, and Virtex-II families. Partial Reconfigurability works through The wizard helps XPower users read in the Modular Design option for ISE. Using Conclusion design data, input VCD files if available, Modular Design, the overall design can be set default parameters, and identify and ISE 4.2i continues to deliver the speed partitioned into sub-modules that can be then set specific input activity rates – all in you need – from the simplest designs in implemented independently of each other. a tab-delineated form that’s easy and intu- the smallest device families to the most Once a module is completed, its timing itive to use. This new wizard helps you get demanding high-speed, embedded sys- and performance are locked down while more accurate thermal estimates faster. tem designs. Upgrade today to get the the remaining modules are being finished, most leading edge capabilities available delivering faster overall design completion. MXE-II Simulation Software for your programmable logic products. With the addition of Partial ModelSim™ Xilinx Edition II (MXE-II) You can find out more about ISE 4.2i at Reconfigurability, the device can also be simulation and debug software is now www.xilinx.com/ise/42i. For a recorded partitioned where electronic functions available to all ISE customers. Based on e-learning lecture on ISE 4.2i, go to make the most sense. Then later on in the Model Technology’s ModelSim 5.5e soft- www.xilinx.com/support/training/ field, one partition can be reprogrammed ware, MXE-II delivers the additional simu- north-america-home-page.htm.

Spring 2002 Xcell Journal 31 New Products Virtex-II Pro Configuration NewNew ConfigurationConfiguration OptionsOptions forfor Virtex-IIVirtex-II ProPro Configure Virtex-II Pro FPGAs – and load embedded processor software – using the System ACE pre-engineered configuration solutions.

by Frank L. Toth Marketing Manager, Configuration Solutions Division devices to give you the benefit of industry- ware and hardware control. Built In Self Xilinx Inc. wide increases in speed and density. When Test (BIST) files at the system level can be [email protected] power is applied, the System ACE CF solu- loaded and used to reconfigure the FPGAs tion uses the JTAG port to configure the to perform system-level I/O, network Xilinx offers a variety of System ACE™ Virtex-II Pro™ fabric and the embedded communication, functionality, and mem- configuration options to meet a wide processor, as shown in Figure 2. Virtex-II ory tests. Then the FPGA can be reconfig- range of configuration speeds, densities Pro FPGAs can also be easily accessed by ured for the mission mode. (bitstream size), and costs, as shown in the Xilinx ChipScope™ debugging tools Built-in Configuration Controller Table 1. These pre-engineered solutions using this same JTAG port. In a system with a Virtex-II Pro device along simplify the configuration of our FPGAs The System ACE CF solution uses the with other Virtex™ and Spartan™-II and help you get your design to market as industry standard FAT file management FPGAs, the Virtex-II Pro device may be quickly as possible. system, which enables you to manage configured first. Then the embedded The System ACE CF solution, shown in both bitstream and software files like disk processor can be used as a configuration Figure 1, leverages the tremendous density space. Multiple configuration bitstreams controller eliminating the need for a sepa- of commercial compact flash memory can be selected and managed under soft- rate processor. The Virtex-II Pro FPGA

System ACE CF System ACE MPM Automatic Test Equipment (Compact Flash) (AMD Standard Flash) PC-Based Tools JTAG Test Tools Multiple Designs no limit up to eight S/W Storage Yes No JTAG Test Removable Yes No Port

R R

IRL Hooks Yes Yes ® R ATA JTAG Density 128Mbit - 8Gbit 16-64Mbit 256Mbits R ACE R COMPACTFLASH Performance ~30Mbit/sec 152 Mbit/sec Controller R

#Components 2 1 CPU R bus Min. Board Space ~(50mm x 50mm) ~(35mm x 35mm) Figure 1 - Space/bit 32-256 Mbit/sq. in. 8-32 Mbit/sq. in. Embedded System ACE CF Microprocessor overview Table 1 - System ACE configuration options

32 Xcell Journal Spring 2002 New Products Virtex-II Pro Configuration

If you want to use a different form factor

R and mount the components directly on HW TQ144 ® External Memory

R JTAG 256Mbits the board, the System ACE Soft System ACE SW COMPACTFLASH Controller IP is available. This pre-engineered solution is identical in functionali- can then be reconfigured allowing one Memory ty to the System ACE MPM solution and processor to be used for configuration, Controller you can download the IP free of charge. system test, and the mission mode. Taking Full Advantage of Because the processor and the intercon- PowerPC System Re-Configurability nect fabric of Virtex-II Pro FPGAs can Processor easily be programmed for multiple func- With the advent of the embedded proces- tions, you can use the optimal configura- sor and the other system-level features of tion mode including JTAG, Slave Serial, Virtex-II Pro Device the Virtex-II Pro family, the use of multi- or SelectMap modes. ple configurations becomes more useful, both to increase system flexibility and Figure 2 - Configuration via JTAG port As an alternative configuration sequence, the extend product life. Multiple configura- Virtex-II Pro FPGA can be “booted,” as tion files can also be used as a vehicle for shown in Figure 3, using a smaller boot file loading BIST and for testing system func- provided by the System ACE solution on tionality, integrity, and performance. power up. The embedded processor can then External Memory take control of the configuration process and Conclusion in turn configure itself and the rest of the sys- With the Xilinx System ACE solutions, tem by sending the appropriate interface and you can easily control both the configura- Memory control signals to the System ACE solution. Controller tion of your FPGAs and automatically load your embedded processor software. There is no easier way to configure your System ACE PowerPC Interface Processor Virtex-II Pro designs. HW For more information on System ACE R Boot Code ®

R products, go to: www.xilinx.com/xlnx/ Mbits JTAG 256 SW System ACE COMPACTFLASH Virtex-II Pro Device xil_prodcat_product.jsp?title=system_ace SW SW Figure 3 - Internal boot on power up

Other Configuration Options Figure 4 - System ACE Xilinx also offers several other pre-engi- multi-package neered configuration solutions including module serial PROMs, the System ACE MPM (Multi-Package Module, shown in Figure 4) and the System ACE SC (Soft Controller). The density of the System ACE MPM solution ranges from 16 to 64 megabits (or more by using the System ACE bitstream compression software) and features a Slave Serial or Select Map configuration port output. The native flash/microprocessor interface allows the System ACE MPM solution to be connected to the microprocessor bus.

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www.xyronsemi.com See us at the Xilinx Programmable World 2002 Perspective Industry Trend PlatformPlatform FPGAsFPGAs TakeTake onon ASICASIC SOCsSOCs Here are seven good reasons why Platform FPGAs provide a superior design environment and faster timetime toto marketmarket thanthan ASICASIC SOCs.SOCs.

by Milan Saini Technical Marketing Manager, Alliance Software Marketing Xilinx, Inc. [email protected]

Spring 2002 Xcell Journal 35 Perspective Industry Trend

The system-on-a-chip (SOC) market has of the speed benefits could not be realized. ering the performance, capacity, and inte- experienced steady and consistent The fact that the choice of system elements gration that is necessary to challenge and growth. Dataquest estimates roughly half is already made greatly simplifies the displace the current established platforms of all ASIC design starts are SOC based. design and development process. A fixed of system design. That percentage is projected to reach architecture is particularly beneficial for For instance, FPGAs now make it entirely 80% by 2005. There are several reasons software tool and IP providers in allowing feasible to build systems of up to 2M (ASIC) for this clear shift in design methodology. them to deliver better value, customiza- gates with CPU(s) running at 400 MHz, Some of the obvious advantages include tion, and architecture-optimized solutions. serial I/O channels at 3.125 Gbps CLB fab- greater component integration, increased ric-switching at 300 MHz, and the entire speed (Logic <-> Processor), lower system clocking over 150 MHz. This sur- packaging and test costs, and passes the projected sweet spot of ASIC increased overall system reliability. SOC designs. All of these combined can potentially make significant contribu- Looking at it in pure economic terms, tions to achieving the often elu- the costs for a typical mask set for a sive but always important goal of 130 nm ASIC run into the $700K+ accelerated time to market. range. That raises the bar for entry into the ASIC space, making the Platform Programmable logic device vendors FPGA an even more attractive option for a have entered the SOC solution space growing percentage of all SOC designs. with the introduction of a new class of devices known as Platform FPGAs – with Summary: FPGA silicon is best-in-class in the most recent addition being the Virtex- process and engineering, thereby deliver- II PRO™. These devices offer the same The assembly of the various hybrid IP ing best-in-class system performance. level of integration as ASIC SOCs, but in blocks in an ASIC adds substantial com- #3 – Software Tools and Methodology contrast, Platform FPGAs facilitate the plexity and hardship to the users’ design development of a wide range of applica- and development environment, because of It is well known that EDA designer pro- tions on the same chip. This article focus- a variety of issues relating to tool and IP ductivity for ASICs is lagging behind es on seven of the key advantages of the interoperability, physical layout, timing, recent silicon advances. The ability to cre- Platform FPGA approach. and system verification. For Platform ate a productive design and debug environ- FPGAs, on the other hand, it is much eas- ment is absolutely essential to the success of #1 – Pre-Engineered Platform ier to tailor and optimize components – any silicon platform. Therefore, software Platform FPGAs integrate several fixed such as silicon, software, support, and IP – plays a critical role in not only making the and predetermined blocks of hard IP because FPGAs represent a fixed and pre- platform easy to use and work with, but (intellectual property) components (sys- engineered target. also in extracting the most performance tem elements) within the programmable and device utilization out of the silicon. Summary: A fixed, pre-engineered but fabric. Notable among these are high-per- programmable FPGA solution offers a The goal is to insulate the user from hav- formance RISC CPUs, multi-gigabit and 3 more productive and efficient developing to learn extraneous details about the high speed I/Os, block RAM, system ment environment from both the software platform, yet providing empowerment and clock management, and dedicated DSP and silicon perspective. control when and where it is needed. To processing hardware. This powerful this end, FPGA vendors have created cus- assembly and harmonious blend of com- #2 – Process Technology tomized and user-friendly processor sys- ponents1 creates a cohesive system design tem generator tools that aid in instantia- PLD vendors have been able to extract environment. This environment offers great value and benefits from Moore’s Law tion, initialization, and configuration of all unprecedented flexibility and perform- and shrinking device geometries. While the various system component blocks. In ance, thus enabling the deployment of a the majority of ASIC design starts are at or addition, these software tools automate wide range of applications. higher than 180 nm, FPGAs have raced otherwise manual and error-prone tasks, The critical technological breakthrough is ahead to bring the cost and performance such as the interconnections among the in the ability to tightly interface the vari- advantages of 130 nm to its customers. processor, its peripherals, and buses. ous elements into the programmable fab- This ability to rapidly migrate to the lead- Design entry is engineered to tightly cou- ric. Without this tight integration, much ing edge of technology is essential to deliv- ple the HW/SW domains. Such engineer- 36 Xcell Journal 2 Spring 2002 Perspective Industry Trend

FPGAs overcome this problem in large part by being able to provide access to real or near real targets at a very early stage in the design cycle. Among other things, this means that SW engineers using FPGAs can quickly and easily sort out logic and design flaws by targeting real silicon. The engineers do not have to rely on ineffi- cient ASIC-centric techniques like co-verification or writing stub code. Application software can be debugged at system speeds with full hardware and software register access and control. Additionally, the FPGA fabric allows for construction of highly customized and value-added cores to enable powerful real- time, on-chip debug capability. Some examples of such instrumentation include: • Logic and bus analyzer functions • Bus protocol compliance monitors • Memory buffers for debug and trace port data • Cross-domain triggers and breakpoints Figure 1 - Software makes use of idle processor time. • Hardware run control of the CPU • HW/SW time synchronization logic. ing leads to not only simplified and easy- to systems on a board, SOC limits visibil- Furthermore, a single cable is able to per- to-use design flows, but it ensures reliability into the internal nodes of the system, form multiple functions, like debugging ity and robustness from the very start by making the task of verification and debug hardware, debugging software, as well as performing design rule and data consisten- more challenging than ever. programming the FPGAs. This greatly cy checks across the two domains. simplifies the lab setup making it much The critical part includes the verification easier to exploit the debug advantages. Two examples of the advantages of cross- of complex interactions between the domain HW/SW co-design include: application software and the custom- Summary: Platform FPGAs offer a clear- • Automatic generation of device drivers designed peripheral hardware. Traditional er, more cohesive, and overall more effec- and header files for SW engineers once HDL-centric verification and debug tech- tive debug strategy. Specifically, Platform a particular block is instantiated by the niques can no longer deal with the rising FPGAs offer up-front silicon access along HW designer complexity of system designs. with unprecedented visibility and control of the processor and its peripherals resid- • Tools to automatically populate SW Consider a typical application, such as ing in the programmable fabric. binary code into appropriate FPGA MPEG A/V decoding, where a large #5 – Top Tier Partnerships and memory bitstreams. number of simulation cycles are required Vendor Tools Support Summary: Software sells silicon. to complete a small sequence of frames. Co-verification tools in this case would In extending the concept of traditional #4 – Advanced Debug either take an impractically long time to programmable logic to Platform FPGAs, The importance of finding problems early complete or validate only a mere fraction certain critical technologies have had to cannot be overstated. Yet, up-front ASIC of the software code, falling far short of be developed or acquired. One of most verification is extremely designer- and what it takes to find problems in the exciting5 aspects brought forth by FPGA computer-resource intensive. Compared HW/SW interface. vendors has been to successfully forge 4Spring 2002 Xcell Journal 37 Perspective Industry Trend

strategic partnerships with vendors hold- tions, for instance, programmed in HW forced to either resolve problems subopti- ing various system technology compo- could be implemented in SW running on mally in software, or in the worst case sce- nents. Driven largely by the successes of the processor to save silicon. nario, they are forced to respin the silicon at the FPGA business models, leading ven- great cost and loss of time to market. On the other hand, SW structures and dors have been eager to partner in fulfill- algorithms – which can be broken into Reprogrammability comes up big here. ing the vision of building powerful pro- parallel, non-blocking processes – can Programmable platforms allow early grammable systems platforms. achieve significant speed and data access to silicon. Engineers can validate Areas of cooperation include partnerships throughput improvements by implement- performance and functionality in real sil- in the form of cutting-edge process tech- ing them in HW. In fact, software engi- icon, leading to greater confidence in the nology, powerful mainstream processing neers represent a new and emerging mar- reliability of the completed system. The elements – such as RISC CPU, high- ket for Platform FPGAs. Aided by design programmability of the platform allows speed I/O – and other components tools, it is now easier than ever for SW itself to be debugged and upgraded even deemed of significance to a system design engineers to explore concepts of software after the system has been deployed. This platform. IBM, Conexant Systems, Inc., acceleration via HW. Both hardware and helps promote and protect the time-to- Wind River Systems, and other high pro- firmware are reprogrammable and field market advantage by alleviating a large file vendors are currently engaged in such upgradeable, which enables the develop- part of the risk. strategic partnerships. What this means to ment and deployment of several product Summary: Programmable Platform you is there is no need for these partners generations from one base. This translates FPGAs provide better control over the to negotiate licensing, royalty, and inte- into a much broader applicability than life cycle management of products by gration issues with individual vendors, ASICs and ASSPs. minimizing the cost and time penalty for thereby greatly reducing your engineering, In addition to being suitable for building design errors and specification changes. management, and accounting overhead. complex embedded applications, HW engi- Conclusion The appeal and draw of FPGAs has neers can utilize an otherwise idle processor caught the attention of independent SW to run relevant portions of their design In an era when SOCs continue to domi- tool vendors. Increasing numbers of ven- algorithms or control logic. As Figure 1 nate mainstream design, Platform FPGAs dors are able to sustain business models shows, the CPU can serve as a simple are emerging to take a share of the spot- selling to FPGA customers. Several new microcontroller running a single-threaded light from ASICs. While ASIC SOCs have vendors are setting up shop to write cus- application. PLD vendors add value by and will continue to be strong in certain tom tools to help enhance and exploit the providing software device drivers and segments – like low power, small form fac- unique capabilities of Platform FPGAs. library functions for rapid implementation tor, and high-volume, cost-sensitive con- Summary: The FPGA business model has without requiring the HW engineer to have sumer electronic gadgets – an increasing attracted top-tier silicon and IP vendors to detailed knowledge of SW practices. range of other infrastructure applications in areas such as networking, telecommu- forge strategic partnerships to create pow- Summary: The Platform FPGAs provide the nications, industrial electronics, and data erful system design platforms. Software most flexible co-design platform by enabling storage have compelling reasons to move vendors are able to financially justify dynamic HW-SW design partitioning. investment in research and development to a programmable platform. leading to a continuous stream of an #7 – Risk Management increasing number of innovative solutions. When compared to Platform FPGAs, ASIC #6 – Application Space: Co-Design Flexibility SOCs present a huge design risk. With more variables and issues to worry about, Programmable HW combined with and with limited debug capabilities processors on a single chip softens the 7 when mistakes are found, HW/SW design boundary. By using ASIC designers are hardware-assisted architectural explo- ration, designers can optimally search for the right HW and SW partitioning, which6 leads to the increased probability of being able to meet performance and area targets. Sequential computing, exception handling, and control func-

38 Xcell Journal Spring 2002 See us at the Xilinx Programmable World 2002 Technology Focus Remote Upgrades YourYour ReconfigurationReconfiguration IsIs inin thethe E-MailE-Mail With Xilinx Internet Reconfigurable Logic technology and Virtex Platform FPGAs, you can perform fast and easy remote field upgrades via e-mail using microcontrollers.

by Marc Defossez Senior Staff Applications Engineer Xilinx, Inc [email protected] Since the beginning of the FPGA technology, Xilinx has pushed the boundaries of reconfiguration. In earlier FPGA families, it was only possible to reconfigure the whole • SMTP – Simple Mail Transfer Protocol is of data happens in the Internet Layer, FPGA. With the introduction of the used to deliver the messages. where IP is implemented. Virtex™ FPGA families, it became possible to partially configure or partially reconfig- • POP3 – Post Office Protocol 3 retrieves • Network Access Layer – Also called the ure an FPGA. It is also now possible to the messages. “link layer,” this is where the hardware interface is managed. reconfigure a remote FPGA via the Internet Figure 1 shows a complete Internet proto- using Xilinx Internet Reconfigurable Logic col stack. Each layer of the protocol stack is • Physical Layer – This is the actual medi- (IRL™) technology. However, only a few an abstraction level hiding details from um for communication across great dis- companies and a few of all FPGA designs other layers on top or below. For example, tances. Such transmission media make use of IRL technology, because of the the network access layer does not need to include co-axial cable, phone lines, fiber perception it is expensive, complicated, and know what kind of data it is carrying. optics, and wireless broadcasting. mostly a proprietary solution. Whether the data is video, voice, or other, Implementation What if we could securely reconfigure it is unimportant to the network access If you want to implement the Internet FPGAs in the field simply by sending an layer. The only thing this layer needs to do stack into an FPGA as hardware, it will: e-mail message? In this article, we will is deliver the data in good quality to the show you just how easy and cost-effective upper layers. • Take a lot of time (including VHDL or that can be. • Application Layer – This is the user Verilog design and simulation). Protocol Stack interface layer. The POP3 and SMTP • Require a robust FPGA. protocols necessary for IRL technology to Xilinx IRL reconfiguration technology uses • Consume a lot of money. work reside in this layer. the same transmission protocols as everyday On the other hand, microcontrollers are Internet e-mail: • Transport Layer – This layer implements good for protocol handling and can miti- reliable, full-duplex communication over • TCP/IP – Transmission Control Protocol gate the time and cost of building an IRL the Internet. TCP works in this layer. over Internet Protocol transports the solution for the remote reconfiguration of e-mail over the Internet to its destination. • Internet Layer – Addressing and routing FPGAs.

40 Xcell Journal Spring 2002 Technology Focus Remote Upgrades

• Once the link has been set up with the e-mail server, the microcontroller asks if STMP POP3 HTTP FTP Application layer there is e-mail available. When there is, the microcontroller checks the e-mail header. UDP TCP Transport layer • If the header is not of a particular type, the controller will delete the mail message on the server. ICMP Internet layer • When the e-mail has the correct header IP type, the microcontroller downloads it. The /PROGRAM pin is toggled, the contents are serialized onto an output pin, and PPP Ethernet Network access layer a bit clock is generated. • When the DONE pin goes High, the Modem UART Ethernet Physical layer microcontroller deletes the e-mail on the server. Figure 1 - Internet protocol stack • The microcontroller breaks the connec- Two microcontroller solutions are possible: Basic Setup tion. • Use external microcontrollers. The simplest setup consists of an FPGA and If the DONE pin does not go High after a a small controller, as shown in Figure 2. period of time, the download operation is • Put a microcontroller inside a Virtex Here’s what happens when the system is repeated until the DONE pin goes High. Platform FPGA. powered up: Although this is the simplest approach, it has There are two ways to embed a microcon- • The FPGA is empty. its shortcomings: troller in a Virtex device. • The microcontroller waits for a certain • An Internet connection is obligatory. • You can use the software MicroBlaze™ time until all components of the IRL microcontroller in Virtex, Virtex-E, • The server must always have mail ready for design have reached a stable state. Virtex-II, or the new Virtex-II PRO™ the application, or else the application can- Platform FPGAs. • Then the controller connects to the net- not start. work by sending AT commands to an • You can buy a Virtex-II PRO Platform • When configuration fails, no fail-safe external modem through an RS-232 FPGA with a hard-wired IBM® recovery mechanism exists. device, or by sending AT commands to an PowerPC™ 405 microcontroller already • The design can go into an endless loop try- onboard chip modem, or by other physi- onboard. ing to download its configuration. cal implementation. External Microcontrollers Several microcontroller manufacturers have Internet capable components. For instance, FPGA two Ubicom microcontrollers – SX52BD

and IP2022 – can be used for IRL applica- RS-232 tions. Such external microcontrollers OR DATA require “virtual peripherals” from Ubicom CCLK and some small modifications and additions to control downloading to an FPGA. PROGRAM These small controllers and peripherals INIT make the implementation of the TCP/IP, OR Microcontroller DONE SMTP, and POP3 components of IRL technology easy and fast. Due to the small amount of internal memory of the microcontrollers, however, the Internet protocol stack is tuned to only perform the neces- Ethernet Modem Figure 2 - Basic design setup sary functions.

Spring 2002 Xcell Journal 41 Technology Focus Remote Upgrades

In either case, the first bitstream must con- VCC tain the basic application of the FPGA. This way the system can operate as a standalone Master mode CE0 unit without problems. However, during

RS-232 CE DATA operation, the FPGA microcontroller can OR TMS DATA contact the Internet and download new bit- TCK 0E/Rst CLK CCLK TDI VCC

CF streams as they become available. TD0 FPGA The “basic setup” for external microcontrollers described above cannot be applied

OR Microcontroller PROGRAM to internal microcontrollers, because the INIT downloaded bitstream must be stored by DONE the FPGA in some semipermanent (flash)

Ethernet Modem memory. The final design of embedded microcontrollers can have different levels Figure 3 - Safe download of fail-safe operation, depending on the system requirements. Fail-Safe Setup • In both cases of soft and hard microcon- Conclusion trollers, the Internet protocol stack must You can make the download more reliable by be programmed (ported) onto the FPGA. It is possible to perform IRL operations in a storing the downloaded bitstream into semi- safe and inexpensive way using external or permanent memory (flash RAM). The • The FPGA must get a basic (possible par- internal microcontrollers – and some extra FPGA can then be reconfigured from the tial) bitstream to download the hardware. Xilinx IRL technology can now be flash memory. See Figure 3. MicroBlaze controller, its memory, and used in almost any design that requires field peripherals. An even more secure solution is to work with upgradability. Reconfiguration by e-mail two memories. A basic configuration can be • The PowerPC Virtex-II PRO Platform eliminates the need for complex and expen- loaded into the FPGA when it is shipped FPGA must have memory and peripherals sive design solutions. Furthermore, with a lit- from the manufacturer. During operation in downloaded before it’s able to boot. tle ingenuity, the IRL solution can be extend- the field, the microcontroller can connect to ed to designs that were not previously con- • The small control algorithm that was the Internet and download a new configura- sidered for field upgradability. Application done in the previous description within tion into the second memory. The new con- notes with detailed solutions will be posted the external microcontrollers must now be figuration bitstream would be downloaded in the coming months on the Xilinx website: implemented in a small CoolRunner™ into the FPGA at next boot. www.xilinx.com/apps/appsweb.htm. Look for CPLD, as shown in Figure 4. “Virtex FPGA” or “FPGA Configuration.” When the download works, the new configuration will be used. If the new programming bitstream fails, the microcontroller will Figure 4 - Internal boot again from original memory. processor Internal Microcontrollers Internal microcontrollers for FPGAs come in the form of MicroBlaze software and the hardware-embedded PowerPC 405 processor in Virtex-II PRO devices. (As a point of interest, the Virtex-II PRO Platform FPGA can be configured with both the MicroBlaze software and the PowerPC 405 processor, but that is beyond the scope of this article.) While there are significant advantages of having microcontrollers onboard Virtex Platform FPGAs, there are also factors, in this design case, that require special con- sideration:

42 Xcell Journal Spring 2002 See us at the Xilinx Programmable World 2002 Xilinx News IP SignOnce and Break the IP License Barrier Xilinx has sponsored the Common License Consortium to streamline the IP licensing process and improve your time to market.

by Mark Bowlby AllianceCORE Program Manager Xilinx, Inc. Strength in Numbers America, Europe, Japan, and Southeast [email protected] Asia, so there is likely a solution provider When selecting IP cores for your FPGA As a designer, you are constantly asked to somewhere near you. There is no cost for designs, you have access to Xilinx deliver new and enhanced systems. Your membership in the consortium, and only LogiCORE™ products as well as prod- marketing department asks you to add new IP providers may join. They do not need ucts from our third-party network of features, but do you have the time or prior to participate in the AllianceCORE pro- AllianceCORE™ providers. This hybrid experience to design everything in the new gram to become a member, and there is no approach ensures you a broad portfolio of specification? If not, you can always look at cost to customers to gain the benefits of IP and expertise to choose from. You ben- including pre-developed system functions the program. efit from competition, and it potentially in the form of intellectual property (IP) puts experts right in your own backyard. What Is Covered? cores from the FGPA vendor or one of a growing number of third-party providers. But everything comes at a price. A multi- The SignOnce IP License leverages the fact But can you wait until the legal issues vendor solution introduces the challenge that licensing IP cores for use in a specific around IP licensing are resolved before you of dealing with multiple providers, each FPGA is less complex than licensing for even begin your design? If only there was a with a different set of IP license terms. use in an ASIC. ASIC use usually requires way to clear the legal hurdles so you could Research has shown that license negotia- the transfer of source code. This requires spend your time on what matters most – tions between a customer and a single sup- extensive legal wording that can swell to getting your design completed on time. plier can exceed six months. Clearly, situ- 30 pages to protect the vendor against such ations that require you to deal with more issues as improper use and piracy. In September of 2001, Xilinx launched the than one vendor would be intolerable. Common License Consortium to specifi- The SignOnce IP License reduces this page cally address this issue. It is an industry- The SignOnce IP License takes care of count to four by focusing on the transfer of first initiative to simplify the licensing this. With it, you can sign up to a single an FPGA netlist. Netlists are specific to process for FPGA-based IP cores. At that set of license terms that, today, gives you particular FPGAs, and they are difficult to time, Xilinx and more than 21 third-party access to 500 reverse engineer or port to a different tech- IP providers all agreed to offer a common IP cores from nology. This dramatically simplifies the set of IP licensing terms – called the well over 30 license process. After a SignOnce IP SignOnce IP License – to get access to use providers. License is in place, you will then be able to their cores. Let’s look at how you can ben- Consortium membership continues to purchase individual cores at a price that efit from this new and innovative program. grow and includes companies from North you and the vendor(s) agree on.

44 Xcell Journal Spring 2002 Xilinx News IP

Usage Options The legal terms form the bulk of the license tium members to purchase more cores. and govern issues such as usage (project Because members have agreed to use the The SignOnce IP License provides project- versus site), intellectual property rights, same licensing terms, additions take little based and site-based usage options. indemnity, warranty, export restrictions, further assistance from your legal depart- A project-based license allows you to use a governmental use, and so on. All legal ment. When dealing with any consortium core within a single design. Ultimately, the terms (except for usage) are identical for member, make sure you let them know that core is incorporated into a larger design, con- both project and site versions of the license. you are interested in licensing IP using the verted to a bitstream, and pro- SignOnce IP License. grammed into the FPGA. Based on In Search of SignOnce IP this, the definition of a “project” includes the following scenarios: All SignOnce IP cores available from Xilinx and our AllianceCORE part- • A single bitstream, which can ners can be found in the Xilinx IP include multiple instances of the Center (www.xilinx.com/ipcenter/). core. You can then use that bit- As shown in Figure 1, the Smart stream on one or more printed Search engine allows you to restrict circuit boards. In this case, the your searches to only show cores that project is defined as the entire are available under the SignOnce IP chip that includes the core, which License. Even if you don’t select this can then be used (without modi- option, the search results will indi- fication) in other designs. This is cate which are SignOnce cores. You similar to the way you might use will need to contact non- an ASIC or ASSP device. AllianceCORE members of the con- • A single printed circuit board, sortium directly to find out what using one or more bitstreams, cores they offer. each containing one or more Conclusion instances of the core. This allows you to leverage the reconfigurable Your job as a designer is already dif- nature of FPGAs in your design. Figure 1 - IP Center Smart Search with SignOnce IP license option ficult enough. IP cores are available to simplify and accelerate your Your design group for the “proj- development process, allowing you ect” can span multiple sites. Usage of the Exhibit A is designed to list the specific to focus on the portions of the design IP core that goes outside of the above def- cores that you will license. Once you have where your expertise adds value. If you initions would require you to negotiate a SignOnce IP License in place with a con- adopt the SignOnce IP License and deal additional fees with the IP vendor. sortium member, you can license addition- with members of the Common License al cores from them by negotiating a sepa- On the other hand, a site-based license Consortium for your IP, you will remove a rate Exhibit A for each core and paying the allows your company to use the core in major time-to-market bottleneck for you appropriate license fees. unlimited designs developed at the speci- and your company. fied site. You would have to pay additional Exhibit B is designed for listing the consor- For more information on the SignOnce pro- fees for usage at other sites, or you could tium members that you wish to do business gram – including the growing list of consor- negotiate a list of sites to be covered under with. Each member signs and attaches a tium members, copies of the licenses, and the up-front license fees. separate Exhibit B so you can add IP searchable lists of Xilinx and AllianceCORE providers at will. You can sign all members In general, site-based licenses cost more than vendor IP – follow the Web links shown in on at once or add ones as needed by simply project-based licenses from IP vendors that Table 1. The solution is available. Let it having each sign a separate Exhibit B that support both. Most consortium participants work for you. references the original license terms. support both license types, but some only offer one. You should inquire about this This structure provides Information Web URL when working with the vendors. considerable flexibility. Even if you sign a Program information, consortium Simplifying the Process www.xilinx.com/ipcenter/signonce.htm license with one vendor members, and license forms The SignOnce IP License consists of three for one core, you have Xilinx IP Center Smart Search Engine www.xilinx.com/search/ipsearch.htm parts: the legal terms contained in the body the ability to later sign plus two exhibits. on additional consor- Table 1 - Web links for SignOnce program information and products

Spring 2002 Xcell Journal 45 New Products IP Bring on the Music– But Take out the Noise

New tools for Xilinx Reed-Solomon LogiCORE products help speed development and reduce errors in noise-prone multimedia and communications devices.

by Warren Miller VP of Marketing Avnet Design Services has created a hard- Reed-Solomon codes append a series of Avnet Design Services ware reference design to demonstrate the symbols (check words) to a series of infor- [email protected] functionality of two Xilinx LogiCORE™ mation symbols (data words). The check Reed-Solomon IP cores in an error-prone words are constructed (similar to the famil- Because Reed-Solomon codes are very system. The reference design uses standard iar parity check) in such a way that if errors good at correcting burst errors, they are Avnet-developed evaluation kits with the are introduced anywhere in the data, the used in applications where noise or defects Raptor/ISD (in-system developer) IP envi- correct data can be reconstructed. The can take out a series of information bits. ronment from Experience First Inc. number of errors that can be corrected is Products like CD and DVD players, as well one half the number of check symbols as wireless and hard-wired communica- Strength from the Core (rounded down). For 8-bit-wide data tions systems, use Reed-Solomon codes. The strength of Reed-Solomon codes in words, a common code has a block size of Successful communications in noisy envi- handling multiple bit errors makes them 207 words with 20 check symbols and 187 ronments using Reed-Solomon codes are one of the most efficient and common data symbols. This is the example code we possible through their means of detecting error correction codes used in communica- will use in the reference design. tions applications. Other codes (such as and correcting multiple errors without The Avnet Virtex Development Kit needing to retransmit the data. This Hamming codes) are better suited for the increases bandwidth and improves data more random error patterns found in The Virtex™ Development Kit developed integrity in error-inducing communica- memory systems, where only one bit at a by Avnet includes hardware tools on a sin- tions channels. time is affected. gle board for testing and debugging a refer-

46 Xcell Journal Spring 2002 New Products IP

(a sample output is shown in Figure 3). Because the signals are run at hardware speeds, hundreds of thousands of cycles can be exercised in the same time as a single cycle of software-only simulation. Conclusion Reed-Solomon codes are a basic building Figure 1 - The Avnet reference design hardware for Reed-Solomon code applications uses a block of many digital communications Xilinx Spartan-II FPGA Encoder (left) and a Virtex-II Platform FPGA Decoder (right). systems. The Xilinx LogiCORE Encoder and Decoder were easily ported to the Avnet development boards, using the ence design implementing Reed Solomon accelerates the development, integration, and Raptor IP development system from codes on Xilinx Virtex and Virtex-II test of IP or IP-based Xilinx FPGA designs. Experience First. For more information on Platform FPGAs. The Avnet board Raptor automatically inserts logic around Avnet Development Boards visit includes the following features: any IP core to route inputs and outputs to www.ads.avnet.com or contact Warren real-time input signals, output signals, and to Miller at Avnet Design Services • Data Generator, which creates an input buffer memory available on the development ([email protected]). For more infor- data stream board. This allows the core to be exercised at mation on the Raptor ISD visit • Reed-Solomon Encoder, which takes “hardware speeds.” expfirst.com or contact Bob Read at blocks of input data and creates the check Experience First ([email protected]). Core output signals that are stored in the symbols buffer memory can be read over • Error Generator, which injects controlled the USB port to a host computer pseudo-random error patterns into the and displayed on the waveform communications channel viewer, just like software simula- • Reed-Solomon Decoder, which detects tion results. This hardware speed and corrects errors in the transmitted data. approach to verification reduces the design/debug cycle time dra- The Data Generator and Encoder reside on matically, making it easy to the Avnet-designed Xilinx Spartan™-II change the design or test set-up FPGA evaluation board, as shown in and see the results immediately. Figure 1 (left). The data block with Used in conjunction with hard- appended check words is transferred to the ware-based input stimuli, verifi- Virtex evaluation board where the data is cation of very complex and received and corrected by the Decoder, as robust test suites are orders of shown in Figure 1 (right). magnitude faster than approach- Figure 2 - Experience First’s Raptor user interface lets you specify input and output signals to your IP reference design. The Error Generator uses a pseudo-random es based on pure software simula- number generator to select errors to inject tion. into the information block. Adding errors to The Raptor user interface, shown a reference design is necessary, because when in Figure 2, allows you to specify there are no errors, it is not clear that any- the inputs and outputs to your thing is actually being done by the design. IP. The necessary logic is auto- An IP development tool that works with the matically added around your IP Avnet Virtex development board allows you and then compiled using the to easily see the results of the decoder’s pro- Xilinx development tools cessing in the reference design. (Foundation™ Series software in Raptor IP Development Environment this example). The IP core is then exercised by the hardware and the The Raptor IP Development Environment is results are read out of memory an integrated software and firmware tool that and transferred to the PC over works in conjunction with the Avnet Virtex the USB port. The signals can be Figure 3 - Real-time Decoder waveform signals are Development Kit. The Raptor environment displayed on a waveform display input through the USB port.

Spring 2002 Xcell Journal 47 Perspective Set-Top Boxes Programmable Solutions for Set-Top Boxes FPGAs are critical to the success of the digital video revolution.

by Amit Dhir Manager, Strategic Solutions Xilinx, Inc. [email protected] The home audio-video landscape is The Set-Top Box Today quickly transitioning from analog to dig- In the early 1970s, the only piece of equip- Digital TV set-top boxes are sometimes ital, now providing several hundred chan- ment needed for watching TV was a stan- called receivers. A set-top box is necessary nels of 24-hour coverage, Internet access, dard television. In the 1980s, this simple to television viewers who wish to use their and other services. The convergence of model began to change. Cable and satellite current analog television sets to receive dig- functions provided by the television and TV providers required consumers to con- ital broadcasts. Typical functions imple- the PC requires a platform to provide nect their TVs to dedicated networks. Also, mented in a set-top box include: these services. With the arrival of several operators decided to scramble TV signals, services, the set-top box is growing • Decoding the incoming digital signal requiring a special box to de-scramble the beyond its traditional function of signals at the consumers home. Today, dig- • Verifying security levels as well as enabling digital video. Future generations ital television requires a set-top box to content access rights of set-top boxes will provide more services receive and decode digital transmissions. such as the ability to pause, record, store • Separating the audio and video data The main function of a set-top box is to and replay live video; provide video on from the decoded signal receive additional digital transmissions demand (VoD); provide Internet access; • Decoding the separated audio and (cable, satellite and/or terrestrial channels) and control other consumer devices. video data and to decode into a form suitable for dis- Providing these services will require the • Presenting video to the display device play on analog television sets. It’s a complex relatively simple set-top box to add com- electronics device comprised of a myriad of ponents such as flash memory, hard-disk • Presenting audio to the audio outputs hardware and software components, usual- drives, security chips, home networking • Processing and rendering Internet con- ly connected to the TV set and the cable chipsets, and so on. Programmable logic tent and other interactive services connection on the wall. They are installed solutions will enable the integration of and configured by the local cable, terrestri- these services and components in future • Providing electronic program guide and al or satellite service provider. generations of set-top boxes. remote control features.

48 Xcell Journal Spring 2002 Perspective Set-Top Boxes

Figure 1 shows the block diagram of a broadcasters to provide flexibility in terms ing CPU bandwidth, providing higher video generic current generation set-top box. of bandwidth vs. quality. frame rates and better audio quality, and enabling multimedia interactivity. According to Dataquest, sales of digital set- The MPEG-2 encoder, at the heart of every top boxes reached 25.1 million units in set-top box, is composed of a number of While MPEG-2 is the most common com- 2000, worth an estimated $6.3 billion, and discrete algorithmic sections: pression scheme used in set-top boxes, will exceed 92 million units and revenues • Temporal processing – It seeks out and MPEG-4 compression technology is gath- of $11 billion by 2005. It is estimated that removes temporal redundancy. This ering acceptance. It is earning keen interest 35 million U.S. homes will use digital set- involves storing several successive from set-top-box vendors and semiconduc- top boxes by the end of 2006, the estimat- images and performing motion estima- tor companies hungry to add features (such ed year ending the transition to DTV. tion, compensation, and simple algo- as picture-in-picture) to current designs, Digital set-top boxes are used for satellite, rithmic processing to derive a pixel-by- and from service providers eyeing it for cable, and terrestrial digital TV services. pixel difference signal. home networking and for set-tops integrat- They are especially important for terrestrial ed with digital video recorders (DVRs). • Spatial Processing – It uses DCT (Discrete services because they guarantee viewers free Cosine Transform) to remove the high fre- The MPEG-4 initiative is led by satellite television broadcasting. A set-top box price quencies not discernable by the human eye. providers exploring ways to reduce the bit ranges from $100 for basic features to over rates of their broadcast streams and by cable $1,000 for a more sophisticated box. It is Statistical or variable length encoding operators looking to add object-based inter- often leased as part of signing up for a serv- (VLC) is used to remove redundancy in the active features to their programming. Using ice. Leading set-top box manufacturers are output from the DCT. The MPEG-2 algo- the MPEG-4 Advanced Coding Efficiency looking to increase revenues by winning con- rithm makes use of the DCT/IDCT algo- profile, satellite broadcast streams – current- sumers that would like to use the TV set not rithm. DCT returns the discrete cosine ly delivered at bit rates of 2.5 to 3 Mbps – only to watch television programs but also to transform of browse websites, send e-mail, and shop for “video/audio goods and services through the Internet. Set-top boxes in the future will provide more channels and increased choices through specialist channels, which can provide immediate feedback to broadcasters. The set-top box will provide new services such as improved pay-as-you view, online shopping, interactive TV, video-on- demand, and hard-drive storage. Providing Digital Video Processing In the digital TV realm, a typical digital set-top box contains one or more microprocessors for running the operating system (possibly Linux or Windows), and for parsing the MPEG transport stream. A set- top box also includes RAM, an MPEG Figure 1- Block diagram of decoder chip, and more chips for audio current generation set-top box decoding and processing. The contents of a set-top box depend on input” (referred to as the even part of the can be trimmed to 1.6 Mbps while main- the digital TV standard used. European Fourier series) and converts an image or taining good-quality video. Meanwhile, DVB-compliant set-top boxes contain audio block into its equivalent frequency some service operators are also considering parts to decode COFDM transmissions coefficients. IDCT (or inverse DCT) recon- MPEG-4 as a way of saving hard-disk-drive while ATSC-compliant set-top boxes con- structs a sequence from its DCT coeffi- space in set-top boxes equipped with DVRs. tain parts to decode VSB transmissions. cients. Compression allows increased The set-top box provides improved quality, throughput through the transmission medi- Others see MPEG-4 as effective in reduc- support for HDTV transmission, prevents um. Video and audio compression makes ing the bandwidth required for real-time “ghosting or interference effects, and allows multimedia systems very efficient by increas- video for home-networking applications.

Spring 2002 Xcell Journal 49 Perspective Set-Top Boxes

There is a need for MPEG-4 in picture-in- The NetTV is a TV-centric consumer appli- the Internet. A house however will have a picture applications – while a national ance that provides Internet access while using single broadband access point and the digi- game broadcast occupies the screen, for the TV as the primary display. In its most basic tal media will be shared not only between example, a local game compressed in offering a NetTV provides limited interactive friends and family across the Internet but MPEG-4 could be broadcast simultaneous- electronic programming guides or customized also between appliances in the house. ly so that it appears as a picture within the information tickers. Advanced NetTVs pro- The set-top box of the future will provide picture. Further, Internet-streaming con- vide full graphical Web browsing and video high-speed Internet access from satellite, tent – compressed in MPEG-4 or email. While the consumer is very interested in cable, DSL, fixed wireless, and terrestrial Windows Media – could also be displayed services such as access to the Internet, cost access technologies. While one box may on screen in a picture-in-picture format. remains a big inhibitor for the success of the support a single access technology, combina- NetTV appliance. Set-top box manufacturers Most set-top box manufacturers are not tions of broadband access technologies will are looking to integrate the functionality of the looking to replace MPEG-2 with MPEG- exist within one set-top box. Set-top boxes NetTV in next generation set-top boxes. In the 4, but to equip a set-top box to transcode will also provide interconnectivity between Internet realm, a set-top box is really a special- MPEG-2 streams into MPEG-4. Clearly, consumer devices through a number of ized computer that can “talk to” the Internet – the versatility of the MPEG-4 standard is playing to its advantage as MPEG-4 finds its way into different set-top uses. SDRAM DRAM Integrating DVR, VoD, and NetTV Functions Controller DRAM The last few years has seen the introduction Cache/Bus Cache of the digital video recorder (DVR), also Controller Clock Generator SDRAM known as digital VCR and personal video & DLLs Controller

recorder (PVR). The DVR uses local storage 32-bit Satellite QPSK Decoder System (such as a hard-disk drive) to enable the user- Processor and FEC Audio/ Audio/ Audio- controlled storage and playback of live digi- I/O Video Video Video Control Buffer tal video streams. The functionality includes Cable QAM Decoder Buffer DACs and FEC the ability to simultaneously record and play- Descrambler back separate video streams or different por- Glue Digital Video & Peripheral Bus Logic Digital Audio tions of the same stream in real-time. General RS-232 Ethernet Purpose Serial Smartcard With a built-in modem, the DVR device MAC I/Os I2C UART Interface dials a service provider and downloads the programming guide and other software updates. While high unit growth is being predicted for these DVRs, most set-top box Figure 2 - Digital set-top box manufacturers are looking to incorporate a hard-disk drive and DVR functionality with- that is, it contains a Web browser (which is in the set-top box. This will provide the capa- home networking technologies, such as: bility to store real-time TV broadcasts in really a Hypertext Transfer Protocol (HTTP) • No new wires – Phonelines, powerlines high digital quality, instant access to the client) and the Internet’s main program, recorded data, proactive and quick TV man- TCP/IP. The service to which the set-top box • New wires – IEEE 1394, IEEE 1355, agement, and the simultaneous use of multi- is attached may be through a telephone line or Ethernet, USB 1.1/2.0, Optic Fiber, RS- ple data streams. It will also allow the ability through a cable TV company. 232, IEEE 1284 Parallel Port to download software and other applications Enabling Broadband Access • Wireless – HomeRF, Infrared, Bluetooth, provided by a digital TV service provider. and Home Networking DECT, IEEE 802.11b, IEEE 802.11a, Apart from providing real-time TV broad- The arrival of digital media such as data, HiperLAN2 cast recording capability, set-top boxes will voice, video and communications (Internet) As home networking gains popularity, provide the consumer with video-on- through appliances such as digital cameras, the set-top box will grow from enabling demand capability. The consumer will be MP3 players, cellular phones, and Web digital TV and broadband access in the able to order a movie instantly. It provides pads, is bringing a need for networking con- house, to a residential gateway that man- the ability to pause, fast forward, and rewind sumer devices and PCs. All these consumer ages and controls other information the movies as often as the consumer desires. devices are demanding high-speed access to appliances in the home.

50 Xcell Journal Spring 2002 Perspective Set-Top Boxes

Categories and Evolution to advanced services such as video telecon- box for receiving television and a modem Home/Residential Gateway ferencing, home networking, IP telepho- to connect to the Internet. Phase two ny, VoD, and high-speed Internet TV includes advanced features such as broad- This huge installed base of set-top boxes services. Additionally, it has enhanced band connectivity, home networking inter- can be broadly classified into the following graphical capabilities to receive high defi- faces, and IP telephony in the residential categories: nition TV signals and can store video on a gateway. The third phase will be deploy- • Analog set-top boxes perform the func- hard disk drive, while providing the capa- ment of powerful gateways, capable of tion of receiving, tuning, and de-scram- bility to record and view video simultane- delivering video, voice and data through- bling incoming television signals. These ously. Such receivers have a range of high- out the home and providing services such receivers have changed very little over the speed interface ports, and resemble resi- as home automation, energy management, past twenty years. dential gateways. For cable, terrestrial, and security control, and so on. satellite companies, set-top boxes that • Dial-up set-top boxes allow subscribers to Supporting multiple technologies makes support advanced technologies are an access the Internet from the comfort of the gateway less likely to become obsolete. opportunity to increase revenue streams their living room through the television. Support for modularity will fuel the evo- through providing services. lution of gateways into a type of applica- • Entry-level digital set-top boxes are capable tion server that of receiving broad- consumers will cast digital television Clock Generator NTSC On Screen Display & use to distribute that is complement- & DLLs PAL Graphics Generator broadband served with a pay-per- Encoder Satellite To TV ices throughout view system and a QPSK Decoder and FEC Audio- their homes. The very basic navigation Glue Logic Video DACs gateway must tool. They have no Memory Analog Cable QAM Decoder have a reliable Front return channel, and and FEC MPEG HomePNA End and robust hard- I/O therefore do not Decoder (AFE) Control ware platform, interact with com- & CPU 10/100 Base- Terrestrial OFDM Decoder TX Ethernet MI and software that puter servers. MAC and FEC is not susceptible Characteristics of Glue Interface 10/100 Base-TX to errors. Unlike this type of low-cost Logic RJ-45 xDSL DSL Driver/Receiver, Transceiver PC users, con- box include limited Transceiver and FEC USB USB sumers will not UTP quantities of memo- Device Transceiver Conditional stand rebooting ry, interface ports Controller Hard Disk HDD Access their gateways. and processing Drive Interface IEEE 1394/Firewire Supporting mul- power. Figure 2 Smart Card RS-232 tiple services shows a digital set- Figure 3 - Residential gateway with complete top box. security is essen- • Mid-range digital set-top boxes include a The residential gateway is a platform to tial. Functions such as e-commerce trans- return (back) channel, which provides bring broadband into the house and con- actions, and remote home control and communication with a server located. nect or bridge to home networking tech- access from authorized service providers These set-top boxes provide e-commerce, nologies. It enables communication are critical. Providing quality of service to Internet browsing, and multimedia serv- between networked appliances in the home support multiple intelligent devices from ices. The return channel further allows and across the Internet. The evolution of different vendors is extremely important. for customized broadcasts to the local new data broadcasting services has created Figure 3 shows the block diagram of a resi- viewing population. These types of boxes the need for a device to pass digital content dential gateway. The gateway provides a have higher processing power and storage between the Internet and the home net- unified platform to satisfy the needs of most capabilities of entry-level boxes. work. Future gateways will provide integrat- consumers, providing infotainment, con- ed services such as remote management, • Advanced digital set-top boxes are like veniences, and communication. The success home automation, and home security. multimedia desktop computers, contain- of the set-top box, and hesitation by a large ing much higher processing power than Mass deployment of gateways will come in population to own a PC, allows for the set- other set-top boxes. Enhanced capabilities three distinct phases. While the gateway is top box to grow into a successful residential in conjunction with a high-speed return a new term, it already exists in many gateway. Set-top boxes will evolve into mul- path can be used to access a variety of homes. Most of our homes have a set-top timedia servers, forming the hub of the

Spring 2002 Xcell Journal 51 Perspective Set-Top Boxes

home network for primary access to the For video processing conventional DSPs presence of the FPGA in the system provides Internet, such as the residential gateway. (digital signal processors) provide a fixed the capability to remotely upgrade features data width and inflexible architecture. They through the Internet when the box has been Programmable Logic Solutions Enable Future typically have 1-4 MAC units and require shipped to the customer, hence providing a Set-Top Boxes serial processing, which limits data through- significant cost savings. For residential gateways to be successful, put. This causes a need for high clock fre- Summary programmable solutions will have to be at quency DSPs, which creates system chal- the heart of the system. Programmable logic lenges. Hence, multiple DSPs are needed to The set-top box is driving the digital revolu- devices address the fundamental disconnect meet bandwidth requirements, thus causing tion right into your living room. Your finger- between ASSPs and provide the interface power and board space issues. tips now command a wealth of high-quality and protocol translation between different Programmable logic devices have a flexible digital information and digital entertain- broadband and home-networking chipsets. architecture with distributed DSP resources ment, right from your favorite armchair. The They provide significant time-to-market and embedded multipliers. These devices set-top box revolutionizes home entertain- advantages and the ability to upgrade quick- can support any level of parallelism or serial ment by providing vibrant television images ly, which is imperative for a successful prod- processing through an optimal with crystal clear sound, along with uct. This gives you the cutting edge to bring performance/cost tradeoff. e-mail, Web surfing, and cus- products first to market, while having the This parallel processing tomized information such ability to remotely add features to the set- maximizes the data as stock quotes, weather top box already deployed in the home. throughput. and traffic updates, The set-top box will combine components Hence, program- on-line shopping, such as digital modem chipsets, home net- mable logic solu- and video-on- working chipsets, processors, memory, and tions exceed DSP demand – right software. Digital modem chipsets provide requirements of through a tradition- connectivity to different broadband net- the video market al television. – providing both works, and home networking chipsets pro- The set-top box will flexibility and per- vide interconnectivity technologies between evolve into home mul- formance. FPGAs are appliances. Other ASSPs/ASICs handle and timedia centers, possibly off-the-shelf devices, process digital video and audio services. forming the hub of the which provide fast time-to- These ASSPs communicate with each other home network system and the market, rapid adoption of stan- via buses on the system board. The proces- primary access for consumers to connect dards, optimal bit widths, and real-time pro- sor is responsible for coordinating the differ- to the Internet. There will be a convergence totyping along with support for high data ent components. With additional features, of technology with equipment connected to rates. With a whole suite of DSP algo- set-top boxes will require higher perform- the television, such as adding hard drives for rithms/cores and tools created for program- ance processors to keep pace with increased television program storage and instant replay. mable logic devices, development time can data throughput. However, all these stan- As the set-top box evolves, it will also provide be reduced by weeks while increasing the dards and ASSPs promote differing inter- home networking capabilities and value- performance of the system. For example, the faces making glueless connectivity impossi- added services, while becoming the residen- implementation of the DCT/IDCT core in ble between the different ASSPs, memories, tial gateway of the future. and processors. a programmable logic device can off-load the system processor performing MPEG Programmable logic solutions are necessary There are three types of set-top box soft- encoding/decoding with a 50X to 200X per- for the success of set-top boxes and resi- ware: operating systems, middleware, and formance gain. dential gateways as they provide time-to- applications. The operating system operates market and time-in-market advantages in the set-top box parts. The middleware is a Programmable solutions also provide the interfacing disparate technologies, compo- layer of software programs that operates ability to interface to different hard-disk nents and system interfaces. They also pro- between the interactive TV applications and drive types as well as NAND and NOR flash vide a significant performance advantage the operating system. Viewers use applica- memory types (depending on availability). over digital video processors. What is clear tion software to watch TV and use interac- They also provide content protection capa- is that the set-top box market is growing at tive features. The middleware also enables bilities using DES, triple DES, AES, and a very dramatic rate, and when markets are the smooth interoperation of information even proprietary encryption schemes. They so dynamic and the future is very unpre- appliances and services within the home, to also provide system interface functions such dictable, decreased time-to-market and the eliminate the complexity, distribution, and as PCI, USB, and so on, in the set-top box ability to upgrade very quickly is impera- technical disparity of the system elements. and residential gateway. In addition, the tive for a successful product.

52 Xcell Journal Spring 2002 New Products Reference Design

with Convergent Designs and utilizing their digital video and audio design expertise allows us to provide some exciting solu- Low-cost Digital Video tions for the consumer market.” Pricing and Availability Centauri is priced at $450 and immediately available for purchase on the Xilinx eSP IEEE 1394 Hardware website (www.xilinx.com/esp). Xilinx eSP for Digital Video Xilinx eSP (www.xilinx.com/esp) is the industry’s first Web portal dedicated to accelerating the design and development Reference Design of consumer products based upon emerging standards and protocols. Recently updated to contain broad coverage of digital video technologies, the eSP Web portal New reference designs provide OEMs with is a comprehensive resource delivering a powerful array of solutions and informa- a complete low-cost solution for integrating tion in a single location. digital video in consumer products. About Convergent Design

Convergent Design has joined the Xilinx XPERTS program, a worldwide third-party Certified Design by Xilinx Staff Service Center trained to take full “The Spartan family of FPGAs provided Xilinx and Convergent Designs recently advantage of the features in Xilinx an ideal low-cost solution,” said Michael announced the availability of Centauri, a FPGAs, software, and IP cores. Schell, president of Convergent Design. low-cost digital video (DV) IEEE 1394 “Because of the Xilinx commitment to hardware reference design based on the low- Convergent Design LLC specializes the Digital Video market, we’re able to cost Xilinx Spartan™ FPGA and the Divio rapidly introduce cost effective consumer in the design and development NW701 DV codec. The new reference of analog digital video/audio “The Spartan family of FPGAs provided an ideal low-cost solution. Because of the Xilinx commitment conversion and processing products. Specific technologies include: PCI, to the Digital Video market, we’re able to rapidly introduce cost effective consumer solutions that 1394, DV/MPEG2 compression, component video, SDI digital video, reduce overall time-to-market and cost.” – Michael Schell, president of Convergent Design. balanced audio, and AES/EBU design provides OEM manufacturers with a digital audio. Convergent Design solutions that reduce overall time-to- complete low-cost solution for easily inte- offers comprehensive design services market and cost.” grating DV over IEEE 1394 into a variety including initial product specification, of consumer digital video products such as “The introduction of this hardware refer- schematic capture, FPGA code DVD R/Ws, digital VHS recorders, set-top ence design is a great example of the com- boxes, residential gateways, Personal Video pelling value that FPGAs offer the con- development, PCB prototype and Recorders (PVRs), Digital TVs (DTVs), sumer marketplace,” said Robert Bielby, debug, compatibility testing, and video projectors, video editors, and profes- senior director of Strategic Solutions release to contract manufacturer. sional digital audio and video equipment. Marketing at Xilinx. “Working closely

Spring 2002 Xcell Journal 53 Perspective Digital Displays Programmable Logic Enables

by Mike Nelson Digital Displays Sr. Manager, Strategic Solutions Xilinx, Inc. [email protected] An overview of an important emerging market. DisplaySearch Inc. forecasts that by 2005, digital displays will eclipse conventional display technologies in market revenue. Digital liquid crystal displays (LCDs), digital plasma display panels (PDPs), digital light processors (DLPs), and many others are fast becoming the display technologies of choice. This article will explain why this is hap- pening and document the universe of complexity that has been spawned in the process. Next we will examine some of the unique challenges that digital display systems pose for you. Finally, we will review a representative case study to illustrate how programmable logic can be used to your advantage in developing digital display products. The Digitization of Display Technologies What’s driving the digital display transition? There are three basic answers to this question: • Content has become digital • Digital displays achieve superior quality • Digital display technologies have enabled new and desirable form factors. Content is king. Analog television became inexpensive because it served a huge content market: broadcast television. But things have changed. The emergence of commodity PCs, the Internet, digital cable and satellite TV, and consumer DVD have combined to establish a huge new universe of digital content. And, as the transition to digital broadcast television unfolds (SDTV and HDTV), virtually the entire display universe will have become natively digital.

54 Xcell Journal Spring 2002 Perspective Digital Displays

With regard to quality, digital content has Which are the correct features to support? • You require a high-bandwidth connec- several advantages. How do they vary by market segment? tion from the source. How do they vary by geography? How are • Digital content can more effectively filter • You need to perform a complex string of they evolving? How do you implement the noise as illustrated by the lack of back- operations on the data. These can include mix of features you need quickly and effi- ground hiss on an audio CD as compared decryption from a secure transmission for- ciently? Can you effectively support a fam- to an analog cassette. mat, decoding into pixel maps, and opti- ily of configurations to service multiple mization of these pixel maps for display. • Digital content enables digital manipula- market segments? How do you get to mar- tion of the content which means that you ket fast enough to gain market share? • You must use the resulting data to gener- can effect highly specific enhancements. Digital convergence is driving these tech- ate the driver signals for the display. For example: shadow enhancement, nologies together, in new ways and in new sharpness control, and color manipula- • Finally the display driver generates a fam- products – and making that happen is your tions commonly used in medical imaging. ily of signals that will be distributed to responsibility. drive each individual pixel. The format of • Digital content can be quickly and Unique Challenges of Digital Display Design these signals varies with each technology, repeatedly replicated with precision and they have exacting timing requirements, widely distributed much more efficiently Beyond the complexity of their world, and their specifications are often unique than analog formats. environment digital displays also present to each and every model. some unique challenges to you. These And then there is form factor. Without dig- include achieving the performance To make things worse this must all be ital displays, products such as today’s lap- required for the target application, cor- achieved in real time, and while transiting top computer would simply not be possible recting for technology-specific display this pipeline the dataflow will expand from (remember the first Compaq CRT based characteristics, and generating the drive about 25 Mbps (streaming HDTV) to 1.5 portable PCs?). The same applies to wall signals for the target display. Gbps (raw uncompressed 1080i HDTV mounted televisions, PDAs, seat back dis- display data). plays on airplanes, and the mini-displays Performance is particularly challenging in on the back of digital cameras. The inher- digital video display applications due to the The optimization stage of the pipeline is a ent flat panel nature of most digital display tremendous computational loads involved. challenge in and of itself. Here the digital technologies is thus a key factor in their increasing success. These applications Wired Broadband Chip to Chip LVDS Interconnect Television Streaming Media could not be fulfilled without them. Connection Access Technologies Technologies Standards Formats The Opening of Pandora’s Box Technologies Technologies LVTTL LVDS NTSC MPEG-1 While the emergence of digital display tech- IEEE 1394 ISDN LVCMOS LVPECL PAL MPEG-2 nologies has been a good thing, the develop- ments behind them have been the equiva- USB 2.0 DSL Chip to Memory BLVDS SECAM MPEG-4 lent of opening Pandora’s Box. In the frantic Ethernet Cable Technologies SDTV 480i MJPEG rush to digitization, technologies have been PC Display Formats invented and re-invented on a multi-dimen- HomePNA WCDMA HSTL-I SDTV 480p Real Networks sional scale across diverse geographies, HomePlug Chip to HSTL-III EGA HDTV 720p QuickTime industries, and suppliers. The result is a mul- HSTL-IV VGA HDTV 1080i MS Media Player titude of standards, formats, regulations, Wireless Backplane specifications, and derivatives, all of which Connection Technologies SSTL-I SVGA Digital Imaging Encryption makes your job ever more challenging. Technologies 5V PCI SSTL-II XGA File Formats Standards To illustrate the complexity that we have 802.11b 3.3V PCI SSTL2-I SXGA TIFF DES wrought, I have compiled a representative list of technologies, formats, and standards 802.11a 3.3V PCI-X SSTL2-II UXGA JPEG 3DES introduced as part of the mass digital HiperLAN2 GTL SSTL3-I WXGA Scitex AES emergence, in Table 1. Bluetooth GTL+ SSTL3-II Targa PKI Difficult Questions HomeRF AGP CTT GIF While by no means complete, Table 1 nev- ertheless illustrates a foremost challenge facing you today: risk and complexity. Table 1 - Standards and technologies spawned in the mass digital emergence

Spring 2002 Xcell Journal 55 Perspective Digital Displays

image data must be adapted to the specific interface and control software need to be The Value of Programmable Logic characteristics of the target display technol- developed? And, if it is determined that Programmable logic is an ideal solution for ogy. This is necessary because while all dis- you need to implement and support a vari- addressing these challenges. By their plays operate on similar principles of color ety of these technologies and options, your nature these devices are flexible – the pre- science, each has its own specific (and non- task becomes much more complex. mium requirement for success in this linear) behavioral characteristics. Thus, RGB data (which is most typically targeted for a CRT display) must be processed to display with acceptable results on an LCD, PDP, or other display technology. This pro- Image cessing can be as simple as color correction, Processing or much more involved with algorithms RGB applied for scaling, contrast, brightness, A/D Digital System Display Video gradation smoothing, edge sharpness, Converter Controller Driver Input RGB shadow enhancement, and so on. Almost anything is possible, it simply takes adequate processing power. µC A Case Study Figure 1 - Generic projection display system design To illustrate the challenges of digital display design let’s analyze a case study example for a digital projector. In the generic case such products traditionally accept ana- 802.11 RF MAC Digital Image log RGB video input, perform some mod- Decoding Processing erate processing on the data, and then drive USB 2.0 PHY MAC the projection display. This is typically Encoded File Formats effected through a variety of analog (blue), System Display Digital RGB Controller Driver digital (black), and control (green) components as illustrated in Figure 1. RGB Video Input A/D Converter With the advent of digital convergence, the µC next iteration of such a product may well be required to support some form, or Figure 2 - Digital convergence projection display system design forms, of direct digital input and include the ability to accept and display encoded file formats. In such a case, you face the dilemmas regarding which inputs and for- 802.11 RF MAC Digital Image mats to support, and then you must select Decoding Processing and integrate appropriate components to USB 2.0 PHY MAC realize them in a design that meets per- Encoded File Formats I/O Digital System Display formance requirements. Digital RGB Control RGB Controller Driver

Figure 2 illustrates an example for such a RGB Video Input A/D Converter design that would support a fast serial USB µC 2.0 connection as well as an 802.11 wireless LAN connection. The simplicity of these illustrations belies Figure 3 - Programmable logic-based digital convergence the complexity of the task. How do you implement the new logic in the system controller to manage the new data flows? What interfaces and signaling standards are Digital Mixed Signal µP or µC Programmable required in order to integrate the new components? What extensions to your user

56 Xcell Journal Spring 2002 Perspective Digital Displays

endeavor. In addition FPGAs are fast and effi- Figure 4 - FPGA cient development plat- utility in component forms, enabling rapid integration development cycles. Finally, modern FPGAs are extremely cost effective, and therefore viable production solutions for almost any application. Figure 3 illustrates how an FPGA-based solution could be used to affect our digital convergence projector. As you can see this design inserts an FPGA (illustrated in red) and associated logic between the A/D converter and existing system controller. In this design the FPGA serves as the I/O arbiter, accept- ing input from all three sources. project such as our example relatively straightforward. In operation the legacy digital RGB signal is simply passed through when this con- On the perimeter of Figure 4 nection is active. In the case of USB 2.0 is System I/O, which allows and 802.11 however, the FPGA serves to each and every I/O pin to be manage these new interfaces completely, as programmed to support any well as decode the incoming data stream of 17 different signaling stan- into the legacy digital RGB format. dards. But System I/O doesn’t Decoding can be accomplished entirely in stop there. In addition to the the FPGA or with the assistance of an basic signaling parameters it ASIC or ASSP as appropriate (illustrated supports programmable drive by the combined black/red block). strength and multiple slew rates too. These features make This approach has several important it easy to deal with unantici- Figure 5 - The benefit of programmable drive strength in System I/O advantages. pated PCB behaviors (in • It retains the existing backend of the legacy those not so rare cases where fabrication design essentially unchanged. This bounds reality doesn’t match design theory) as development complexity and reduces risk. illustrated in Figure 5. • The programmable bridge imposes no Some FPGAs, such as the new Spartan™- schedule penalties for numerous iterations. IIE family from Xilinx, even go a step fur- This can be a significant advantage when ther including support for LVDS, BLVDS, you are tasked with integrating new and and LVPECL differential signaling stan- unfamiliar technologies. dards at up to 400 Mbps per pin pair. This enables very high-performance component • Upon completion the design can be interconnection without the need to resort released and in production very quickly. to higher pin count and more expensive How is all this possible? Figure 4 illus- packaging. Further, it reduces system trates some of the standard features and power, lowers EMI, and is much less sensi- IP available in Xilinx FPGAs that make a tive to noise as illustrated in Figure 6. Figure 6 - Noise immunity benefit of LVDS signaling

Spring 2002 Xcell Journal 57 Perspective Digital Displays

Figure 4 also shows a representative sam- whatever, they can be quickly and effi- engine could allow you to support what- ple of the standard controller IP modules ciently integrated. ever your customers require both today available for FPGAs. These are commer- and tomorrow. Another advantage in our example is the cial quality function blocks that are avail- modular architecture for system input. In When used as the heart of the display able to jump-start your design. Much can this design we could support a family of driver circuit, programmable logic can be accomplished with standard IP as solu- configurations to address a variety of geo- give your design the ability to support two tions are available to address most of the graphic and application requirements. or more display options. This can be of topics listed in Table 1. Further, there is no reason why these can- tremendous value in managing the cost For buffers and FIFOs you have a variety not be developed in a serial fashion, for this high dollar bill of materials com- of on-chip memory resources to choose enabling the most important configura- ponent (more than paying for the FPGA from. These include 200 MHz flip-flops, tions to get to market first. And, all that in many cases) or to support a family of true dual ported Block RAM, a Shift would change from configuration to con- products based upon a common core Register Mode (SRL16) capability in the figuration in the core design is the bit- design that increases your accessible mar- FPGA’s fabric Look-up Table (LUT) struc- stream program in the FPGA. ket. In addition, you can use LVDS to route these signals around the board tures, and highly configurable Distributed With programmable logic in the data path (which quite often involves traversing RAM. These features provide high- you have tremendous ability to tailor large tracts of real estate) and thus mini- performance and silicon-efficient solutions encoding/decoding, encryption/decryp- mize system level EMI and the impact of for almost any on-chip memory need. tion, and image processing functionality noise on these critical signals. For clock management Xilinx FPGAs fea- to your precise needs. More importantly, ture four or more Delay-Locked Loops you also have the flexibility to keep up FPGAs are also well suited for crafting a (DLL) per device. These provide the with changes as these needs evolve over unique and attractive user interface for resources to synchronize and connect your time. Take file decryption for streaming your design. They are the very definition system elements together and manage media as an example. Today there are no of GPIO (General Purpose I/O) and can EMI. These DLLs exhibit superior noise firmly established standards, and the stan- implement microcontrollers (or even a immunity compared to PLLs, and they dards that do exist vary widely by geogra- PowerPC microprocessor) for supervisory feature excellent jitter specifications, mak- phy and content provider. And remember, control. In today’s competitive markets ing your job easier. A few examples of Content is king, and that using a pro- the user interface can be one of the most their utility are illustrated in Figure 7. grammable device as the decryption effective ways to differentiate your prod-

Finally, an array of Configurable Logic Blocks (CLB) and internal interconnect resources tie everything together. These are EMI Savings illustrated in Figure 8 and are the underlying fabric that make an FPGA an FPGA.

The FPGA Way

While the benefits of programmable logic are obvious as illustrated in our example, its value can be even greater when lever- Clock Multiplication & Division Clock Phase Synthesis For Use Internally or Externally aged as a foundation element in your Internally or Externally Benefit - Slower Clock on PCB Benefit - Faster State Machines, Double-Edged design. Figure 9 illustrates how our digital Duty Cycle Correction Clocking for DDR/QDR Memories convergence projector might look if it were designed from scratch, only this time the FPGA way. Spartan-IIE Spartan-IIE In this design the flexibility of FPGAs is being leveraged to maximum advantage. Speedup TC2O Clock Mirror Zero-Delay Board Clock Buffer By designing the core logic of the system Zero-Delay Internal Clock Buffer Benefit - Reduce Board Delay, controller into an FPGA component you Benefit - Allows Use of Cheaper Memory Reconstruct Nooisy Backplane Clock gain maximum flexibility in the selection of every other component you require – Figure 7 - Some examples of DLL capabilities be they HSTL, SSTL, LVTTL, LVDS, or

58 Xcell Journal Spring 2002 Perspective Digital Displays

uct from that of your competition, and an systems require ever more connectivity and Its rich features, efficient development flow, FPGA gives you the maximum freedom intelligence. It is no longer good enough to and extensive IP support will simplify your to innovate. have the best widget or display. Now you job and give you a chance to meet aggressive need a more digitally connected and data schedules. The newest generations of devices Finally, your FPGA based solution is manipulating widget or display, one that are cost efficient solutions for almost any never frozen. If a customer comes to you supports the standards and formats in your design. And when made a fundamental part requesting a new feature, a slightly differ- of your architecture from ent capability, or a new con- the beginning, this technol- figuration, you have a plat- ogy can be exploited to form to quickly and effi- ased Interc CL DLL IOB IOB IOB IOB IOB IOB DLL C B on modularize your configura- or n ciently deliver it. When t e I c c e t tions, provide flexibility O B CLB CLB CLB CLB CLB V inevitable bugs and incom- B R ns 2 with critical and costly com- patibilities crop up you can I A 2 ns O M CLB CLB CLB CLB CLB CL ponents, and tailor your not only fix them quickly, B 2 ns I product functionality to you can also update deployed O B CLB CLB CLB CLB CLB CLB B B R R your exact needs. systems in the field. This can I A O M CLB CLB CLB CLB CLB CLB M O greatly reduce support and B B To learn more about digital I I CLB Tiles service costs. And if you ever O B CLB CLB CLB CLB CLB CLB B O • Fast, predictable video and digital conver- B R R interconnect face a supply problem for a I A A I gence technologies, and O M CLB CLB CLB CLB CLB CLB M O system component while in B B how FPGAs can help with production, you have the CLDLLIOB IOB IOB IOB IOB IOB DLL CL them, visit the Emerging flexibility to find and sup- Standards and Protocols port an alternate solution to Figure 8 - FPGA CLBs and interconnect resources (eSP) Web portal at keep your factory running, www.xilinx.com/esp. This your product shipping, and website was developed by revenue coming in. Xilinx as a resource for the digital system target market and geography – and one design community and is specifically target- Conclusion that does it before your competition. ed at dealing with these new and challenging The era of digital convergence is upon us. Programmable logic is an invaluable asset in technologies. To date, segments have been From pictures to e-mail, from music to confronting this challenge. Its inherent flexi- deployed for home networking, Bluetooth, news, the world has gone digital. And bility makes it an ideal mechanism for graft- and digital video technologies, and more are because of this digital explosion today’s ing new functionality into an existing design. on the way.

HyperlAN2 RF Digital 802.11 RF Mixed Signal Ethernet PHY µP or µC 1394 PHY Digital Image Programmable Decoding Processing USB 2.0 PHY

Programmable Display I/O Control A System Display Controller Driver Display RGB Video Input A/D B Converter 1 2 3 µC 4 5 6 7 8 9 * 0 # Figure 9 - Maximizing the value of programmable logic

Spring 2002 Xcell Journal 59 Perspective Digital Convergence DigitalDigital ConsumerConsumer ConvergenceConvergence DemandsDemands ReprogrammabilityReprogrammability

by Robert Bielby Sr. Director, Strategic Solutions Xilinx, Inc. [email protected] Seventeen years ago, Xilinx developed the industry’s first Field Programmable Gate Array (FPGA). The concept was quite simple – using Static Random Access Memory (SRAM) as the basis of the logic fabric, you could instantly develop integrated logic circuits directly on your desktop. The benefits were far reaching, because this technology did away with the risk and delay typically associated with designing custom Application Specific Integrated Circuits (ASICs). While the concept of “user programmable” Not long ago, logic was perhaps first pioneered by enter- prising engineers who used Programmable Read Only Memories (PROMs) as a “pro- the idea of creating an grammable ASIC”, this solution was able to achieve only small levels of integration. ASIC on the desktop The cost efficiency and logic density achieved by using PROMs as custom logic was extremely poor compared to ASICs. was considered a Interestingly, however, the concept of using look-up tables to implement logic functions is actually a basic technology used in novel concept. today’s multi-million gate FPGAs.

60 Xcell Journal Spring 2002 Perspective Digital Convergence

Today, FPGAs have evolved into a main- select an FPGA over an ASIC became other consumer electronics – FPGAs have stream technology because their current common. This proved to be true even in rapidly become a key driver behind the densities and performance compete with cases where it could be demonstrated that digital consumer revolution. custom ASICs. Additionally, designing for an ASIC solution provided a lower overall And reprogrammability, which used to be an FPGA is almost exactly the same as an solution cost than the FPGA. However, considered a liability, is now clearly seen ASIC – your circuit can be described there were practical limits to how great the as a key benefit in not only getting a either by schematic, or by a high-level unit volumes or disparity in price would product to market sooner, but keeping it hardware description language such as become before a design would transition longer in the market by providing the VHDL or Verilog. This description is from FPGA to ASIC. ability to upgrade it and add new features then synthesized for the FPGA with the These fundamental benefits of being first once it’s in the field. But how and why final result being a configuration bit- to market and of risk aversion have proven programmable logic is being used is stream that ultimately programs device to be especially important to the network- sometimes just as interesting as where it’s look-up tables that are interconnected by ing and communications industries – as being used. programmable wires. Just like the look-up demonstrated by the fact that currently tables, the configuration bitstream also ReplayTV – Personal Video Recorder 70% of the $5 billion market for pro- determines the connectivity for the programmable logic is consumed by network- Personal video recorders (PVRs) are per- grammable wires. ing and communications applications. haps one of the most exciting consumer Because the programmability is based FPGAs have been particularly important products to offer new features and capa- upon volatile, SRAM technology, there is in these markets because they have been bilities made possible only by the combi- a requirement to “re-write” the configura- able to keep up with the pace and innova- nation of digital technologies and FPGAs. tion bit stream every time power is tion in those markets and accommodate With a PVR, traditional analog video pro- removed and re-applied to the FPGA. the wide range of new standards that con- gramming is converted to digital using This configuration bit stream is usually tinuously emerge. MPEG 2 encoding and stored directly to contained in an external, memory which Flexibility for the Masses is dedicated for configuration, or by reserving a portion of a main system Moore’s Law, which says that transis- memory with the FPGA configuration tor density of an ASIC will double information. every 18 months due to advances in When FPGAs were first introduced, the semiconductor technology, has fact that they required programming from played a key role in driving larger an external memory source, and that they density FPGAs with greater features lost their configuration once power was and performance. This has in turn removed, was generally considered a lia- continued to fuel the increased demand a hard drive – enabling instant search bility. Fixed ASICs had none of these and consumption of FPGAs in network- access and high quality video imaging. ing and communications applications. requirements or added complexities. And PVRs represent a quantum leap in capa- for the most part, ASICs were still signifi- The advances in semiconductor technolo- bility and quality compared to traditional cantly cheaper than FPGAs – at least on a gy have not only yielded larger and faster videocassette recorders (VCRs). For exam- unit cost basis. FPGAs, they have also yielded FPGAs ple, a PVR such as ReplayTV’s can store However, for applications that shipped a that are 10,000% cheaper than they were as much as 60 hours of programming, relatively low number of units, it could be five years ago! The result is that FPGAs, allowing viewers to watch programming shown that the high non-recurring which were previously practical only for on their personal schedules instead of charges for the ASIC more than offset the prototyping or low volume, high-end those set by broadcasters. applications, are now appearing in some higher unit costs of the FPGA. Because of The ReplayTV also contains an integrated of the hottest, newest high-volume con- these cost constraints, the use of FPGAs 56K-baud modem, which is used to sumer electronics. was historically relegated to the lower vol- download the equivalent of a TV guide ume, less cost sensitive applications that Four years ago, Xilinx developed the that can be searched, sorted, and grouped had large-scale integration requirements. Spartan series family of FPGAs that were like traditional database programs. This Over time, the additional benefits of being optimized for low-cost, high-volume allows for easy recording setup and unique first to market and the ability to fix bugs or applications. The results are impressive; programming search capabilities. This accommodate late specification changes from MP3 players, to DVD writers, digi- modem connection also enables addition- rose in importance, and the decision to tal cameras, digital modems, and a host of al unique capabilities – such as reconfig-

Spring 2002 Xcell Journal 61 Perspective Digital Convergence

sures and the risk of missing the narrow Christmas window of opportunity drove KB Gear Interactive, a manufacturer of Internet communications products and interactive gear for young computer trekkers, to chose the low cost Spartan™ FPGA because of its affordability and design flexibility. As a testament to the viability of FPGAs in such a cost sensitive consumer product – the JAMCAM 3.0, which cost just $99, was sold in over 14,000 retail outlets including Best Buy, Target, K-Mart, WalMart, Circuit City, and a host of other highly recognizable consumer retail outlets. Because KB Gear had designed a toy that had broad appeal and used a Spartan FPGA, they were able to deliver one of the “must have” toys for the 2000 Christmas season on the shelves in time for the Christmas season. Years ago, the thoughts of an FPGA in a $99 kid’s toy would have seemed impossible.

uring the FPGA. The reprogrammable In one case, ReplayTV found itself forced logic is updated simply by downloading a to deal with a condition that caused new bitstream. If the unit is already degraded video quality in a few systems installed in a customer’s home, the bit- already in homes – one of the chips in the stream is downloaded from ReplayTV’s system had an undocumented clock Internet server. This allows bugs to be threshold switching problem that varied fixed even after the customer takes the as a function of lot processing. Because unit home, and lets ReplayTV add new the control signals for this device were features as necessary. Obviously, this generated in the FPGA, it was possible to extends the life of the product too, eliminate the problem by changing the Conclusion because rather than having to replace it as timing of the FPGA-generated signal. Seventeen years ago the idea of creating an market requirements change; the cus- The company responded with a software ASIC on the desktop was considered a tomer simply has the unit’s logic repro- change that was uploaded to all ReplayTV novel concept; they were primarily limited grammed via the modem. systems in the field as soon as it was to prototyping and low volume produc- ReplayTV reprogramming takes place in debugged and certified. Most customers tion. The fact that the FPGAs needed to be the background: each evening the PVR never realized that the change had been programmed every time they were powered automatically downloads TV schedule made; though some may have noticed up was considered both a liability and a information from the company server, improved video quality. A revolutionary risk. Today, because of their lower cost and along with any bug fixes, operating system capability enabled by FPGA programma- high flexibility, FPGAs have found a home updates, or program modifications. The ble technology! in a wide range of applications. Xilinx customer’s unit is improved as he sleeps FPGAs are now used in a wide range of KB Gear – JAMCAM 3.0 without intervention on his part. End users high-volume, cost sensitive applications, Digital Camera are typically never made aware of changes especially those that require reprogramma- or fixes to their systems unless the func- Perhaps one of the least likely places one bility to meet the continuously changing tionality of the PVR changes as new fea- would expect to find an FPGA would be in standards and demands of the new digital tures are added. a toy digital camera. But time to market pres- consumer markets.

62 Xcell Journal Spring 2002 For High-Speed Design, Yo u ’re Better Connected With Xilinx.

Through our XPERTS program, Xilinx certifies SystemIO addresses all aspects of system connectivity many 3rd party design centers specializing in terabit Xilinx provides the most comprehensive SystemIO solution to address applications. By taking advantage of industry-unique features such as the your interface needs ranging from “inside-the-box” to wide area network SelectI/O™-Ultra technology in the Virtex®-II Platform FPGA, Xilinx and its (WAN) applications. XPERTS partners provide the fastest and most flexible high-bandwith solution supporting rapidly evolving connectivity standards. Using Virtex-II 840 Mbps LVDS performance and an abundance of memory and logic resources, Xilinx is able to provide solutions for 10GE MAC, PCI Our XPERTS partners have extensive experience using the popular Xilinx & PCI-X, RapidIO, POS-PHY Level 3 and 4, Flexbus 4, HyperTransport, PCI 32/33, 64/66 and PCI-X cores, and are ready to take on the challenges and other source-synchronous bus standards. of designing with multi-gigabit serial interfaces using the 3.125 Gbps serial I/O technology in the next generation Virtex-II family. With SystemIO and our XPERTS program, you’re better connected with Xilinx.

For more information visit http://www.xilinx.com/xperts/systemio.htm

www.xilinx.com

© 2002, Xilinx Inc. All rights reserved. The Xilinx name, Xilinx logo, and Virtex are registered trademarks. SelectI/O-Ultra is a trademark. The Programmable Logic Company is a service mark of Xilinx Inc. All other trademarks are the property of their respective owners. New Technology Prototyping and Verification FlexBench Tool Suite Relies on Xilinx Silicon by Marco Pavesi Head of Innovative Designs Laboratory Italtel SpA and Software [email protected] System verification is the major bottleneck in the development of contempo- rary and future system-on-a-chip (SoC) Improve your time designs. Increasing numbers of applications that process large quantities of data in real time (such as telecom and video) to market with rapid require verification techniques that run at or near real-time speeds. Delaying your prototyping and system software development until working devices are available is not a viable option in the face of enormous competitive time- verification enabled to-market pressures. by Virtex-II FPGAs and Thus, early hardware/software (HW/SW) co-verification is not just practical – it’s essential. At Italtel SpA, we and our part- ChipScope Integrated ners have developed a superior method of improving system verification confidence Logic Analyzer. through high-speed register transfer level (RTL) prototyping and the Virtex™ family of FPGAs. Prototyping at Real Time Speeds RTL prototyping allows you to run system hardware and software at speeds high enough to hunt and find hidden bugs. Just as important, you can confidently evaluate subjective characteristics, such as audio and video quality. RTL prototyping uses off-the-shelf FPGAs to implement SoC custom logic, as well as test physical, real devices like memories, interfaces, and processors that comprise the other parts of the system to be verified. This strategy enables us to create, in effect, a clone of the SoC and all the parts of system that it interfaces with. We call this

64 Xcell Journal Spring 2002 New Technology Prototyping and Verification

assembling a “demonstrator.” With a To approach real-time system speeds, a our team to create and patent the demonstrator, we can map the hardware modular rapid prototyping tool with new FlexBench concept: and run the application software. RTL pro- interconnection technologies and a novel 1. QuickSwitch™ bus switches from totyping can be roughly divided in two topology had to be developed. Such a tool Integrated Device Technology (IDT), Inc. types, custom and modular: – with single-ended, point-to-point signals – would have a physical speed limit ranging • Custom prototyping is the fastest tech- 2. Mictor™ high-speed connectors from from 80 MHz to 100 MHz. nique, in terms of frequen- Tyco Electronics. cy. FPGAs and other These two technological devices are assembled on a innovations gave our team board expressly designed the means of reconfiguring for the demonstrator to be multiple printed circuit verified. Such a demonstra- boards (PCBs) as needed tor may reach speeds as during the HW/SW co- high as 200 MHz – but it design process. Employing requires several months the reliable and fast-grow- from initial system design ing Xilinx FPGA technolo- to the end of the verifica- gy, we envisaged it was pos- tion process because of the sible to design the unique intrinsic delay of the board FlexBench HW/SW tool fabrication process. suite.

• Modular prototyping is not The FlexBench challenge quite as fast as custom pro- was to create a rapid proto- totyping for verification – typing tool so general in but when it comes to giving Figure 1 - Co-verification solution: Italtel FlexBench hardware with Temento Diaflex software purpose as to become the you the time-to-market industry standard. Taking advantage, it is, by far, the better solu- Given these parameters, three European such a concept and turning it into a high- tion. With modular prototyping, you can companies collaborated for two years to powered tool, however, is quite an under- assemble FPGAs and other devices on design and develop the FlexBench™ mod- taking that requires strategic alliances and general-purpose daughterboards that ular rapid prototyping tool suite: adequate funding. allow you to create a wide range of different demonstrators. Modular prototyping • Italtel SpA, the largest Italian telecom We applied for – and received – start-up is a HW/SW co-development scheme manufacturer, is the leader for hardware funding from the European Commission. based on a set of configurable carrier development. With that funding, we worked in a frenet- boards where daughterboards can be ic manner for two years to gather the inserted and interconnected as necessary • Mistel SpA, another Italian telecom man- expertise and to execute the rapid proto- during the co-design process. ufacturer, supports the hardware effort. typing tool we envisioned. Avoiding the FPIC Dead End • Temento Systems, based in France, is At the hardware level, the FlexBench rapid dedicating its electronic test automation prototyping platform was to be basically a Modular RTL prototyping platforms have (ETA) software resources to the testing of set of complex board designs. Fortunately, intrinsic speed limitations related to modu- SoCs and electronic boards. we had the PCB know-how and related larity, accessibility, and routability. Field resources in-house at Italtel – and valuable programmable interconnect chips (FPICs) Moreover, Oktet Ltd., a design service contributions from Mistel. have been the traditional solution for company based in St. Petersburg, Russia, routability problems. Unfortunately, the was also deeply involved in the develop- On the software side, the development of existing technology trends for FPICs are ment the FlexBench verification system. the computer assisted engineering (CAE) insignificant (in terms of speed and the software we needed was not our area of Putting Together FlexBench Hardware number of I/Os) compared to the skyrock- competency. Therefore, we entered into a eting speed and size of Virtex-II and As the FlexBench project leader, I had partnership with Temento Systems, a com- Virtex-II PRO™ FPGAs. In short, no been searching for a practical means of pany known for its excellent ETA software. modular rapid prototyping platform based modular rapid prototyping in a HW/SW Temento developed the DiaFlex™ soft- on FPIC technology can meet your cus- co-design environment. In 1999, two ware tool we needed to monitor the tomers’ need for speed and time to market. new technologies emerged that enabled FlexBench system in action. See Figure 1.

Spring 2002 Xcell Journal 65 New Technology Prototyping and Verification

Our acquisition of Certify™ RTL parti- converters. Memories are allocated on Integrating DiaFlex Software tioning software from industry-leading small modules, named MiniPlugs, direct- Complementing the FlexBench hardware is Synplicity™ Inc. completed our primary ly inserted into FlexPlugs in order to min- the DiaFlex software tool developed by software tool set. imize interconnect delays. Temento Systems. Dedicated to configuring, Now that we had the boards and the soft- We obtained the FlexBench speed charac- downloading, verifying, and controlling the ware, we had to find the best programmable teristics by interconnecting different FlexBench RPE, the DiaFlex program suite logic devices. It was a short search. In a class FlexPlug modules through the distributed allows you to design the RPE configuration by themselves, Virtex-II Platform FPGAs network of pass-transistors. Each side of a through an intuitive, three-dimensional from Xilinx perfectly fit the needs of our FlexPlug contacts the side of the nearest graphical user interface. Starting from RPE verification engineers: high speed, fast and other FlexPlugs by means of channels. configuration, the DiaFlex application gener- simple compilation, and high capacity. Channel size is configurable, through the ates a flattened description of the platform JTAG port, from 0 to 222 functional definition into a Verilog format, called a VB You can see the FlexBench design chain in wires with 8-bit granularity. Trace length Figure 2. minimization is achieved through a clever three-dimensional architecture. The relatively short trace length of RTL VHDL or Verilog Design QuickSwitch delays (0.1 nanosecond)

FlexBench and the best-in-class set-up and clock-to- Figure 4 - DiaFlex Multi-FPGA Synplicity Certify Configuration Partitioning output parameters of Virtex-II FPGAs Populated FlexMother permits us to achieve 100 MHz clock Per-FPGA Xilinx file. The VB file provides the Certify verifica- P & R speed (and over) on modular systems tion software with an easy view of the RPE populated by up to 18 FPGAs. Downloading resources and connectivity. Moreover, it pro- Connectivity DiaFlex Verification Monitoring The FlexBench rapid prototyping equip- vides direct channel configuration bitstreams . ment (RPE) is composed of a rack, a RPE The Certify program compiles RTL code, backplane (FlexPanel), a software-con- Rapid Prototyping FlexBench and spreads it according to the VB file Equipment trolled clock generator (FlexClock), some description of the RPE. The Certify tool also carrier boards (FlexMothers), and several Figure 2 - FlexBench design chain modules (FlexPlugs and MiniPlugs). FlexMother boards are connected FlexBench Rapid Prototyping at 100 MHz through flexible printed circuits (FlexCable) and through the FlexPanel. As we said earlier, to achieve the speed See Figure 3 to see how the whole Flex edge in RTL prototyping with a modular hardware family interacts to form the tool, the FPIC approach is simply not FlexBench verification system. suitable. A novel technology had to be Figure 4 shows a populat- introduced, based on the speed of IDT’s ed FlexMother. QuickSwitch bus switches. By using pass- transistors, you can select interconnections among neighboring HW modules on multipurpose panels. We built QuickSwitch bus switches and receptacles into the FlexBench mother- boards, which are populated by daughterboards named FlexPlugs. These modules are based on an open standard form factor. Using advanced, off-the-shelf interconnect technology, FlexPlug modules make available up to 888 functional signals. FlexPlugs host active devices, such as Figure 3 - FlexBench the leading edge Virtex-II 6000 Platform reconfigurable proto- FPGA. The FlexPlugs also host power typing system

66 Xcell Journal Spring 2002 New Technology Prototyping and Verification

synthesizes all FPGAs. The FPGAs vides the same functional controls are then placed-and-routed via pro- of a sophisticated logic analyzer. prietary tools to produce FPGA con- With ChipScope ILA, you spend figuration bitstreams. less time verifying chip functionality, and therefore, speed up your The DiaFlex application downloads time to market. all bitstreams to the RPE and provides interactive debugging through a By means of the ChipScope ILA, TemTag™ JTAG PCI board. you get full visibility into the Moreover, the DiaFlex software pro- FlexBench RPE. ChipScope ILA vides diagnostics, reports errors, and lets you see every selected node in analyzes test results. This allows every FPGA used in your design. debugging at the signal name level, This virtually eliminates the need functional testing, and automatic for invasive physical probing of management of IEEE 1149.1 test the FlexBench RPE. With the bench generation. Additionally, the Figure 5 - FlexBench library Xilinx ChipScope ILA solution, DiaFlex program takes complete con- you can perform real-time, on- trol of the FlexClock board. This enables you to configure FlexClock Target FPGA with ILA Cores

parameters: the frequency of clock syn- USER USER FUNCTION FUNCTION thesizers, the selection of global clock Target FPGA with ILA Cores sources, and the control of other tim- ILA ILA USER USER FUNCTION FUNCTION ing functions. USER PC with ChipScope JTAG FUNCTION CONTROL Target FPGA with ILA Cores ILA ILA ILA A Flexible Prototyping Library USER USER USER FUNCTION FUNCTION JTAG FUNCTION CONTROL ILA To perform effective rapid prototyp- ILA ILA ing, you must have a set of FlexPlugs JTAG USER and MiniPlugs. These plugs enable Connection JTAG FUNCTION CONTROL ILA you to interconnect state-of-the-art MultiLINX Cable FPGAs, memories, I/Os, processors, design platforms, and other components of your design. FlexBench chip debugging. Figure 6 shows a function- While Italtel and our affiliates have al representation of how ChipScope ILA designed general-purpose FlexBench facilitates the debugging of a modular modules, design-specific modules FlexBench design. must developed by final OEM customer. This is where the services of a Conclusion company like Oktet Systems can Currently, some functional FlexBench plat- become essential. ChipScope forms have been developed and are being uti- Sixteen general-purpose modules lized in Italtel development and innovation currently comprise the FlexBench projects. Regardless, the FlexBench mission is library. Some of the modules are dis- not to become a proprietary tool, but to played in Figure 5. Figure 6 - ChipScope and FlexBench solution become an industrial standard. A Matter of Observability Italtel/Temento are and will be engaged Xilinx has removed this weakness thanks to in trials with major silicon vendors to Compared with the “observability” you can its Integrated Logic Analysis (ILA) core, a demonstrate and to prove the FlexBench get with emulators, the classic argument solution that provides trigger and trace cap- technology. We believe the versatile against rapid prototyping has been that you ture capability within the FPGA itself. FlexBench model is a major step in rapid can’t “see” what’s going on inside the Implemented by the Xilinx ChipScope™ prototyping and system verification. We design, because invasive physical probing is Analyzer, the ILA core allows real-time are proud to have designed it. To ensure difficult, if not impossible, to accomplish access to any node in the FlexBench chips. best diffusion of this tool, we are now in modular equipment. An easy-to-use graphical user interface pro- researching the best sales channel.

Spring 2002 Xcell Journal 67 New Products Development System Multiprotocol Modular Engineering Solutions Platform Offers Design Flexibility and Faster Time to Market

The Nu Horizons Engineering Solutions Platform presents a cost-effective alternative to single-board tools for developing high-end data communication and server applications.

by Bill Pratt Regional Applications Manager Virtex-II daughtercard Nu Horizons Electronics [email protected] sion cards for multiple solutions, or you can Today’s one-sided trend toward shorter sys- build a total solution in a modular environ- of a total solution. The Horizon Bus has tem development cycles and increasingly ment. The days of purchasing a develop- an aggregate bandwidth of 26 Gbps, and complex designs are driving the need for ment board for a single application are gone. is highly suited for developing solutions more timely system validation. Although for the telecommunications and data net- designers recognize this weighted ratio, and work markets. are turning more and more to Xilinx FPGAs for their designs, they have also The main board, or motherboard (Figure 1), recognized a need for development boards has the following features: that are up to the challenge. • Xilinx XCR3128XL -10PQ VQ100 Nu Horizons Electronics Corp. under- CoolRunner™ CPLD stands this short-cycle/high-complexity • High-density board-to-board connectors design ratio and has introduced a line of for two expansion cards hardware development platform tools that facilitate system verification within an inte- • Dual seven-segment LCD display grated environment. The Nu Horizons • RS-232 level shifter for UART core Engineering Solutions Platforms are based Engineering Support Platform motherboard instantiation on a modular design concept that allows Motherboard the re-use of expansion cards with other • JTAG configuration headers interface expansion cards to create a unique The primary function of the Engineering • Two 44-pin PLCC sockets for Xilinx development evaluation environment. Solutions Platform motherboard is to configuration PROMs provide a high-speed backplane for Modular Design Solution board-to-board data transfers. This back- • Fifty test points The Engineering Solutions Platform solu- plane is called the Horizon Bus. With the • Power management tion consists of up to three boards in a mod- high-density board-to-board connectors, • Reset controller ular environment. With this modularity, you you can evaluate the functions of two may combine a number of different expan- expansion cards, which allows emulation • Status LEDs.

68 Xcell Journal Spring 2002 New Products Development System

Virtex-II Expansion Card V.35 HDLC (high-level data link control). The daughtercard also incorporates an Coupled with the HDLC core from Xilinx, ICS525-02 user-configurable clock chip The Xilinx Virtex™-II expansion card you can turn your Virtex-II FPGA into a from Integrated Circuit Systems Inc. The (Figure 2) is a cost-effective development powerful network engine. The multiproto- ICS525-02 is the most flexible way to board with a broad suite of features. col clock/data transceivers also support generate a wide range of highly accurate Available now is the XC2V1000 FG456 X.21, V.11, RS-232, RS-449, and RS- clock output from a standard crystal or one-million-gate Virtex-II device with the 53W\ serial interfaces. following features as implemented on clock oscillator. You can easily program the Engineering Solutions Platform the ICS525-02 to output a frequency daughtercard: from 1 MHz to 200 MHz by setting a Display bank of switches located on the board. • 16 channels of LVDS interface You may also supply a LVDS clock, as Reset Jumpers, – User-configurable as eight trans- Button Pin Headers well as four other single-ended user mit and eight receive or 16 supplied clocks, for a total of six usable transmit channels CoolRunner clock inputs. XCR3128XL Voltage DB9 RS-232 5 VDC CPLD Regulators • Multiprotocol serial clock/data Conn. Driver Input With the Horizon Bus backplane, the transceivers with auto cable termi- Configuration PROMS Virtex-II daughtercard becomes a very

nation XC18V04 XC18V04 Bus Switch powerful development platform offering up to 26 Gbps throughput and – Certified TBR-1, TBR-2, NET-1, allowing the instantiation of a multi- and NET-2 compliant. Horizon Bus / Daughtercards tude of bus architectures, such as CSIX • 16 megabits of synchronous for telecommunications. NBT SRAM Figure 1 - ESP motherboard block diagram Nu Horizons Electronics Corp. is in the – Flow through and pipelined process of developing new daughter- • Programmable clock from 1 MHz cards for the Engineering Solutions to 200 MHz SSRAM Platform. Future cards include an HTML server/white appliance con- Reset LVDS Header, • Six user clock inputs Button Pin Headers troller and a high-speed AFE (analog • High speed 133-bit at 200 MHz front end) with an Ethernet interface. backplane Virtex-II XC2V1000 Voltage Conclusion MSPC FPGA Regulators • DCI (digitally controlled Chipset The Engineering Solutions Platform impedance). from Nu Horizons Electronics Corp. is DB25 Design Platform for Conn. a modular Virtex-II development envi- High-End Applications ronment that provides designers with Horizon Bus / Daughtercards the hardware necessary to develop, pro- Targeted at high-end data communi- totype, verify, and test their designs cations applications, the Virtex-II Figure 2 - Virtex-II daughtercard block diagram before they are finalized. Intended to daughtercard is applicable to many accelerate the design cycle timeline, the scenarios, including SPI-3 to CSIX Engineering Solutions Platform is a bus interface or offering transparency NBT (no bus turnaround) RAM offers a modular solution that enhances and sim- within high-end networking solutions. The standard packaging for high-speed SSRAM plifies system design and validation 16 channels of high-performance LVDS devices. The Virtex-II daughtercard has 16 processes. Its modularity makes it highly (low voltage differential signaling) provide MB of NBT SSRAM from GSI Technology, functional over many design cycles, thus the capability to prototype high-speed dif- which allows for zero-wait, read-write bus providing a cost-effective alternative to sin- ferential interfaces such as the SPI-3 and utilization. This GSI SSRAM is program- gle-board tools for developing high-end SPI-4 bus technologies. The Receive port mable as FT (flow through) or pipelined, data communication and server applica- includes parallel termination; the Transmit operating as a pipelined synchronous device. tions. The Engineering Solutions Platform side does not require this feature. This means that in addition to the rising- motherboard with the Virtex-II daughter- The multiprotocol clock/data transceivers edge triggered registers that capture input card sells for $999 and is available for with auto cable termination can support signals, the device incorporates a rising-edge immediate shipment. For more informa- multiple protocols such as two channels of triggered output register. tion, please log onto www.nuhorizons.com.

Spring 2002 Xcell Journal 69 Plug in your high-density FPGA. And get ready. You’ve never seen performance like this. Introducing Amplify ® Physical Optimizer™ — the first and only physical synthesis solution for programmable logic. Now you can achieve aggressive performance goals, and save weeks while you’re at it. Easy to learn and use, Amplify delivers better Quality of Results by utilizing both physical and timing constraints during synthesis. As a result, designers are achieving up to 35% performance gains, on or ahead of schedule. Plus, Amplify supports and enhances Team Design. Not only does it manage the physical hierarchy of a design, Amplify optimizes performance, regardless of how a design is allocated across the team. Get in on the outstanding performance. For more information and an evaluation copy, visit www.synplicity.com/amplify.

mable World 2002, and attend our upcoming webcast semi ity at Program nar featuring in Synplic ® ex-II Pro™. Details at w Synplicity Jo mizer and Xilinx Virt ww.synplicity.com/eve ’s hysical Opti nts/xilinx_ev Amplify P ents.html

See us at the Xilinx Programmable World 2002 phone: (408) 215-6000 www.synplicity.com Simply Better Results email: [email protected]

Copyright ©2002 Synplicity, Inc. All rights reserved. Synplicity, the Synplicity ‘S’ logo, Simply Better Results, and Amplify are registered trademarks of Synplicity, Inc.Physical Optimizer is a trademark of Synplicity, Inc. Xilinx and Virtex are registered trademarks of Xilinx, Inc.. New Products Hardware Parallel Cable IV Connects Faster and Better This new high-speed download cable supports ultra-low voltages. by Theresa Vu Product Marketing Engineer which gives you the flexibility to use either Xilinx, Inc. the JTAG (IEEE 1149.1) or Slave Serial [email protected] download mode at the fastest speeds. The small profile of the ribbon cable connector The new Parallel Cable IV downloads data minimizes the need for board space. The more than 10X faster than the previous ribbon cable offers an error-free, quick con- JTAG/Parallel Cable III. Now, you can nect target interface compared to cumber- download to one XC2V8000 Virtex™-II some flying lead wires of Parallel Cable III. FPGA in less than eight seconds. The PCIV is backward compatible with The PCIV features ultra low-voltage the PC III and offers a connector for support for all Xilinx FPGA, flying lead wires. CPLD, System ACE™ MPM Parallel Cable IV connected to PC (multi-package module), and PCIV extends Xilinx leadership ISP (in-system programmable) in pre-engineered configura- PROM devices (see Table 1). tion solutions by offering a fast, simple, low-cost download The PCIV connects to any desk- solution for all Xilinx FGPA, CPLD, top or laptop computer using the standard System ACE MPM, and ISP PROM IEEE 1284-compliant parallel port and devices. The Parallel Cable IV will be draws power directly from the computer available in late March through Xilinx (through the mouse/keyboard port) or an distributors and the Xilinx e-commerce external power supply. site for $95. For more information, see A robust ribbon cable ships with the PCIV, www.xilinx.com/support/programr/cables.htm. Parallel Cable IV connected to external power supply Parallel Cable IV Parallel Cable III Download Speed up to 4 Mbps up to 300 Kbps I/O Voltage Support 1.5V, 1.8V, 2.5V, 3.3V, 5V 2.5V, 3.3V, 5V Download Modes JTAG (IEEE 1149.1) and Slave Serial JTAG (IEEE 1149.1) and Slave Serial Power Supply PC or External Power Supply Target System Board Connections Ribbon Cable and Flying Wires Flying Wires Software Support iMPACT iMPACT

Table 1 - Parallel Cable IV vs. Parallel Cable III Parallel Cable IV with ribbon cable connector

Spring 2002 Xcell Journal 71 Technology Focus IP scc-II Microsequencer – A New Solution for Platform FPGA Designs When your project design is too big for a finite state machine, but a microcontroller would be overkill, try Ponderosa Design’s scc-II microsequencer.

by Aki Niimura Microcontrollers are commonly used to The key architectural benefits of the Consultant implement complex protocols. However, scc-II are: Ponderosa Design they require substantial resources (mem- • Small footprint [email protected] ory, cost, pins, ...), which can be difficult • High-level language support to justify in real-life situations. On the As the complexity of FPGA-based systems • Small code size grows every year, we are asked to imple- other hand, software implementations • Configurable and customizable ment larger, more complex functionality allow designers to cope with mounting within tighter schedules. Furthermore, the logic complexity. They are easy and quick • Capable of handling 16-bit and 32-bit type of design has changed rapidly in to implement and easier to maintain. data types recent years. People used to design an There is a gap, however, between the • Timer (integrated into the core FPGA taking an existing board design, range of design complexity that FSM architecture) often containing asynchronous clocks. methodology can handle and what • Support of interrupt handling Those days are over. You can not design microcontroller-based methodology is • Developing and debugging tools today’s Platform FPGA just by extending good for, as shown in Figure 1. As micro- yesterday’s design practices. New designs controllers become more powerful, the • Utilization of Xilinx Spartan™-II and often require the implementation of com- gap is widening. Virtex™-II devices. plex sequences or communication proto- The scc-II is not just another set of A block diagram of the scc-II is shown in cols. The finite state machine (FSM) is a Figure 2. The core itself requires 400 to 600 well-known design methodology to imple- microcontrollers. We specifically constructed the microsequencer to fill the LUTs, depending on the configuration and ment such sequences. FSM is very effective synthesis constraints. when the sequence is not very complex. gap between low-level FSM solutions However, implementing a and high-level microcontroller designs. How the scc-II Works complex sequence using Complexity scc-II – A Configurable Microsequencer The scc-II employs a stack-based architec- an FSM is not prac- Sequencers have been used in many LSI ture. Stack computers use data stacks to tical and is often evaluate given operations (Figure 3). The Microcontroller projects to implement functions. For difficult to benefits of stack-based architecture are: maintain. example, instructions in a CISC Microsequencer (Complex Instruction Set Computer) • High-level language ready – can execute CPU were often implemented in this way syntax tree directly (called microcode, which is written in a FSM • Simple hardware – easy to understand, proprietary assembly language). By allow- easy to customize Performance ing users to write programs in a high-level Figure 1 - Performance versus language, the scc-II can accommodate a • Small instruction code – most scc-II functional complexity wider range of FPGA applications. instructions are one byte long.

72 Xcell Journal Spring 2002 Technology Focus IP

Another unique aspect of the scc-II architecture is the use of register windows. Register Instruction decoder Program windows are used to pass arguments to a I/O ROM IP function being called. Because the scc-II Work does not use a stack frame in memory to RAM pass arguments, the scc-II does not require Interrupt ALU logic Data stack data memory to run a high-level language Return stack program, thus making the scc-II more Timer attractive for Platform FPGA applications. Programs for the scc-II are almost entirely Figure 2 - scc-II block diagram written in the high-level language SC.

The Language SC y = a + b ALU The scc-II assumes the use of a high-level language. However, existing high-level lan- guages are not designed for microsequencer b applications. Therefore, we developed a a a a + b stripped-down version of C language – SC. push a push b add pop y SC programs do not support “struct” and Figure 3 - How stack computers operate other complex data types, but SC has several enhancements to describe control applications efficiently. Timer, I/O, and debug arithmetic functions (such as averaging) • Larger Block RAM allows larger program features are natively supported in SC. are good candidates for implementation sizes (up to 8 KW). by the scc-II. The following is a code fragment from a • Native multiply operators are supported. project that controls an SDRAM memory. Other target applications include: Case Study – Web on FPGA • Read/write flash, To demonstrate the effectiveness of the void EEPROM, 1-Wire™ scc-II solution, we have developed a Web init_sdram() devices server that uses less than 25% of the { • Interface to I2C, resources of a Spartan-II FPGA while(!eval_cond(DLL_RDY)) { } // wait for DLL is ready RS-232, Ethernet, (XC2S150). The only additional hardware USB1.1, IrDA required beside the FPGA are an Ethernet wait(14); // 286 uS PHY device and a signature ROM (option- outp(SDCMD, SD_PRE); • Command interpreter al). We found that the Spartan-II VoIP repeat(8) { (a block is controlled Development Kit from Insight Electronics outp(SDCMD, SD_AREF); // looping takes 7 cycles through commands) (www.insight-electronics.com) included all } // tRC = 84nS; 20nS * 5 • User interface (such outp(SDCMD, SD_MODE); as keypad, LCD, } touch panel) • Servo controller (some arithmetic operations In the above code fragment, eval_cond(n), required) wait(n), and outp(port) are not function calls, • Design that requires many variants. but they are natively supported by SC. Note that the loop counter of the repeat state- The scc-II and Virtex FPGAs ment is placed in the data stack and not in The Virtex family of FPGAs are true “sys- Figure 4 - WebThermo demo application the register file. tem on a chip” platforms. The advanced scc-II Target Applications technology available in Virtex-II devices the hardware components we needed. Thus, provides further attractive features to the The scc-II can be used in designing func- we decided to use this off-the-shelf board to scc-II, including: tional blocks to perform procedural con- create our Web server design. Figure 4 trol. For example, flow charts or simple • The scc-II can run at 70 MHz or faster. shows a screenshot from a Web server proj-

Spring 2002 Xcell Journal 73 Technology Focus IP

ect called WebThermo. The screen displays – Execution trace log generation nicate with a Virtex FPGA. By substituting the current temperature every minute. the instruction ROM block in the scc-II – Dis-assembler to display current con- Table 1 shows utilization statistics from a design with a JTAG embedded ROM text (on-the-fly/offline) Synplify analysis of the XC2S150 device. block, you can perform several debug com- 2. Ready to try on the board: mands, such as downloading a program WebThermo Usage of XC2S150 Note – JTAG debugger to download program without going through the FPGA backend LUTs 828 (23%) Synplify 7.0 without backend (synthesis + PAR) design process. No signal change is required, as JTAG signals are hidden from 3 for TX, RX buffer, Block RAM 8 of 12 – UART customized for debugging (one 5 for Program your RTL code. can use printf()) BUFTs 320 (18%) Conclusion – “xdl” script to replace ROM contents Table 1 - WebThermo logic size without backend. We have presented a microsequencer, the scc-II, which is new to conventional FPGA Lessons learned: design practices. Unlike other IP cores, the The 2 KB WebThermo program imple- potential of the scc-II is not limited to its ments all Ethernet, TCP/IP, and Web 1. Logic simulation is always the best tool original form. Rather, the scc-II can evolve (HTTP) protocols, as well as Celsius-to- for debugging. to meet each application challenge. One Fahrenheit conversion. At start up, the pro- 2. printf() is a primitive but very powerful avenue we plan to explore is adding Galois gram retrieves a unique 48-bit ID code means for debugging. instructions to the original scc-II core. This from a Dallas 1-Wire device (DS18S20), #ifdef ... #else ... #endif enhancement can help in error correction which is used as an Ethernet MAC address. 3. Use to switch or security applications. For further details on the WebThermo proj- between debug and release. ect, please visit home.pacbell.net/akineko/. 4. A bigger vehicle is needed for debug- Another avenue we plan to pursue is project ging (you may need 2 KB to develop a automation, such as a wizard script that sets Program Development 1 KB program). up project directories and tools – and then One challenge of the scc-II solution is in creates a skeleton version of RTL code, as JTAG debugger providing reasonable program development well as skeleton SC program and header files. and debugging tools. Figure 5 illustrates a The JTAG debugger (jtagdbg) has proved The complete scc-II design solution typical program development flow. In addi- to be a powerful tool to facilitate the debug- is offered by Ponderosa Design tion to key software tools, we wrote many ging process. The JTAG debugger uses the in Sunnyvale, California Please write scripts and templates to automate the Virtex USER1 JTAG command to commu- [email protected] or visit design process. While creating several proj- http://home.pacbell.net/akineko/. ects with the scc-II, we refined the RTL design, as well as the development software and scripts. As a result, they have become mature and stable. Currently the development environment is supported under Unix. It is also possible to port some of the tools to Windows platform using Cygwin from Cygnus (RedHat). The tools are developed assuming that the user’s RTL design is in Verilog HDL. Debugging, Then Debugging Again

Debugging is the biggest challenge in developing an scc-II based design. We are providing several debugging aids: 1. Debugging starts with simulation:

– Three debug instructions (print, $dump, $stop)

– Self-checking embedded in the code Figure 5 - The scc-II program development flow

74 Xcell Journal Spring 2002 Your FPGAs are getting as complex as ASICs.

But are your FPGA tools ASIC enough?

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www.synopsys.com/fpga

See us at the Xilinx Programmable World 2002 ©2002 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All rights reserved. registered ©2002 Synopsys, Inc. Synopsys and the logo are New Product FPGA Synthesis Upgrade to Synopsys FPGA Compiler II Synthesis Tool to Maximize Virtex-II Pro Performance FPGA Compiler II’s unique algorithms aid in designing chips correctly and on time.

register banks to match your latency requirements, and FCII does the rest, mov- Virtex-II Pro Platform FPGAs. FCII coming the registers into the optimal position by Jackie Patterson bines the architecture-specific synthesis to form your pipeline. engine of FPGA Express with advanced Director of Marketing Programs Register retiming is easy to use in FCII. All technologies suitable for ASIC-like design Synopsys, Inc. you have to do is set the retiming variable challenges, as shown in Figure 1. These [email protected] in your script, and FCII will automatically leading-edge capabilities are unique to position your registers in the optimal places When you target Virtex-II Pro™ Platform FPGA Compiler II and not found in any to maximize clock speed. FPGA, you are using one of the best other synthesis tools on the market. FPGAs on the market – and you current_chip my_chip FPGA Compiler II need a high-performance synthe- FPGA Express set_chip_retiming -enable sis tool to match. That’s why Register Retiming • Architecture-Specific and Pipeline Insertion You can also use the FCII graphical Synopsys Inc. is focusing efforts Optimization • Design Wizard Flow interface to invoke retiming, if you on its premier FPGA Compiler .db Output • High Performance QoR Common prefer. Just select Edit->Constraints II™ FPGA synthesis tool and • Built-In Static Timing Synthesis • Schematic Viewer from the menu and check the continuing to hone its support Technology dc_shell • BLIS retiming box in the Xilinx vendor for top-of-the-line programma- Translator options tab. Synopsys full-chip ble logic devices. In 2002, FPGA Figure 1 - FCII adds flexibility to DesignWare Foundation retiming optimizes performance of Compiler II is superceding high-performance synthesis engines. all datapath, control, and random FPGA Express™, which will be logic in the high end of the Xilinx discontinued. line – the Virtex™, Virtex-II, and This article will explain the differences Register Retiming Virtex-II Pro families of devices. between the two synthesis tools, summarize FCII uses sophisticated retiming algo- DesignWare Foundation IP Library key features carried forward from FPGA rithms to boost clock speed automatically. Express to the FPGA Compiler II, and ASIC designers save design time by Retiming works by analyzing all the com- explain how you can upgrade to FPGA reusing components from the Synopsys binational logic in the design, and then Compiler II today. DesignWare Foundation IP library. selecting the optimal register placement to Although some components in the library FPGA Compiler II Has Unique Capabilities meet your design goals. See Figure 2. are also useful for production FPGA FPGA Compiler II (FCII) was developed Retiming can also pipeline your design designs, the biggest benefits come for for high-performance devices such as automatically. Just code in the number of those who are using a Virtex-II Pro device

76 Xcell Journal Spring 2002 New Product FPGA Synthesis

engine you’ve relied on in FPGA Express. Existing Circuit Circuit After FCII Register Retiming This includes: • Support for all Xilinx devices through Virtex-II Pro and beyond FCII improves both datapath and control logic 8.2 • Block Level Incremental Synthesis (BLIS) while preserving 7.5 10.2 9.8 pin-to-pin functionality. clock period = 10 to speed your design cycle time by re- doing only the blocks in the design that Inputs Outputs have changed

Existing Circuit Circuit After FCII Register Retiming • User control of register duplication to pipeline_design eliminate critical paths caused by high fan-out nets FCII allows easy automatic pipelining; 23.0 8.9 4.0 7.3 • Networked licenses on both UNIX and PC insert registers, then apply timing 10 ns period • Integrated schematic viewing and tim- Inputs Outputs Inputs Outputs ing analysis • Full TCL scripting Figure 2 - FCII register retiming optimizes performance. • ROM inference. Upgrading to FPGA Compiler II to prototype an ASIC or SOC. For a pro- Synopsys FCII customers can leverage all FPGA Compiler II is the choice for syn- totype, FCII’s ability to implement the available means to get their designs done thesis of high-performance FPGAs such as DesignWare components in the FPGA correctly and on time. the Virtex-II Pro pf1. provides confidence that the ASIC will Architecture-Specific Synthesis Engine work as planned, because it allows you to To upgrade to FPGA Compiler II, contact verify exactly the same IP that is used in FPGA Compiler II carries forward the your Synopsys account manager or visit the ASIC. same architecture-specific synthesis www.synopsys.com/fpga. Full Flow Support FPGA Compiler II allows designers to take advantage of other high-performance tools for FPGA design and verification. When undertaking large, complex Virtex-II Pro devices, designers need to verify the silicon before it gets into the lab. That process starts with a quick analysis of the source code using the LEDA® HDL checker. The LEDA checker leverages general-purpose rules along with Xilinx-specific rules to alert designers to potential problems and optimization opportunities in the HDL. Then the HDL functionality is verified using a fast simulator such as VCS™ for Verilog or Scirocco™ for VHDL. After the optimization by FPGA Compiler II, designers can use Formality® to formally verify the design, avoiding time-consuming simulation runs. Of course, the timing of Figure 3 - Synopsys design flow the design is comprehensively checked for Virtex-II Pro Platform FPGA through static timing analysis. In this way,

Spring 2002 Xcell Journal 77 Technology Focus Rocket I/O Use Rocket I/O Multi-Gigabit Transceivers to Double Your FPGA Bandwidth Virtex-II Pro Platform FPGAs break open the I/O bottleneck.

by Brian Von Herzen, Ph.D. MGTs Onboard Configurable hardware support is CEO, Rapid Prototypes, Inc. provided for: The Rocket I/O MGTs are shown in a member of Xilinx XPERTS Program – Figure 1, which illustrates the overall • 8B/10B encoding Xilinx Worldwide 3rd Party Certified Design Centers Virtex-II Pro architecture. The MGTs are [email protected] • Disparity control located above and below columns of Block As FPGAs increase in size and performance, RAM, providing close availability of Block • Transmitter and receiver termination I/O resources become the main bottleneck RAMs for ingress and egress FIFOs. As impedance to FPGA performance. Although the effec- many as 16 MGTs are integrated on each • Pre-emphasis tive area of a chip grows as the square of the FPGA above and below the Block RAM feature size, the perimeter I/Os grow only columns. The clock distribution networks • Amplitude control linearly. State of the art designs require can feed these transceivers for low-skew • Loopback testing. higher performance I/O modules. clock alignment between MGTs. These are the essential configurable hard- Rocket I/O In response to this increasing demand on DCM High-Speed Transceiver ware features that enable compliance with I/O resources, Xilinx has developed novel all of the main multi-gigabit signaling stan- I/O structures called Rocket I/O™ multi- dards. You can find more information on gigabit transceivers (MGTs) that enable Virtex-II Pro standards support on the CLB order-of-magnitude increases in I/O per- Xilinx website at www.xilinx.com/partin- formance. The Rocket I/O MGTs double fo/databook.htm. the total I/O bandwidth of the Virtex-II CLB CLB

Processor Block MGTs Speed up FPGA Communications Pro™ family of devices using only a few

percent of the pins. Multipliers and

Block SelectRAM Block Although MGTs have many important CLB applications interfacing to industry stan- With up to 16 MGTs per device, the Virtex- Configurable Logic II Pro achieves an additional 100 gigabits per dard gigabit communications protocols, second of I/O bandwidth in the larger they can serve another important function devices over what is available with the gener- Select I/O - Ultra in boosting the bandwidth available among FPGAs. al-purpose I/O blocks. Rocket I/O MGTs Figure 1 - Virtex-II Pro FPGA architecture, enable multiple gigabit I/O standards and including up to 16 Rocket I/O MGTs Figure 2 shows a data communications maximize performance for FPGA-to-FPGA application requiring two FPGAs. For a communications. Even though Rocket I/O MGTs = Multiple Gigabit Standards typical implementation, half of the I/O MGTs dramatically increase performance for bandwidth is allocated to external links and demanding applications, they are easy The Rocket I/O MGTs have been designed half to the inter-FPGA link. With 800 gen- enough to use for simple FPGA-to-FPGA to be compliant with: eral-purpose I/O pins available, running at communications with special soft macros • Gigabit Ethernet a typical speed of 250 MHz, the pair of such as the Aurora core available from Xilinx. FPGAs can support a pipeline throughput The interface has been simplified to the • 10 Gigabit Ethernet XAUI of 100 gigabits per second. extent that no external resistive termination • Fibre Channel If the 16 bidirectional MGT links are is required with the Rocket I/O MGTs. The added, 16 links x 3.125 gigabits are avail- transceivers can be internally configured to • InfiniBand™ Architecture able in each direction, for another 100 match 50 or 75 transmission lines. • Xilinx Aurora core gigabits per second total. Figure 3 shows

78 Xcell Journal Spring 2002 Technology Focus Rocket I/O

Alternatively, multiple MGTs can be bond- apart using standard PC board transmis- ed together to form a higher-bandwidth sion-line traces. Pre-emphasis improves the FPGA FPGA GPIO only GPIO only 100 Gbps 100 Gbps 100 Gbps interface. The Aurora macro ensures that noise and jitter performance at these high channel-bonded data will appear on the speeds for longer PC traces where disper- Figure 2 - FPGA processing pipeline using same clock cycle at the other end of the sion affects timing and voltage margins. general purpose I/O (GPIO) only communications link. The 8B/10B encod- You can clearly see in Figure 5, which shows ing method is used for the Aurora soft oscilloscope traces at the receiver without macro, giving an effective bandwidth of 10 100 Gbps more inter-FPGA bandwidth from Rocket I/O MGTs pre-emphasis and with 30% pre-emphasis. gigabits per second for a set of four channel- 2VP50 FPGA 100 Gbps 2VP50 FPGA The pre-emphasis enables reliable signal with MGTs with MGTs bonded MGTs between two FPGAs. 100 Gbps 100 Gbps 100 Gbps transmission at 3.125 Gigabits per second

Total of 200 Gbps between FPGAs Pre-Emphasis Goes the Distance over long PC board traces in standard FR-4 PC board material. Transmitter and receiv- Another important feature of the Rocket Figure 3 - FPGA processing pipeline using er termination is provided internally to each Rocket I/O multi-gigabit transceivers and I/O solution is pre-emphasis, which com- MGT, eliminating the need for external ter- general purpose I/O (GPIO) pensates for the filtering effects of FR-4 PC mination of these transmission lines. The board material at gigabit speeds. Pre- termination impedance can be set to 50 emphasis boosts the output levels to com- Differential Pair ohms or to 75 ohms. Virtex-II PRO Virtex-II PRO pensate for the filtering effects of extended Rocket I/O Differential Pair Rocket I/O PCB traces. With pre-emphasis, PCB runs Conclusion MGT MGT of 20 inches or longer can be supported reli- The Rocket I/O MGTs enable high-speed Up to 20 inches of 50 or 75 ohm ably at speeds of 3.125 gigabits per second. PC board transmission line interfaces for Virtex-II Pro Platform FPGAs. Figure 4 shows how two MGTs on separate Standards such as InfiniBand Architecture, Figure 4 - Rocket I/O MGTs configured to pre-emphasize data transmission over PCB FPGAs can be easily linked up to 20 inches Fibre Channel, XAUI, and Gigabit Ethernet traces up to 20 inches long are directly supported. Inter-FPGA commu- No Pre-Emphasis nications are greatly enhanced by Rocket the system diagram for two Virtex II Pro I/O modules and the Aurora soft macro, devices including the Rocket I/O MGTs which enable simple FPGA links with chan- between the devices. With Rocket I/O, the nel-bonded performance of over 10 gigabits total bandwidth available between the two per second. Using pre-emphasis, PCB trace FPGAs increases to 200 gigabits per sec- runs of 20 inches or greater are possible at ond. This extra bandwidth is extremely speeds of up to 3.125 gigabits per second per useful in switching applications that may link. In the larger Virtex-II Pro devices, this require up to 100% internal overhead to represents a factor of two increase in total handle control protocols over and above I/O performance available per FPGA. the datapath requirements. This 2X Clearly, Virtex-II Pro Platform FPGAs with increase is an example of the dramatic I/O Rocket I/O MGTs give you a competitive performance increase available in Virtex-II advantage, both in terms of performance Pro Platform FPGAs. and time to market. Aurora Boosts FPGA-to-FPGA Links 30% Pre-Emphasis The Xilinx XPERTS Program Xilinx has developed a software macro called the Aurora core that provides easy 16- The Xilinx XPERTS program identifies bit and 32-bit interfaces from FPGA-to- engineering firms around the world FPGA using one or more Rocket I/O who have demonstrated significant expertise in developing Xilinx FPGA- MGTs. The Aurora core handles the fram- based electronic products and solutions. ing, synchronization, and channel bonding For more information on how Rapid tasks, allowing you to focus more on their Prototypes Inc. can meet your high- application. A single MGT can provide a performance FPGA application 16-bit or 32-bit FPGA-to-FPGA interface. requirements, please visit The software Aurora core coupled with www.FPGA.com. hard core (implemented in silicon) MGTs Figure 5 -Received signals after 50 inches FR-4 PC can create powerful serial-to-parallel and board material with no pre-emphasis and with parallel-to-serial tranceivers. 30% pre-emphasis in the Rocket I/O MGT.

Spring 2002 Xcell Journal 79 New Products Development Tools New CoolRunner-II CPLD Development Kit An ideal kit for applying CPLD technology to high-performance portable and battery-powered systems.

by Xilinx Staff 1.8V CoolRunner-II device; multiple Insight Electronics recently introduced a options for power supplies, I/O voltages, complete solution for developing designs and clock sources; a JTAG port; 45 user About Insight Electronics and applications based on the new high- I/Os; a prototyping area; a two-digit LCD performance, ultra-low power Xilinx Insight Electronics is a member display; and two push-button switches. CoolRunner™-II CPLD family. The of The Memec Group, the world’s The Xilinx ISE WebPACK™ software Insight CoolRunner-II Development Kit leading distributor of proprietary contains all the development software you enables experimentation with CoolRunner- advanced-technology semiconductors. need, and can be II design con- With 52 divisions in the U.S., downloaded at no cepts, including “Xilinx is pleased to have Insight providing timely support Mexico, Canada, and South America, cost from the Xilinx the investigation Insight is the largest specialty semi- for our breakthrough CoolRunner-II RealDigital CPLDs. website, or is includ- of multiple I/O Through this development kit, users can evaluate the ed in the WebPACK conductor distributor in North and standards, clock unbeatable combination of high performance and version of the kit. South America. Insight focuses its management, line card on leading semiconductor security, and ultra low power that CoolRunner-II devices offer.” “Xilinx is pleased to companies, enabling their sales team CPLD power have Insight provid- – Steve Sharp, senior manager of Silicon Solutions Marketing. and field application engineers to consumption. ing timely support devote their time and resources for our breakthrough “Releasing our CoolRunner-II RealDigital CPLDs,” stat- to mastery of supplier products, CoolRunner-II Development Kit in tan- ed Steve Sharp, senior manager of Silicon processes, and technologies. The dem with the Xilinx CoolRunner-II fam- Solutions Marketing. “Through this company’s value-added services, ily introduction continues Insight’s suc- development kit, users can evaluate the design expertise, inventory manage- cessful development kit introduction unbeatable combination of high perform- ment, logistics, and e-business tools strategy,” said Jim Beneke, director of ance and ultra low power that Technical Marketing at Insight. “This ensure that customers receive the CoolRunner-II devices offer.” approach gives designers immediate products they need, when and access to the devices’ full range of fea- Price and Availability where they need them. For more tures, allowing them to verify the ultra- information, visit the Insight Website Available for order now, Insight’s low power and high performance of the at www.insight-electronics.com. CoolRunner-II Development Kit is priced Xilinx second generation Fast Zero at $95. For more information on this and Power™ (FZP) technology as used in the other Xilinx design kits available from CoolRunner-II family.” Insight, call 888-488-4133, or go to The Insight kit includes the 64 macrocell, www.insight-electronics.com/coolrunner2.

80 Xcell Journal Spring 2002 Real Performance. Real Low-Power. The RealDigital™ CPLD.

The RealDigital CPLD is the breakthrough in Only CoolRunner-II — with Fast Zero Power™ technology high-performance and low-power you’ve been looking for. Shipping right — provides ultra-high performance and ultra-low standby now, the new CoolRunner™-II family of devices are the only CPLDs offering current. It’s fast. It’s cool. It’s available now! a 100% digital core, eliminating power-hungry analog sense amps. FREE downloadable software A real-world feature set for real-world challenges The new CoolRunner-II RealDigital CPLDs are fully supported by the easy-to-use With complete I/O support including HSTL and SSTL, you’ve got the real-world ISE WebPACK™, downloadable FREE via the Internet. Or choose our ISE 4.1i interfacing you need today. Our unique software — the fastest, most advanced 1.8V CORE VOLTAGE CPLD COMPETITIVE CHART Clock Divider means no more dividing the development system in the industry, and part Manufacturer Xilinx Lattice Altera clock off-chip. And the Clock Doubler Device Family CoolRunner-II ispMACH4000C None of the total solution offered only by Xilinx. gives you speeds up to 400 MHz. The new Standby Current <100 µA 2 mA N/A RealDigital CPLDs also provide advanced Clock Divider YES NO N/A Find out more about the RealDigital Clock Doubler YES NO N/A Design Security. A comparison of 1.8V CPLD CPLD, plus get your free CoolRunner-II I/O Standards Support LVTTL, LVCMOS, LVTTL, LVCMOS N/A devices shows CoolRunner-II is still up to 20 HSTL, SSTL resource CD by visiting times less power than our nearest competitor! I/O Banks (max) 4 2 N/A www.xilinx.com/digital today.

www.xilinx.com/digital

© 2002, Xilinx Inc. All rights reserved. The Xilinx name and the Xilinx logo are registered trademarks, CoolRunner, WebPACK are trademarks, and The Programmable Logic Company is a service mark of Xilinx Inc. All other trademarks and registered trademarks are the property of their respective owners. R Virtex-II Pro Platform FPGAs: Introduction and Overview

XCELL (v1.0) January 11, 2002 Advance Product Specification

Summary of Virtex-II Pro Features ¥ 8-, 16-, or 32-bit selectable internal FPGA interface ¥ 8B/10B encoder and decoder ¥ High-performance Platform FPGA solution including ¥50Ω / 75Ω on-chip selectable transmit and receive ter- - Up to sixteen Rocket I/Oª embedded multi-gigabit minations transceiver blocks (based on Mindspeed's ¥ Programmable comma detection SkyRailª technology) ¥ Channel bonding support (two to sixteen channels) - Up to four IBM¨ PowerPCª RISC processor ¥ Rate matching via insertion/deletion characters blocks ¥ Four levels of selectable pre-emphasis ¥ Based on Virtexª-II Platform FPGA technology ¥ Five levels of output differential voltage - Flexible logic resources ¥ Per-channel internal loopback modes - SRAM-based in-system configuration ¥ 2.5V transceiver supply voltage - Active Interconnectª technology - SelectRAMª memory hierarchy PowerPC RISC Core Features - Dedicated 18-bit x 18-bit multiplier blocks - High-performance clock management circuitry ¥ Embedded 300+ MHz Harvard architecture core - SelectI/Oª-Ultra technology ¥ Low power consumption: 0.9 mW/MHz - Digitally Controlled Impedance (DCI) I/O ¥ Five-stage data path pipeline ¥ Hardware multiply/divide unit The members and resources of the Virtex-II Pro family are ¥ Thirty-two 32-bit general purpose registers shown in Table 1. ¥ 16 KB two-way set-associative instruction cache ¥ 16 KB two-way set-associative data cache Rocket I/Oª Features ¥ Memory Management Unit (MMU) ¥ Full-duplex serial transceiver (SERDES) capable of baud - 64-entry unified Translation Look-aside Buffers rates from 622 Mb/s to 3.125 Gb/s (TLB) ¥ 80 Gb/s duplex data rate (16 channels) - Variable page sizes (1 KB to 16 MB) ¥ Monolithic clock synthesis and clock recovery (CDR) ¥ Dedicated on-chip memory (OCM) interface ¥ Fibre Channel, Gigabit Ethernet, 10-Gbit Attachment Unit ¥ Supports IBM CoreConnectª bus architecture Interface (XAUI), and Infiniband-compliant transceivers ¥ Debug and trace support ¥ Timer facilities

Table 1: Virtex-II Pro Field-Programmable Gate Array Family Members CLB (1 CLB = 4 slices = Max 128 bits) Block SelectRAM Rocket I/O PowerPC Maximum 18 X 18 Bit Max Transceiver Processor Array Distributed Multiplier 18 Kbit Block RAM Max Device Blocks Blocks Row x Col Slices RAM Kbits Blocks Blocks Kbits DCMs I/O Pads XC2VP2 4 0 16 x 22 1,408 44 12 12 216 4 204 XC2VP4 4 1 40 x 22 3,008 94 28 28 504 4 348 XC2VP7 8 1 40 x 34 4,928 154 44 44 792 4 396 XC2VP20 8 2 56 x 46 9,280 290 88 88 1,584 8 564 XC2VP50 16 4 88 x 70 22,592 706 216 216 3,888 8 852

©2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

82 Xcell Journal Spring 2002 R General Description

Virtex-II Pro Platform FPGA Technology ¥ SRAM-based in-system configuration - Fast SelectMAPª configuration ¥ SelectRAM memory hierarchy - Triple Data Encryption Standard (DES) secu- - Up to 4 Mbit of True Dual-Port RAM in 18-Kb block rity option (bitstream encryption) SelectRAM resources - IEEE1532 support - Up to 706 Kb of distributed SelectRAM resources - Partial reconfiguration - High-performance interfaces to external memory - Unlimited reprogrammability ¥ Arithmetic functions - Readback capability - Dedicated 18-bit x 18-bit multiplier blocks ¥ Supported by Xilinx Foundationª and Allianceª - Fast look-ahead carry logic chains series development systems ¥ Flexible logic resources - Integrated VHDL and Verilog design flows - Up to 45,184 internal registers / latches with Clock - ChipScopeª Integrated Logic Analyzer Enable ¥ 0.13-µm, nine-layer copper process with 90 nm - Up to 45,184 Look-Up Tables (LUTs) or cascadable high-speed transistors variable (1 to 16 bits) shift registers ¥ 1.5V (VCCINT) core power supply, dedicated - Wide multiplexers and wide-input function support 2.5V VCCAUX auxiliary and VCCO I/O power - Horizontal cascade chain and Sum-of-Products supplies support ¥ IEEE 1149.1 compatible boundary-scan logic - Internal 3-state busing support ¥ High-performance clock management circuitry ¥ Flip-Chip and Wire-Bond Ball Grid Array (BGA) - Up to eight Digital Clock Manager (DCM) modules packages in standard 1.00 mm pitch á Precise clock de-skew ¥ Each device 100% factory tested á Flexible frequency synthesis á High-resolution phase shifting General Description - 16 global clock multiplexer buffers in all parts ¥ Active Interconnectª technology The Virtex-II Pro family is a platform FPGA for designs that - Fourth-generation segmented routing structure are based on IP cores and customized modules. The family - Fast, predictable routing delay, independent of incorporates multi-gigabit transceivers and PowerPC CPU fanout cores in Virtex-II Pro series FPGA architecture. It empowers - Deep sub-micron noise immunity benefits complete solutions for telecommunication, wireless, net- ¥ SelectI/O-Ultraª technology working, video, and DSP applications. - Up to 852 user I/Os The leading-edge 0.13µm CMOS nine-layer copper - Twenty two single-ended standards and process and the Virtex-II Pro architecture are optimized five differential standards for high performance designs in a wide range of densities. - Programmable LVTTL and LVCMOS sink/source Combining a wide variety of flexible features and IP cores, current (2 mA to 24 mA) per I/O the Virtex-II Pro family enhances programmable logic - Digitally Controlled Impedance (DCI) I/O: on-chip design capabilities and is a powerful alternative to mask- termination resistors for single-ended I/O standards programmed gates arrays. - PCI support (designated banks only) - Differential signaling á 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers á Bus LVDS I/O á HyperTransport (LDT) I/O with current driver buffers á Built-in DDR input and output registers - Proprietary high-performance SelectLink technology for communications between Xilinx devices á High-bandwidth data path á Double Data Rate (DDR) link á Web-based HDL generation methodology

Spring 2002 Xcell Journal 83 R Virtex-II Pro FPGAs: Introducton and Overview

Architecture nel can be operated at a maximum data transfer rate of 3.125 Gb/s. Virtex-II Pro Array Overview Each Rocket I/O core implements the following function- Virtex-II Pro devices are user-programmable gate arrays ality: with various configurable elements and embedded cores ¥ Serializer and deserializer (SERDES) optimized for high-density and high-performance system ¥ Monolithic clock synthesis and clock recovery (CDR) designs. Virtex-II Pro implements the following functionality: ¥ Fibre Channel, Gigabit Ethernet, XAUI, and ¥ Embedded high-speed serial transceivers enable data Infiniband compliant transceivers bit rate up to 3.125 Gb/s per channel. ¥ 8-, 16-, or 32-bit selectable FPGA interface ¥ Embedded IBM PowerPC 405 RISC CPU cores provide ¥ 8B/10B encoder and decoder with bypassing option performance of 300+ MHz. on each channel ¥ SelectI/O-Ultra blocks provide the interface between ¥ Channel bonding support (two to sixteen channels) package pins and the internal configurable logic. Most - Elastic buffers for inter-chip deskewing and popular and leading-edge I/O standards are supported channel-to-channel alignment by the programmable IOBs. ¥ Receiver clock recovery tolerance of up to 75 non- ¥ Configurable Logic Blocks (CLBs) provide functional ele- transitioning bits ments for combinatorial and synchronous logic, includ- ¥ 50Ω / 75Ω on-chip selectable TX and RX terminations ing basic storage elements. BUFTs (3-state buffers) ¥ Programmable comma detection associated with each CLB element drive dedicated seg- ¥ Rate matching via insertion/deletion characters mentable horizontal routing resources. ¥ Automatic lock-to-reference function ¥ Block SelectRAM memory modules provide large 18-Kb ¥ Optional TX and RX data inversion storage elements of True Dual-Port RAM. ¥ Four levels of pre-emphasis support ¥ Embedded multiplier blocks are 18-bit x 18-bit dedicated ¥ Per-channel serial and parallel transmitter-to-receiver multipliers. internal loopback modes ¥ DCM (Digital Clock Manager) blocks provide self-cali- brating, fully digital solutions for clock distribution delay ¥ Cyclic Redundancy Check (CRC) support compensation, clock multiplication and division, and PowerPC 405 coarse- and fine-grained clock phase shifting. The PPC405 RISC CPU can execute instructions at a A new generation of programmable routing resources called sustained rate of one instruction per cycle. On-chip Active Interconnect Technology interconnects all of these ele- instruction and data cache reduce design complexity and ments. The general routing matrix (GRM) is an array of rout- improve system throughput. ing switches. Each programmable element is tied to a switch matrix, allowing multiple connections to the general routing PPC405 features include: matrix. The overall programmable interconnection is hierar- ¥ PowerPC RISC CPU chical and designed to support high-speed designs. - Implements the PowerPC User Instruction Set All programmable elements, including the routing resources, Architecture (UISA) and extensions for embedded are controlled by values stored in static memory cells. These applications values are loaded in the memory cells during configuration - Thirty-two 32-bit general purpose registers (GPRs) and can be reloaded to change the functions of the program- - Static branch prediction mable elements. - Five-stage pipeline with single-cycle execution of most instructions, including loads/stores Virtex-II Pro Features - Unaligned and aligned load/store support to cache, main memory, and on-chip memory This section briefly describes Virtex-II Pro features. - Hardware multiply/divide for faster integer arith- Rocket I/O Multi-Gigabit Transceiver Cores metic (4-cycle multiply, 35-cycle divide) - Enhanced string and multiple-word handling The Rocket I/O Multi-Gigabit Transceiver core, based on - Big/little endian operation support Mindspeed’s SkyRail technology, is a flexible parallel-to- ¥ Storage Control serial and serial-to-parallel transceiver embedded core used - Separate instruction and data cache units, both for high-bandwidth interconnection between buses, back- two-way set-associative and non-blocking planes, or other subsystems. - Eight words (32 bytes) per cache line Multiple user instantiations in an FPGA are possible, provid- - 16 KB array Instruction Cache Unit (ICU), 16 KB ing up to 80 Gb/s of full duplex raw data transfer. Each chan- array Data Cache Unit (DCU)

84 Xcell Journal Spring 2002 R Architecture

- Operand forwarding during instruction cache line fill The IOB elements also support the following differential - Copy-back or write-through DCU strategy signaling I/O standards: - Doubleword instruction fetch from cache improves ¥ LVDS and Extended LVDS (2.5V only) branch latency ¥ BLVDS (Bus LVDS) ¥ Virtual mode memory management unit (MMU) ¥ ULVDS - Translation of the 4 GB logical address space into ¥ LDT physical addresses - Software control of page replacement strategy Two adjacent pads are used for each differential pair. Two - Supports multiple simultaneous page sizes ranging or four IOB blocks connect to one switch matrix to access from 1 KB to 16 MB the routing resources. ¥ OCM controllers provide dedicated interfaces between Configurable Logic Blocks (CLBs) Block SelectRAM memory and processor core instruc- CLB resources include four slices and two 3-state buffers. tion and data paths for high-speed access Each slice is equivalent and contains: ¥ PowerPC timer facilities - 64-bit time base ¥ Two function generators (F & G) - Programmable interval timer (PIT) ¥ Two storage elements - Fixed interval timer (FIT) ¥ Arithmetic logic gates - Watchdog timer (WDT) ¥ Large multiplexers ¥ Debug Support ¥ Wide function capability - Internal debug mode ¥ Fast carry look-ahead chain - External debug mode ¥ Horizontal cascade chain (OR gate) - Debug Wait mode The function generators F & G are configurable as 4-input - Real Time Trace debug mode look-up tables (LUTs), as 16-bit shift registers, or as 16-bit - Enhanced debug support with logical operators distributed SelectRAM memory. - Instruction trace and trace-back support In addition, the two storage elements are either edge-trig- - Forward or backward trace gered D-type flip-flops or level-sensitive latches. ¥ Two hardware interrupt levels support ¥ Advanced power management support Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources. Input/Output Blocks (IOBs) Block SelectRAM Memory IOBs are programmable and can be categorized as follows: The block SelectRAM memory resources are 18 Kb of ¥ Input block with an optional single data rate (SDR) or True Dual-Port RAM, programmable from 16K x 1 bit to double data rate (DDR) register 512 x 36 bit, in various depth and width configurations. ¥ Output block with an optional SDR or DDR register and Each port is totally synchronous and independent, offer- an optional 3-state buffer to be driven directly or through ing three “read-during-write” modes. Block SelectRAM SDR or DDR register memory is cascadable to implement large embedded ¥ Bi-directional block (any combination of input and output storage blocks. Supported memory configurations for configurations) dual-port and single-port modes are shown in Table 2. These registers are either edge-triggered D-type flip-flops or Table 2: Dual-Port and Single-Port Configurations level-sensitive latches. 16K x 1 bit 4K x 4 bits 1K x 18 bits IOBs support the following single-ended I/O standards: 8K x 2 bits 2K x 9 bits 512 x 36 bits ¥ LVTTL ¥ LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) ¥ PCI (33 and 66 MHz) 18 X 18-Bit Multipliers ¥ GTL and GTLP A multiplier block is associated with each SelectRAM mem- ¥ HSTL 1.5V and 1.8V (Class I, II, III, and IV) ory block. The multiplier block is a dedicated 18 x 18-bit 2s ¥ SSTL 3.3V and 2.5V, (Class I and II) complement signed multiplier, and is optimized for operations based on the block SelectRAM content on one port. The digitally controlled impedance (DCI) I/O feature auto- The 18 x 18 multiplier can be used independently of the matically provides on-chip termination for each single-ended block SelectRAM resource. Read/multiply/accumulate I/O standard. operations and DSP filter structures are extremely efficient.

Spring 2002 Xcell Journal 85 R Virtex-II Pro FPGAs: Introducton and Overview

Both the SelectRAM memory and the multiplier resource are SAMPLE, IDCODE, and USERCODE non-test instruc- connected to four switch matrices to access the general tions. The EXTEST, INTEST, and HIGHZ test instructions routing resources. are also supported. Global Clocking Configuration The DCM and global clock multiplexer buffers provide a Virtex-II Pro devices are configured by loading the bit- complete solution for designing high-speed clock schemes. stream into internal configuration memory using one of the following modes: Up to eight DCM blocks are available. To generate deskewed internal or external clocks, each DCM can be used to elimi- ¥ Slave-serial mode nate clock distribution delay.The DCM also provides 90, 180, ¥ Master-serial mode and 270-degree phase-shifted versions of its output clocks. ¥ Slave SelectMAP mode Fine-grained phase shifting offers high-resolution phase ¥ Master SelectMAP mode adjustments in increments of 1/256 of the clock period. Very ¥ Boundary-Scan mode (IEEE 1532) flexible frequency synthesis provides a clock output frequen- A Data Encryption Standard (DES) decryptor is avail- cy equal to a fractional or integer multiple of the input clock able on-chip to secure the bitstreams. One or two triple- frequency. For exact timing parameters, see Virtex-II Pro DES key sets can be used to optionally encrypt the con- Platform FPGAs: DC and Switching Characteristics. figuration data. Virtex-II Pro devices have 16 global clock MUX buffers, with The Xilinx System Advanced Configuration Enviornment up to eight clock nets per quadrant. Each clock MUX buffer (System ACE) family offers high-capacity and flexible can select one of the two clock inputs and switch glitch-free solution for FPGA configuration as well as program/data from one clock to the other. Each DCM can send up to four storage for the processor. See DS080, System ACE of its clock outputs to global clock buffers on the same edge. CompactFlash Solution for more information. Any global clock pin can drive any DCM on the same edge. Readback and Integrated Logic Analyzer Routing Resources Configuration data stored in Virtex-II Pro configuration The IOB, CLB, block SelectRAM, multiplier, and DCM ele- memory can be read back for verification. Along with the ments all use the same interconnect scheme and the same configuration data, the contents of all flip-flops/latches, access to the global routing matrix. Timing models are distributed SelectRAM, and block SelectRAM memory shared, greatly improving the predictability of the perform- resources can be read back. This capability is useful for ance of high-speed designs. real-time debugging. There are a total of 16 global clock lines, with eight avail- The Xilinx ChipScope Pro Integrated Logic Analyzer (ILA) able per quadrant. In addition, 24 vertical and horizontal cores and Integrated Bus Analyzer (IBA) cores, along with long lines per row or column, as well as massive secondary the ChipScope Pro Analyzer software, provide a complete and local routing resources, provide fast interconnect. solution for accessing and verifying user designs within Virtex-II Pro buffered interconnects are relatively unaffected Virtex-II Pro devices. by net fanout, and the interconnect layout is designed to minimize crosstalk. Horizontal and vertical routing resources for each row or column include: ¥ 24 long lines ¥ 120 hex lines ¥ 40 double lines ¥ 16 direct connect lines (total in all four directions) Boundary Scan Boundary-scan instructions and associated data registers support a standard methodology for accessing and configuring Virtex-II Pro devices, complying with IEEE standards 1149.1 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II Pro device will continue to function while executing non-test boundary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Virtex-II Pro Test Access Port (TAP) supports BYPASS, PRELOAD,

86 Xcell Journal Spring 2002 R IP Core and Reference Support

IP Core and Reference Support ¥ Memory cores (Flash, SRAM, and more) ¥ Peripheral cores (UART, IIC, and more) Intellectual Property is part of the Platform FPGA solution. In addition to the existing FPGA fabric cores, the list below ¥ Networking cores (ATM, Ethernet, and more) shows some of the currently available hardware and software intellectual properties specially developed for Virtex- Software Cores II Pro by Xilinx. Each IP core is modular, portable, Real- ¥ Boot code Time Operating System (RTOS) independent, and ¥ Test code CoreConnect compatible for ease of design migration. Refer to www.xilinx.com for the latest and most complete ¥ Device drivers list of cores. ¥ Protocol stacks Hardware Cores ¥ RTOS integration ¥ Bus Infastructure cores (arbiters, bridges, and more) ¥ Customized board support package

Virtex-II Pro Device/Package Combinations and Maximum I/Os

Offerings include ball grid array (BGA) packages with 1.0 The Virtex-II Pro device/package combination table (Table mm pitch. In addition to traditional wire-bond interconnects, 3) details the maximum number of I/Os for each device flip-chip interconnect is used in some of the BGA offerings. and package using wire-bond or flip-chip technology. The use of flip-chip interconnect offers more I/Os than is ¥ FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). possible in wire-bond versions of the similar packages. Flip- chip construction offers the combination of high pin count ¥ FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). and excellent power dissipation. ¥ BF denotes flip-chip fine-ptich BGA (1.27 mm pitch).

Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os (Advance Information) User Available I/Os Package Pitch (mm) Size (mm) XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP50 FG256 1.00 17 x 17 140 140 FG456 1.00 23 x 23 156 248 248 FF672 1.00 27 x 27 204 348 396 FF896 1.00 31 x 31 396 556 FF1152 1.00 35 x 35 564 692 FF1517 1.00 40 x 40 852 BF957 1.27 40 x 40 564 584

Spring 2002 Xcell Journal 87 For digital video, Spartan®-IIE is the clear choice.

The new Spartan-IIE FPGAs deliver over 20 billion The eSP Web Portal . . . a Unique Designer’s Resource MACs/s, giving you the DSP performance required The Xilinx eSP web portal gives you all the support you could wish for for high-resolution digital images. Together with as standards continue to rapidly change. advanced signaling standards including LVDS, Simply log on to xilinx.com/esp and HSTL and SSTL, you’ve got the speed you need you’ll get immediate access to reference for digital video processing. boards, system block diagrams, a full spectrum of technology & stan- From Picture to Pixel, the Complete Solution dards tutorials, and much more. You’ll soon see why eSP is one of the Through capture, process and display, Spartan-IIE FPGAs bring the total most successful websites of its kind. solution into focus. Encryption IP, operating at high speed Visit www.xilinx.com/spartan2e/dvt today and find out video rates, offers a new level of security protecting every pixel. why Spartan-IIE FPGAs are the clear choice for digital And the desktop programmability of Spartan-IIE FPGAs video design. solves your time-to-market pressures as design cycles get shorter.

The Programmable Logic CompanySM www.xilinx.com/spartan2e/dvt

® 2001 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx and Spartan are registered trademarks, WebPACK ia a trademark and The Programmable Logic Company is a service mark of Xilinx, Inc. Reference FPGAs

Xilinx FPGA Product Selection Matrix

CLB (1 CLB = 4 slices = Max 128 bits) Block SelectRAM Rocket I/O™ PowerPC™ Maximum 18 x 18 Bit Max Transceiver Processor Array Distributed Multiplier 18 Kbit Block RAM Max Device Blocks Blocks Row x Col Slices RAM Kbits Blocks Blocks Kbits DCMs I/O Pads

XC2VP2 4 0 16 x 22 1,408 44 12 12 216 4 204 XC2VP4 4 1 40 x 22 3,008 94 28 28 504 4 348 XC2VP7 8 1 40 x 34 4,928 154 44 44 792 4 396 XC2VP20 8 2 56 x 46 9,280 290 88 88 1,584 8 564 XC2VP50 16 4 88 x 70 22,592 706 216 216 3,888 8 852

CLB Resources BLK RAM CLK Resources I/O Features Speed System Gates (see note 1) (Row X Col) Array CLB Number of Slices Logic Cells (see note 2) CLB Flip-Flops Max. Distributed RAM Bits # Block RAM Blocks Block RAM Bits # Dedicated Multipliers (min/max) DLL Frequency # DLL's Synthesis Frequency Phase Shift Digitally Controlled Impedance Number of Differential I/O Pairs Max. I/O I/O Standards Commercial Speed Grades (slowest to fastest) Industrial Speed Grades (slowest to fastest) Serial PROM Family Config. Memory (Bits) Virtex-II Family — 1.5 Volt .15um Eight Layer Metal Process XC2V40 40K 8 x 8 256 576 512 8K 4 72K 4 24/420 4 DCM DCM YES 44 88 LDT-25, LVPECL-33, -4 -5 -6 -4 -5 0.4M XC2V80 80K 16 x8 512 1,152 1,024 16K 8 144K 8 24/420 4 DCM DCM YES 60 120 LVDS-33, LVDS-25, -4 -5 -6 -4 -5 0.6M XC2V250 250K 24 x16 1,536 3,456 3,072 48K 24 432K 24 24/420 8 DCM DCM YES 100 200 LVDSEXT-33, LVDSEXT-25, -4 -5 -6 -4 -5 1.7M XC2V500 500K 32 x 24 3,072 6,912 6,144 96K 32 576K 32 24/420 8 DCM DCM YES 132 264 BLVDS-25, ULVDS-25, -4 -5 -6 -4 -5 2.8M XC2V1000 1M 40 x 32 5,120 11,520 10,240 160K 40 720K 40 24/420 8 DCM DCM YES 216 432 LVTTL, LVCMOS33, -4 -5 -6 -4 -5 4.1M XC2V1500 1.5M 48 x 40 7,680 17,280 15,360 240K 48 864K 48 24/420 8 DCM DCM YES 264 528 LVCMOS25, LVCMOS18, -4 -5 -6 -4 -5 5.7M XC2V2000 2M 56 x 48 10,752 24,192 21,504 336K 56 1008K 56 24/420 8 DCM DCM YES 312 624 LVCMOS15, PCI33, PCI66, -4 -5 -6 -4 -5 7.5M XC2V3000 3M 64 x 56 14,336 32,256 28,672 448K 96 1728K 96 24/420 12 DCM DCM YES 360 720 PCI-X, GTL, GTL+, HSTL I, -4 -5 -6 -4 -5 10.5M XC2V4000 4M 80 x 72 23,040 51,840 46,080 720K 120 2160K 120 24/420 12 DCM DCM YES 456 912 HSTL II, HSTL III, HSTL IV, -4 -5 -6 -4 -5 15.7M XC2V6000 6M 96 x 88 33,792 76,032 67,584 1056K 144 2592K 144 24/420 12 DCM DCM YES 552 1104 SSTL21, SSTL211, -4 -5 -6 -4 -5 21.9M XC2V8000 8M 112 x 104 46,592 104,832 93,184 1456K 168 3024K 168 24/420 12 DCM DCM YES 554 1108 SSTL3 I, SSTL3 II -4 -5 -4 29.1M Virtex-E Family — 1.8 Volt .18um Six Layer Metal Process XCV50E 72K 16 x 24 768 1,728 1,536 24K 16 64K NA 25/350 8 YES YES NA 88 176 -6 -7 -8 -6 -7 0.6M XCV100E 128K 20 x 30 1,200 2,700 2,400 37.5K 20 80K NA 25/350 8 YES YES NA 98 196 -6 -7 -8 -6 -7 0.9M XCV200E 306K 28 x 42 2,352 5,292 4,704 73.5K 28 112K NA 25/350 8 YES YES NA 142 284 LVTTL, LVCMOS2, -6 -7 -8 -6 -7 1.45M XCV300E 412K 32 x 48 3,072 6,912 6,144 96K 32 128K NA 25/350 8 YES YES NA 158 316 LVCMOS18, PCI33, -6 -7 -8 -6 -7 1.88M XCV400E 570K 40 x 60 4,800 10,800 9,600 150K 40 160K NA 25/350 8 YES YES NA 202 404 PCI66, GTL, GTL+, -6 -7 -8 -6 -7 2.7M XCV600E 986K 48 x 72 6,912 15,552 13,824 216K 72 288K NA 25/350 8 YES YES NA 256 512 HSTL I, HSTL III, HSTL IV, -6 -7 -8 -6 -7 3.97M XCV1000E 1,569K 64 x 96 12,288 27,648 24,576 384K 96 384K NA 25/350 8 YES YES NA 330 660 SSTL3 I, SSTL3 II, -6 -7 -8 -6 -7 6.6M XCV1600E 2,188K 72 x 180 25,920 34,992 51,840 486K 144 576K NA 25/350 8 YES YES NA 362 724 SSTL21, SSTL211, BLVDS, -6 -7 -8 -6 -7 8.4M XCV2000E 2,542K 80 x 120 19,200 43,200 38,400 600K 160 640K NA 25/350 8 YES YES NA 402 804 LVDS, LVPECL -6 -7 -8 -6 -7 10.2M XCV2600E 3,264K 92 x 138 25,392 57,132 50,784 793.5K 184 736K NA 25/350 8 YES YES NA 402 804 -6 -7 -8 -6 -7 13M XCV3200E 4,074K 104 x 156 32,448 73,008 64,896 1014K 208 832K NA 25/350 8 YES YES NA 402 804 -6 -7 -8 -6 -7 16.3M Virtex-EM Family — 1.8 Volt .18um Six Layer Metal Process XCV405E 1.31M 40 x 60 4,800 10,800 9,600 150K 140 560K NA 25/350 8 YES YES NA 202 404 Same As -6 -7 -8 -6 -7 3.43M XCV812E 2.54M 56 x 84 9,408 21,168 18,816 294K 280 1120K NA 25/350 8 YES YES NA 278 556 Virtex-E -6 -7 -8 -6 -7 6.52M Spartan-IIE Family — 1.8 Volt .18um Six Layer Metal Process XC2S50E 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/320 4 YES YES NA 84 182 LVTTL,LVCMOS2, LVCMOS18, -6 -7 -6 0.6M XC2S100E 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/320 4 YES YES NA 86 202 PCI33, PCI66, GTL, GTL+, -6 -7 -6 0.9M XC2S150E 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/320 4 YES YES NA 114 263 HSTL I, HSTL III, HSTL IV,SSTL3 I, -6 -7 -6 1.1M XC2S200E 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/320 4 YES YES NA 120 289 SSTL3 II,SSTL2 I,SSTL2 II, AGP-2X, -6 -7 -6 1.4M XC2S300E 300K 32 x 48 3,072 6,912 6,144 96K 16 64K NA 25/320 4 YES YES NA 120 329 CTT, LVDS, BLVDS, LVPECL -6 -7 -6 1.9M Spartan-II Family — 2.5 Volt .22/.18um Six Layer Metal Process XC2S15 15K 8 x 12 192 432 384 6K 4 16K NA 25/200 4 YES YES NA NA 86 LVTTL, LVCMOS2, -5 -6 -5 0.2M XC2S30 30K 12 x 18 432 972 864 13.5K 6 24K NA 25/200 4 YES YES NA NA 132 PCI33 (3.3V & 5V), -5 -6 -5 0.4M XC2S50 50K 16 x 24 768 1,728 1,536 24K 8 32K NA 25/200 4 YES YES NA NA 176 PCI66 (3.3V), GTL, GTL+, -5 -6 -5 0.6M ISP ISP ISP ISP ISP XC2S100 100K 20 x 30 1,200 2,700 2,400 37.5K 10 40K NA 25/200 4 YES YES NA NA 196 HSTL I, HSTL III, HSTL IV, -5 -6 -5 OTP0.8M OTP OTP OTP OTP XC2S150 150K 24 x 36 1,728 3,888 3,456 54K 12 48K NA 25/200 4 YES YES NA NA 260 SSTL3 I, SSTL3 II, SSTL2 I, -5 -6 -5 1.1M XC2S200 200K 28 x 42 2,352 5,292 4,704 73.5K 14 56K NA 25/200 4 YES YES NA NA 284 SSTL2 II, AGP-2X, CTT -5 -6 -5 1.4M Note: 1. System Gates include 20-30% of CLBs used as RAM Important: Verify all Data with Device Data Sheet 2. A Logic Cell is defined as a 4 input LUT and a register DCM – Digital Clock Management

Spring 2002 Xcell Journal 89 Reference FPGAs

Xilinx FPGA PackageXilinx Options Configuration and User Storage I/O Solutions

User Available I/Os Density Number Memory Package Pitchof (mm) Size (mm) XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP50 FG256 1.00 17 x 17 140 140 FG456 1.00 23 x 23 156 248 248 FF672 1.00 27 x 27 204 348 396

FF896 1.00 31 x 31 396 556 Components space Min board FF1152 1.00 35 x 35 564 692 System ACE CF up to FF1517 1.00 40 x 40 852 8 Gbit 2 25 2 BF957 1.27 40 x 40 564 584 cm No JTAG Unlimited Yes Yes Yes 30 Mbit/secCompactFlash

System ACE

MPM

Virtex-II (1.5V) Virtex-E (1.8V) V-EM Spartan-IIE (1.8V) Spartan-II (2.5V) XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E XCV405E XCV812E XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

Pins Body Size I/O’s 88 120 200 264 432 528 624 720 912 1104 1296 176 176 284 316 404 512 660 724 804 804 804 404 556 182 202 263 289 329 86 132 176 196 260 284 PQFP Packages (PQ) 208 28 x 28 mm 146 146 146 146 146 132 140 140 140 140 240 32 x 32 mm 158 158 158 158 158 158 158 HQFP Packages (HQ) 240 32 x 32 mm 158 158 VQFP Packages (VQ) 100 14 x 14 mm 60 60 TQFP Packages (TQ) 144 20 x 20 mm 102 102 86 92 92 92 Chip Scale Packages — wire-bond chip-scale BGA (0.8 mm ball spacing) 144 12 x 12 mm 88 92 92 94 94 94 86 92 BGA Packages (BG) — wire-bond standard BGA (1.27 mm ball spacing) 352 40 x 40 mm 196 260 260 432 40 x 40 mm 316 316 316 560 42.5 x 42.5 mm 404 404 404 404 404 404 404 575 31 x 31 mm 328 392 408 728 35 x 35 mm 456 516 FGA Packages (FT) — wire-bond fine-pitch thin BGA (1.0 mm ball spacing) 256 17 x 17 mm 182 182 182 182 182 FGA Packages (FG) — wire-bond fine-pitch BGA (1.0 mm ball spacing) 256 17 x 17 mm 88 120 172 172 172 176 176 176 176 176 176 176 176 456 23 x 23 mm 200 264 324 284 312 202 263 289 329 196 260 284 676 27 x 27 mm 392 456 484 404 444 404 680 40 x 40 mm 512 512 512 512 860 42.5 x 42.5 mm 660 660 660 900 31 x 31 mm 512 660 700 556 1156 35 x 35 mm 660 724 804 804 804 FFA Packages (FF) — flip-chip fine-pitch BGA (1.0 mm ball spacing) 896 31 x 31 mm 432 528 624 Note: Virtex-II packages FG456 and FG676 are footprint compatible. 1152 35 x 35 mm 720 824 824 824 Virtex-II packages FF896 and FF1152 are footprint compatible. 1517 40 x 40 mm 912 1104 1108 Important: Verify all Data with Device Data Sheet BFA Packages (BF) — flip-chip fine-pitch BGA (1.27 mm ball spacing) Numbers indicated in the matrix are the maximum number of user 957 40 x 40 mm 624 684 684 684 684 I/O’s for that package and device combination. Xilinx Home Page http://www.xilinx.com/support/support.htm http://www.xilinx.com Xilinx IP Center Xilinx Online Support http://www.xilinx.com/ipcenter/index.htm

590 Xcell Journal Spring 2002 Spring 2002 C32X 00184 ./ . 0 6- 1 7-0416 16 16 4 4 4 16 -10 -12 -7-10 -7-10-12 -7-10 4 7.5 -6-7-10 -7-10 -6-7-10 6 -5-7-10 6 164 5 108 68 3.3 36 18 3.3 3 3.3 18 18 -7-10 3.3 3 3 18 3.3/5 -6-7-10 -7-10 -7-10 3 6 3.3/5 -5-7-10 -7-10 -5-7-10 48 3.3/5 5 -5-7-10 5 256 3.3/5 192 48 6000 5 128 XCR3256XL 48 117 2.5/3.3 3000 72 64 48 18 XCR3128XL 36 18 2.5/3.3 32 1500 18 3 2.5/3.3 3 XCR3064XL 3 2.5/3.3/5 750 2.5/3.3 -10 XCR3032XL -7 2.5/3.3/5 18 -7 90 2.5/3.3/5 -5-7-10 288 3 CoolRunner XPLA3—3.3 Volt 90 2.5/3.3/5 5 6400 -4-5-7 -4-5-7 90 144 XC95288XL -7 4 72 4 90 3200 4 192 XC95144XL 36 -3-4-5-7 1600 2 1 1.8/2.5/3.3 3.5 117 72 800 1 XC9572XL 1.8/2.5/3.3 1.8/2.5/3.3 36 1.8/2.5/3.3 XC9536XL 90 1.8/2.5/3.3 1.8/2.5/3.3 288 1.8/2.5/3.3 XC9500XL Family —3.3 Volt 90 6400 1.8/2.5/3.3 90 144 XC95288XV 72 90 3200 XC95144XV 36 1600 XC9572XV 800 XC9536XV XC9500XV Family —2.5 Volt CC1 100 1 4 15182533 ./././. 20 6 6- 1 - 1 3 17 3 17 -7-10 17 3 16 3 -6-7-10 -7-10 4 17 16 6 -6-7 -6-7-10 3 17 -10-12 4 4 6 -7-10-12 3 270 -5-6-7 1.5/1.8/2.5/3.3 17 -5-7 -10 -12 1.5/1.8/2.5/3.3 7.5 4 40 3 -7-10-12 -6-7 240 5 512 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 7.5 -4-5-7 12000 40 -4-6 2 384 -4-6-7 260 184 4 1.5/1.8/2.5/3.3 XC2C512 1.5/1.8/2.5/3.3 9000 4.5 40 -3-4-6 220 1 2 256 3.5 100 1.5/1.8/2.5/3.3 64 XC2C384 1.5/1.8/2.5/3.3 6000 1.5/1.8/2.5/3.3 1 40 1.5/1.8/2.5/3.3 3.3 40 128 33 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 64 XC2C256 3.3 3000 40 1500 32 XC2C128 750 XC2C64 3.3/5 3.3/5 XC2C32 48 CoolRunner-II Family —1.8 Volt 512 48 12000 384 XCR3512XL 9000 XCR3384XL Xilinx CPLDProductSelectionMatrix PRODUCT SELECTIONMATRIX

System Gates

Macrocells

Product terms per Macrocell

Input Voltage Compatible

Output Voltage Compatible Features I/O Max. I/O I/O Banking Min. Pin-to-Pin Logic Delay (ns) motn:Verify allDatawithDevice SheetandProduct Availability with yourlocalXilinxRep Important: Speed

324 256 FBGA Packages (FG) — wire-bond FinelineBGA(1.0mmballspacing) 256 BGA Packages (BG)—wire-bond standard BGA(1.27mmballspacing) 280 144 48 Chip ScalePackages (CS)—wire-bond chip-scale BGA(0.8mmballspacing) 56 Chip ScalePackages (CP)—wire-bond chip-scale BGA(0.5mmballspacing) 144 100 TQFP Packages (TQ) 100 64 44 VQFP Packages (VQ) 208 PQFP Packages (PQ) 44 PLCC Packages (PC) Commercial Speed Grades (fastest to slowest)

75x1. m3 43 43 63 33 33 36 36 34 34 34 34 17.5 xmm Industrial Speed Grades 3x2 m202020270 240 212 212 184 260 220 212 212 164 164 192 192 80 108 80 118 64 118 100 192 192 117 173 173 33 173 118 120 23 xmm 33 108 84 192 17 xmm 68 117 27 xmm 117 117 180 172 164 81 16 xmm 72 36 12 xmm 36 117 117 52 36 81 168 72 34 34 20 xmm 14 xmm 168 16 xmm 34 34 12 xmm 12 xmm 28 xmm

Body Size (fastest to slowest) m4 345 33 48 6 Xmm m 63 63 640 36 38 36 38 36 7 x7mm Global Clocks Clocking Product Term Clocks per Function Block PACKAGE OPTIONSANDUSERI/O XC9536XV XC9500XV XC9572XV

XC95144XV

XC95288XV

XC9536XL XC9500XL XC9572XL

XC95144XL

XC95288XL

XCR3032XL CoolRunner XPLA3 XCR3064XL

XCR3128XL

XCR3256XL

XCR3384XL Reference XCR3512XL

Xcell Journal XC2C32

XC2C64 CoolRunner II

XC2C128

XC2C256

XC2C384 CPLDs

91 XC2C512 Reference Development Tools

Xilinx Software

Feature ISE WebPACK ISE BaseX ISE Foundation ISE Alliance

Platform PC PC PC/UNIX PC/UNIX Device Support Virtex Series Up to 300K (Virtex E and Virtex II) Up to 300K ALL ALL Spartan Series Spartan-II Series ALL ALL ALL XC4000 Series No 4KE & Newer 4KE & Newer 4KE & Newer CoolRunner Series ALL ALL ALL ALL XC9500 Series ALL ALL ALL ALL Design Planning Modular Design No Sold as an Option Sold as an Option Sold as an Option Educational Services Yes Yes Yes Yes Design Services Yes Yes Yes Yes Support Services Web Only Yes Yes Yes Design Entry Schematic Editor (Gate & Block Level HDL) Yes Yes PC Only No HDL Editor Yes Yes Yes Yes State Diagram Editor Yes Yes PC Only No CORE Generator No Yes Yes Yes Xilinx System Generator for Simulink No Sold as an Option Sold as an Option Sold as an Option Synthesis FPGA Express No Yes PC Only No Xilinx Synthesis Technology (XST) Yes Yes Yes No Synplify/Pro Integration No Yes PC Only PC Only Leonardo Integration Yes Yes Yes Yes ABEL CPLD CPLD CPLD (PC Only) No Implementation Tools iMPACT Yes Yes Yes Yes FloorPlanner Yes Yes Yes Yes Xilinx Constraints Editor Yes Yes Yes Yes Timing Driven Place & Route Yes Yes Yes Yes Timing Improvement Wizard No Yes Yes Yes Board Level Integration IBIS Models Yes Yes Yes Yes STAMP Models Yes Yes Yes Yes LMG SmartModels Yes Yes Yes Yes Verification HDL Bencher Yes Yes PC Only No ModelSim Xilinx Edition (XE) ModelSim XE Starter Included ModelSim XE Starter Included ModelSim XE Starter Included ModelSim XE Starter Included (See www.xilinx.com for more information) (ModelSim XE Sold as an Option) (ModelSim XE Sold as an Option) (ModelSim XE Sold as an Option) (ModelSim XE Sold as an Option) Static Timing Analyzer Yes Yes Yes Yes Chipscope ILA No Sold as an Option Sold as an Option Sold as an Option FPGA Editor with Probe No Yes Yes Yes ChipViewer Yes Yes Yes Yes XPower (Power Analysis) Yes Yes Yes Yes 3rd Party Simulator Support Yes Yes Yes Yes IP/CORE For more information on the complete list of Xilinx IP products, visit the Xilinx IP Center at http://www.xilinx.com/ipcenter

92 Xcell Journal Spring 2002 Reference Configuration

Xilinx Configuration Storage Solutions Memory Density Number of Components space Min board Compression FPGA Config. Mode Multiple Designs Storage Software Removable IRL Hooks Max Config. Speed Media Non-Volatile

System ACE CF up to 8 Gbit 2 25 cm2 No JTAG Unlimited Yes Yes Yes 30 Mbit/sec CompactFlash

System ACE MPM 16 Mbit 1 12.25 cm2 Yes SelectMAP (up to 4 FPGA) Up to 8 No No Yes 152 Mbit/sec AMD Flash Memory 32 Mbit Slave-Serial (up to 8 FPGA chains) 64 Mbit

System ACE SC 16 Mbit 3 Custom Yes SelectMAP (up to 4 FPGA) Up to 8 No No Yes 152 Mbit/sec AMD Flash memory 32 Mbit Slave-Serial (up to 8 FPGA chains) 64 Mbit

I/O Voltage FPGA PD8 VO8 SO20 PC20 PC44 VQ44 Core Voltage 2.5V 3.3V I/O OTP Configuration PROMs for Spartan-II/IIE Voltage XC17S50A XC2S50E Y Y Y 3.3V Y Y

Density PD8 VO8 SO20 PC20 PC44 VQ44 Core Voltage 2.5V 3.3V XC17S100A XC2S100E Y Y Y 3.3V Y Y In-System Programming (ISP) Configuration PROMs XC17S200A XC2S150E Y Y Y 3.3V Y Y XC18V256 256Kb Y Y Y 3.3V Y Y XC17S200A XC2S200E Y Y Y 3.3V Y Y XC18V512 512Kb Y Y Y 3.3V Y Y XC17S300A XC2S300E Y 3.3V Y Y XC18V01 1Mb Y Y Y 3.3V Y Y XC17S15A XC2S15 Y Y Y 3.3V Y Y XC18V02 2Mb Y Y 3.3V Y Y XC17S30A XC2S30 Y Y Y 3.3V Y Y XC18V04 4Mb Y Y 3.3V Y Y XC17S50A XC2S50 Y Y Y 3.3V Y Y One-Time Programmable (OTP) Configuration PROMs XC17S100A XC2S100 Y Y Y 3.3V Y Y XC17V01 1.6Mb Y Y Y 3.3V Y Y XC17S150A XC2S150 Y Y Y 3.3V Y Y XC17V02 2Mb Y Y Y 3.3V Y Y XC17S200A XC2S200 Y Y Y 3.3V Y Y XC17V04 4Mb Y Y Y 3.3V Y Y XC17V08 8Mb Y Y 3.3V Y Y XC17V16 16Mb Y Y 3.3V Y Y

Xilinx Home Page Xilinx Education Center http://www.xilinx.com http://www.xilinx.com/support/education-home.htm

Xilinx Online Support Xilinx Tutorial Center http://www.xilinx.com/support/support.htm http://www.xilinx.com/support/techsup/tutorials/index.htm

Xilinx IP Center Xilinx WebPACK http://www.xilinx.com/ipcenter/index.htm http://www.xilinx.com/sxpresso/webpack.htm

Spring 2002 Xcell Journal 93 Reference IP/Cores itches itches switches orage yer uters, switches nsmission channel frastructure of Fiber Channel of Fiber Channel T, and Ethernet s local loop, DSLAM, PBX s local loop, DSLAM, PBX ards, rtouters, switches IP routers SONET, and Ethernet mmunication, data storage Bridges, switches, links WAN Network adapters, routers, DSLAMs Network adapters, routers, multiplexers Digital broadcast, transmitter microwave Line card: routers & optical switches terabit Line card: routers & optical switches terabit ror correction, wireless, DVB, Satellite data link Channel coding in telecom/wireless, broadcast Broadcast, wireless LAN, cable modem, xDSL, nets, satellite com,uwave TV digital Broadcast, wireless LAN, cable modem, xDSL, nets, satellite com,uwave TV digital X.25, POS, cable modems, relay switches, frame video conferencing over ISDN X.25, POS, cable modems, relay switches, frame video conferencing over ISDN 3G base stations, broadcast, wireless LAN, modem, cable xDSL, satellite com, uwave re Bluetooth applications II Ethernet switched,hub, NICS II Ethernet ode fiber optic devices, Networking, Broadband, SOHO, Home networking, storage, 1-256 bits wide cell length, header length with ITU-T I.363 for AAL3/AAL4 with ITU-T I.363 for for L2CAP, LHP, HC1, voice support M11 interfaces, RMON and Etherstate statistics routers, switches, printers, NIC full duplex, CRC-16/32, 8/16-bit address insertion/deletion Compliant with ATM Forum IMA, Forum ATM Compliant with prog. groups & links, driver SW Compliant ATM Forum IMA, Forum ATM Compliant prog. groups & links, SW driver available Conforms to ETSI EN 300 421 v1.1.2, selectable convolutional code rate Separate generator and verifier blocks, generator Separate AAL5 compat with ITU-T I.363 for ATM, RFC1619 (IP&IPX) POS, and verification, 16/32 bit FCS generation stats Compliant with ANSI X9.52,Compliant with or two independent 64-bit keys 128-bit key Secure co 16/32-bit frame seq,16/32-bit frame 8/16-bit addr insert/delete, flag/zerop insert/detect DVB-RCS compliant, 9Mbps, rate, data sizes and frame switchable code rates Er Block & convolutional support. features. param 3GPP, UMTS, GSM, DVB compliant Implementation Example Xilinx LogiCORE V-II 40% 104 XC2V1000 FG456-4 Line card: routers & optical switches terabit XilinxXilinx LogiCORE LogiCORE V-II V-II VE VE 15% 55% 104 104 XC2V1000 FG456-4 XCV50E-8 Line card: routers & optical switches terabit Xilinx LogiCORE V-II 33% 104 XC2V6000 FF1152-4 endor NameType IP Virtex-II Virtex Spartan-II Spartan Occupancy MHz Device Features Key Application Examples Function V Communication & Networking BUFE-based Multiplexer Slice3G FEC Package Convolutional DecoderTurbo 3GPP Compliant Convolutional EncoderTurbo 3GPP Compliant DecoderTurbo 3GPP 8b/10b Decoder8b/10b EncoderADPCM 1024 Channel XilinxADPCM 16 Channel XilinxADPCM 256 ChannelADPCM 512 Channel LogiCOREADPCM 768 Channel Xilinx LogiCOREADPCM Speech Codec, 32 Channel (DO-DI-ADPCM32) V-IIADPCM Speech Codec, 64 Channel (DO-DI-ADPCM64) V-II LogiCORE V Xilinx VAssembler (CC-201) XilinxCell V-II Xilinx sysonchipCell Delineation (CC-200) VConvolutional Encoder LogiCORE AllianceCOREConvolutional Encoder LogiCORE LogiCORE Amphion (CC-130)Verifier and CRC10 Generator Xilinx S-II V-II V-II V-II Xilinx Amphion V-II AllianceCORE Amphion (CC-131)Verifier and CRC32 Generator V V 80% V-II V AmphionDES V LogiCORE AllianceCORE AllianceCORE 65% DES Cryptoprocessor AmphionTriple DES - LogiCORE S-II V AllianceCOREDES Cryptoprocessor V-II 40 V-II S-II AllianceCOREDistributed Sample Descrambler V-II V-II 60 VDistributed Sample Descrambler V V-II Paxonet VDistributed Sample Scrambler V V Paxonet Paxonet XC2V500 V S-II Paxonet 62% AllianceCORE S-IIDVB Satellite Modulator Core XC2V250 AllianceCORE S-II 87% 61% AllianceCORE DecoderDVB-RCS Turbo TILAB AllianceCORE 25 Board Evaluation Ethernet (10/100 Mbps) MAC Fast Xilinx 66 27Access Controller Ethernet (10/100 Mbps) Media Fast inSilicon AllianceCORE 1 BRAM V and Receiver Cores Transmitter V 1 BRAM 89%Flexbus 4 Interface Core, 3GPP specs, V 16-Channel (DO-DI-FLX4C16) LogiCORE 2 Mbps, 100 BER=10-6 for 1.5dB SNR Paxonet AllianceCORE XC2V500 VFlexbus 4 Interface Core, Paxonet 4-Channel (DO-DI-FLX4C4) XC2V500-5 TILAB 100 XC2V500Flexbus 4 Interface Core, 16 1-Channel (DO-DI-FLX4C1) V-II TILAB 89% AllianceCORE V PCM CodecG.711 AllianceCORE Xilinx inSilicon Compliant w/ 3GPP, AllianceCORE puncturing XC2V1000 TILAB PCM CompressorG.711 V S AllianceCORE 50 XC2V1000 V MemecCore Xilinx PCM ExpanderG.711 S-II S AllianceCORE S XCV150-6 MemecCore XilinxHDLC Controller Core, 32 Channels S-II LogiCORE S AllianceCORE AllianceCORE 22% V 3GPP/UMTS compliant, S-IIHDLC Controller Core, IMT-2000, Single Channel 2Mbps data 44% AllianceCORE V S Industry std 8b/10b en/decode for serial data transmission VATM 67%IMA-32 Inverse Multiplexer for LogiCORE iCODING XC2V500-5 V-II G.726, 43% G.727, Industry std 8b/10b en/decode for serial data transmission 32 duplex channels VATM 20IMA-8 Inverse Multiplexer for LogiCORE S-II S G.726, S-II V 60 G.727, 2% 64 duplex channels AllianceCOREInterleaver Deinterleaver V-II S-II 40Wireless In 3G V V 29Interleaver/De-interleaver V-II S-II 10% V-II S G.721, 93% V 723, S-II 726,Addressable MemoryIPlogiCAM Internet Protocol Content S 726a, 727, 144 727a, S u-law, a-law S-II XCS30-4 S-IIT1 FramerMT1F XC4005XL-1 V Decoder, Codec, Viterbi Turbo S 26 Convolutional Enc G.721, XC4010XL-9 723, Channel Model S-II TILABTransmission 726,Noisy 48 726a, S 90% 727, 727a, u-law, 14% a-law XCS30-4 PARSER:Analyzer and Data Extractor Bit Stream G.721, Xilinx S 723, S Physical layer 726, Xilinx 726a, 14% 727, XCV50-6 Dual Speed 10/100 Mbps Ethernet MACPE-MACMII Mindspeed 727a,Wireless Infrastructure 3G u-law, S AllianceCORE a-law 20% Physical layer Xilinx 50 74 Xilinx Error correction, Mindspeed wireless XC2S150-6 G.721, 39% XC2V40 AllianceCORE 723, 9% Octet wide operation, 726, HEC compute,POS-PHY Level 3 Link Layer Interface Core, 48 Channel (DO-DI-POSL3LINK48A) Octet wide operation, 726a, cell scrambling 74 DECT,VOIP,Wireles HEC verification, 727, Xilinx LogiCORE cell scrambling 727a, 79% and verifier blocks, generator Separate LogiCORE 31% compatible u-law, a-law 94POS-PHY L3 Link Layer Interface, AllianceCORE 16-Ch (DO-DI-POSL3LINK16) DECT,VOIP,Wireles 45–70 Alcatel LogiCOREPOS-PHY L3 Link Layer Interface, 104 4-Ch (DO-DI-POSL3LINK4) TILAB XCV150-4 V-II LogiCORE 27% V-II V 200 25POS-PHY L3 Link Layer Interface, XCV50-6 2-Ch (DO-DI-POSL3LINK2) code rate, 54% LogiCORE 12% gen. vectors, AllianceCORE CMSTR length customizable VPOS-PHY L3 Link Layer Interface, XCV50-6 DECT,VOIP, Single Channel cordless telephony V XC2S100-6 V TILAB XCV50-4 200 AllianceCORE XC2V3000 FG676-5 S-IIPOS-PHY L3 Physical Layer Interface (DO-DI-POSL3PHY) TILAB V-II XilinxWireless Infrastructure 200 3G 69 XCV50-6POS-PHY L4 Multi-Channel Interface (DO-DI-POSL4MC) DECT,VOIP, k from 3 to 9, cordless telephony S-II puncturing from 2/3 to 12/13 V XC2V1000 FG456-5 S-II XC520-4 AllianceCOREPPP8 HDLC Core CC318f V V S XC2V1000 FG456-5 AllianceCORE adapter c ATM DECT,VOIP, Xilinx adapter cards, cordless telephony ATM Reed-Solomon Decoder ro S-II V LogiCORE ITU-T I.432. data width, IEEE 802.3 compliant RMON, Param S-II MIBs stats, cell & header length Xilinx M Reed-Solomon Decoder V XC2V2000-5 S-II Xilinx ITU-T I.432. S-II data width, Param 9% cell & header length VirtualReed-Solomon Encoder DECT,VO BOOST Lite Bluetooth Baseband Processor NewLogic AllianceCORE V-II V 73% 33 XC2V1000-4 Compliant to Bluetooth v1.1, BQB qualified softwa Xilinx IP Selection Guide

94 Xcell Journal Spring 2002 Reference IP/Cores ation ications ation tal camera, scanners edded systems appliance, industrial control JPEG, MPEG, H261 designs add-in boards, CPCI, Embedded add-in boards, CPCI, Embedded CPCI,Embedded,hiperf video,gb ethernet CPCI,Embedded,hiperf video,gb ethernet CPCI,Embedded,hiperf video,gb CPCI, Embedded, hiperf video, gb ethernet deo phone, Set-top box, PDA display deo editing, digital camera, scanners Communication, embedded systems TV, HDTV, color imaging, color video TV, HDTV, color imaging, color video TV, HDTV, color imaging, color video TV, HDTV, color imaging, color video Video editing,Video digital camera, scanners Comm systems, SAN, clustered servers, image, video phone, color laser printers Automotive, network, home automation Ultra 3 SCSI/Fibre Ch RAID,Ultra multi-port Gb Embedded systems, 8-bit processing apps. Scanners, Printers, Handhelds, Mass Storage High speed embedded systems, audio, video Audio/Video recording and editing equipment Audio/Video speed interface to memory and encryption engines, high end video Server,Embedded,gb ethernet,U320 SCSI,Fibre Ch,RAID cntl,graphics Server,Embedded,gb t JPEG, MPEG, H.26X r, 4-16 char display Embedded systems interface t, verified with Routers, switches, backplane, control plane, data path, embedded sys, high 1-64 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide 1-256 bits wide Motorola's RapidIO bus functional model v1.4 8-bit processor,ALU, 8 bit 16 bit stack pointer, 33 opcodes, 4 addr. Modes, 2 user opcodes v2.2 comp, assured PCI timing, 3.3/5-V,0-waitstate, friendly CPCI hot swap PC Compliant with USB1.1 spec.,VCI bus, Supports CRC, Performs Supports 1.5 Mbps & 12 v2.2 comp, assured PCI timing, 3.3/5-V,0-waitstate, friendly CPCI hot swap v2.2 comp, assured PCI timing, 3.3/5-V,0-waitstate, friendly CPCI hot swap v2.2 comp, assured PCI timing, 3.3/5-V,0-waitstate, friendly CPCI hot swap v2.2 comp, assured PCI timing, 3.3/5-V,0-waitstate, friendly CPCI hot swap PC boards, PC boards, PC PC boards, 33 MHz PCI initiator and target IF,3.3 V PCI-X at 33-66 MHz,33 MHz PCI initiator and target IF,3.3 V PCI at 0-33 MHz 3.3 DCT & IDCT, one clock cycle per sample. as DCT 38 MHz when operated Baud rate generator for 13 common baud rates, generator Baud rate I/O ports, parallel prog. timer/counters Conforms to ISO/IEC Baseline 10918-1, 4 quantization tables, 4 Huffman tables. Stallable Includes PCI32 board, drive development kit, class and customer education 3-day training PCI-X 1.0 comp, 64/32-bit, 66 MHz PCI-X initiator and target IF,PCI 2.2 comp, 64/32-bit, PCI-X 1.0 comp, 64/32-bit, 66 MHz PCI-X initiator and target IF,PCI 2.2 comp, 64/32-bit, Supports CAN 2.0A, 2.0B, error handling, stuff bit generation, SRC, individual acceptance filtering RISC implementation,ALU, 8 bit 8 bit control, 32 bit I/O, bit timer/counters, 16 SFR I/F, ext. memory I/F 33 MHz PCI initiator and target IF,3.3 V PCI-X at 33-66 MHz,33 MHz PCI initiator and target IF,3.3 V PCI at 0-33 MHz 3.3 Device Features Key Application Examples Implementation Example Occupancy MHz endor NameType IP Virtex-II Virtex Spartan-II Spartan Function V USB 1.1 Device Controller MemecCore AllianceCORE V-II V S-II 21% 12 XC2V1000-5 Video & Image Processing Video XF-UART Asynchronous Communications Core XF-UART Bus Interfaces Standard MemecCore AllianceCORE V-II V S Phy Layer (DO-DI-RIO8-PHY)RapidIO 8-bit port LP-LVDS 15% Xilinx 50 LogiCORE V-II XCS20-4 generator and baud rate UART YUV2RGB Color Space Converter 24%Basic Elements 250 XC2V1000 FG456-5 RapidIO Interconnect v1.1 complian Xilinx Serial data communic LogiCORE V S-II 12% 65 XC2S100 Microprocessors, (continued) & Peripherals Controllers Timer/CounterOPB (16450,OPB UART 16550) LiteOPB UART WDTOPB ModulePF3100 PC/104-Plus Reconfigurable R8051 RISC MicroControllerR80515 High-speed 8-bit RISC MicrocontrollerSPISynchronous DRAM ControlleruEBX Reference and Development Platform DerivationuPCI Reference and Development PlatformV8-uRISC 8-bit RISC Microprocessor AllianceCORE CASTXF8250 UART V-II Xilinx Interface Peripheral XF8255 Programmable XF8256 Multifunction Microprocessor Support Controller Xilinx AllianceCORE Display Interface Keyboard XF8279 Programmable MemecCore NMI Serial Interface Master-Only LogiCORETwo-Wire XF-TWSI CAST Serial Interface Master-SlaveTwo-Wire AllianceCOREXF-TWSI-MS NMI LogiCORE Xilinx V-II MemecCore V AllianceCORE MemecCore VAutomation AllianceCORE NMI V-II V AllianceCORE AllianceCORE MemecCoreArbiter AllianceCORE Xilinx AllianceCORE MemecCore LogiCORECAN Bus Interface R3.0 V AllianceCORE AllianceCORE AllianceCORE S-II Bus SlaveEP100 PowerPC V-II V Bus MasterEP201 PowerPC LogiCORE V S-II N/A (DO-DI-PCIX64-VE)Virtex-E PCI-X 64/66 Interface for V V V-II S-II N/A V V Xilinx V S-II MemecCore 56% V S Xilinx S-IIPCI32 Single-Use License for Spartan (DO-DI-PCI32-SP) XC2V1000 FG256 S-II AllianceCORE S-II Interface Design Kit (DO-DI-PCI32-DKT)Virtex PCI32 42 S-II LogiCORE 89% Interface,Virtex PCI32 IP Only (DO-DI-PCI32-IP) S S 76% LogiCORE S 125 S XilinxPCI64 & PCI32, IP Only (DO-DI-PCI-AL) V-II NA 125 Interface Design Kit (DO-DI-PCI64-DKT)Virtex 10PCI64 NA 46% 24% XCV200E-8 Xilinx 64% 34 Interface,Virtex PCI64 V IP Only (DO-DI-PCI64-IP) Sci-worx 5% * Eureka NA PC/104 & PC/104+ devlopment board LogiCORE Eureka Virtex-II 59 NA 8 S-II VE 125 AllianceCORE 8 Xilinx 137 Xilinx LogiCORE Virtex-II XCS20-4 AllianceCORE XC2S150-6 AllianceCORE * V-II 125 TILABTransform1-D Discrete Cosine Xilinx LogiCORE S NA LogiCORETransform Discrete Cosine XCV50-42-D DCT/IDCT Forward/Inverse Xilinx Virtex-II XCS20-4 XCV50-6 XCS05-4 V V NATransform Discrete Cosine DCT/IDCT Forward/Inverse V AllianceCORE V-II V 59% V-II DECODERFASTJPEG_BW Xilinx LogiCORE S-II S-II Virtex-II S-II DECODERFASTJPEG_C * LogiCOREFIFO, Interfaces through OPB to MicroBlaze Vkeyboard char 8 lockout, 2-key rollove S-II n-key V Bundled in the MicroBlaze Development KitTransform Discrete Cosine S-II FIDCT Forward/Inverse 10 inSilicon 30% V-II Internet SJPEG CODEC V-II S S LogiCORE S-II V S-II ControllerVideo logiCVC - Compact AllianceCORE V 66 Code GeneratorTime Longitudinal Bundled in the MicroBlaze Development Kit V 12% V-II Interfaces NMI's MicroEngines to EBX bus 12X faster, I2C-like, SRF I/F multi master fast/std. 6% modes S-II SRGB2YCrCb Color Space Converter * XCS10-4 S S-II Interfaces NMI's MicroEngines to PCI bus TILABRGB2YCrCb Color Space Converter Core V SDRAM refresh, S-II customizable 66 Bundled in the MicroBlaze Development Kit XilinxRGB2YUV Color Space Converter Core Virtex-II XCV300E-8 66 S 6% V 7% Bit set/reset supportYCrCb2RGB Color Space Converter * AllianceCORE S-II S XC2S200 PQ208-6 YCrCb2RGB Color Space Converter XC2V1000 FG456-5 LogiCORE S-II BARCO-SILEX 66 66 6 - 7% 7% AllianceCORE BARCO-SILEX V-II xylon Processor applications BUFE-based Multiplexer Slice XC2V1000 FG456-5 S XC2V1000 FG456-5 Processor applications V V-II 66 DELTATEC AllianceCORE Multiplexer SliceBUFT-based 66 33 * V Xilinx PerigeeBinary Counter V-II AllianceCORE V 86% AllianceCORE S-II XC2V1000 FG456-5 Interfaces through OPB to MicroBlazeBinary Decoder Xilinx Processor applications appl XC2V1000 FG456-5 PCI ethernet/graphics S-II DC to 625K baudBit Bus Gate V AllianceCORE PC104 applications LogiCORE 29 PerigeeBit Gate XCV50-6 Emb inSilicon Processor applications Bit Multiplexer Embedded systems using SDRAMs Xilinx LogiCORE V VBus Gate AllianceCORE AllianceCORE 77%Bus Multiplexer Embedded systems XC2S100-6 V S-IIComparator LogiCORE V RegisterFD-based Parallel 78 67% S-IIFD-based Shift Register Xilinx V Embedded systems 2 priority classes - strong/weak, V Networking, access counters communications, S-II processor apps MUXFour-Input V Xilinx 78% Latch 73LD-based Parallel S S-II S-II XCV200-6 Converter 35%Parallel-to-Serial LogiCORE V S-II 56 12%RAM-based Shift Register LogiCORE 22%Register S V-II XC2V1000-4 88 S-II S 49% MUXThree-Input V-II 85 202 Xilinx MUX XC2V1000-4 VTwo-Input 16% 53% Xilinx DCT for 8X8, 75% 16X16, V 65 IDCT IEEE1180-1990 complian Serial communications XC2V250-4 Conforms to ISO/IEC Baseline 10918-1, S-II Xilinx color, multi-scan, LogiCORE Gray-Scale purpose bus arbitration General 80 XCV100E-8 XCV100-4 S-II Conforms to ISO/IEC Baseline 10918-1, 20 Gray-Scale 15% LogiCORE Xilinx Xilinx V-II Xilinx XC2S30 LogiCORE Xilinx V-II Single & double panel, support, 70 LCD/CRT SMTPE/EBU compliant, Xilinx 4 gray, PAL/NTSC, 256 colors lock-on external video reference Xilinx V LogiCORE XCV400E-8 XC2S30 XCV100E-8 LogiCORE V-II V X PCI-X 64/100 Interface for Virtex-II (DO-DI-PCIX64-VE)Virtex-II PCI-X 64/100 Interface for Xilinx LogiCORE V-II 30% 100 XC2V1000 FG456-5

Spring 2002 Xcell Journal 95 Reference IP/Cores PHY layer PHY layer PHY layer ATM PHY layer ATM PHY layer ATM DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps DSP, Math, Arithmetic apps Data transmission, wireless DSP, Math, Arithmetic apps. DSP, Math, Arithmetic apps. High capacity ATM switches ATM High capacity switches ATM High capacity switches ATM High capacity switches ATM High capacity X.25, Relay, Frame B/D-Channel Embedded systems, professional audio, video Networking, edge and access, Switches and routers L/MMDS, broadcast equip, wireless LAN, cable modem, xDSL, sat com, nets uwave 3G base stations, broadcast, wireless LAN, cable modem, xDSL, satellite com, uwave Broadcast, wireless LAN, cable modem, xDSL, nets, satellite com,uwave TV digital ISDN PRA links, mux equip, satellite com, digital PABX, high-speed computer links ISDN PRA links, mux equip, satellite com, digital PABX, high-speed computer links 1-256s bit wide 1-256s bit wide MPHY, HEC processing, round robin polling, ind. receiver transmitter ATM Intel 8XC152 Global Serial Channel, Serial Comm., HDLC apps, telecom Std or cust coding, 3-12 bit width, up to 4095 symbols with 256 check symb Protocol conversion from UTOPIA L2 Pb (RACE BLNT), L2 Pb (RACE Protocol conversion from UTOPIA 8/16 bit operation ATM 32-bit input/coeff width, 1024 taps, 1-8 chan, polyphase, online coeff reload Full IEEE-754 compliance, pipelines, 4 precision real format support Single Full IEEE-754 compliance, pipelines, 4 precision real format support Single Full IEEE-754 compliance, pipelines, 4 precision real format support Single Solution requires SPEEDAnalyzer ASIC,Solution requires SPEEDAnalyzer 2.5 Gbps fdx wire speed; net processor (NPV) Supports ATM Forum UTOPIA Level-3. UTOPIA Forum ATM cell format,Supports Configurable data width Level-3. UTOPIA Forum ATM cell format,Supports Configurable data width Full IEEE-754 compliance, 4 pipelines, Single precision real format support Full IEEE-754 compliance, 15 pipelines, Single precision real format support 16/32-bit frame seq,16/32-bit frame 8/16-bit addr insert/delete, flag/zerop insert/detection Full IEEE-754 compliance, double word input, 2 pipelines, Single precision real output Full IEEE-754 compliance, pipelines, 7 32x32 mult, Single precision real format support Protocol conversion from Pb (RACE BLNT) to UTOPIA L2, BLNT) to UTOPIA Protocol conversion from Pb (RACE 8/16 bit operation ATM Supports ATM Forum UTOPIA Level-3. UTOPIA Forum ATM cell format, Configurable Supports data width, FIFO size configurable Cell handshake in SPHY mode,Cell handshake 8/16 bit operation, internal FIFO, detects runt cells in SPHY mode,Cell handshake 8/16 bit operation, internal FIFO, detects runt cells 64-bit input data width, constant, inputs, or variable reloadable implementation parallel/sequential Radix-2/radix4 architectures,Radix-2/radix4 BER, depuncturing. Code rate, length parameterizable contraint Supports ATM Forum UTOPIA Level-3. UTOPIA Forum ATM cell format, Configurable Supports data width, FIFO size configurable Device Features Key Application Examples XC2V500 16 bit complex data, 2's comp, and inverse transform forward XC2V500XC2V500 16 bit complex data, 2's comp, and inverse transform forward XC2V500 16 bit complex data, 2's comp, and inverse transform forward 16 bit complex data, 2's comp, and inverse transform forward XC2V1500-5 100, 7.7us 100, 1.9us 80, 2.5Gbps 130, 123ns 100, 41us Occupancy MHz endor NameType IP Virtex-II Virtex Spartan-II Spartan Function V Communication & Networking (continued) Reed-Solomon DecoderReed-Solomon EncoderSDLC ControllerSingle-Channel XF-HDLC ControllerSPEEDROUTER Network ProcessorT1 DeframerT1/E1 Framer Decoder - 3GPPTurbo EncoderTurbo DecoderTurbo TURBO_DEC Level-2 PHY Side RX InterfaceUTOPIA TX Interface Level-2 PHY Side UTOPIA MemecCore ReceiverATM Level-3 UTOPIA AllianceCORE TILAB TransmitterUTOPIA Level-3 ATM Xilinx Level-3 PHY ReceiverUTOPIA IPTransmitter Level-3 PHY UTOPIA AllianceCORE Master (CC140f)UTOPIA V-II V Slave (CC141) LogiCOREUTOPIA AllianceCORE CAST Slave (CC143S)UTOPIA TILAB V V-II V-II DecoderViterbi S-II TILAB SysOnChip AllianceCORE DecoderViterbi V TILAB AllianceCORE V Decoder,Viterbi AllianceCORE IEEE 802-compatible V-II Xilinx AllianceCORE XilinxDigital Signal Processing inSilicon V-II inSilicon AllianceCORE V Complex FFT IFFT S-II1024-Point TILABVirtex-II Complex FFT IFFT for 1024-Point 95% V-II V LogiCORE AllianceCORE inSilicon inSilicon AllianceCORE V Complex FFT / IFFT16-Point LogiCORE SVirtex-II Complex FFT IFFT for V16-Point AllianceCORE V 77 AllianceCORE AllianceCORE 56% Complex FFT / IFFT256-Point S-II V-II 42% PaxonetVirtex-II Complex FFT IFFT for 256-Point S-II 64% V V Complex FFT/IFFT32 Point 61 V V S Paxonet Xilinx 180 V Complex FFT IFFT AllianceCORE64-Point XC2S15-5 Paxonet S V S-IIVirtex-II V Complex FFT IFFT for 64-Point S-II 38% Xilinx S-II S-II AllianceCORE 8%Bit Correlator S-II XC2V1000-5 AllianceCORE 88% LogiCORE 10% Comb (CIC)Cascaded Integrator S-II S-II S 158 S XC2V40 XilinxComb Filter Xilinx 99% TILAB V LogiCORE 53 V-II 65Direct Digital Synthesizer 61 Xilinx S S Xilinx 5%Arithmetic FIR Filter 6%Distributed V-II Xilinx 15% 48% S-II V 65 XC2V100-5 V AllianceCOREDual-Channel Numerically Controlled Oscillator LogiCORE LogiCORE 7% 21% 22%Accelerator Xilinx DSP Hardware GVA-200A 164 XC2V2000-5 150 LogiCORE XCV50-6 120 LogiCORE S-II 54 S-IIAccelerator S DSP Hardware GVA-220 Xilinx XCV50-6 V-II Like LogiCOREAccelerator DSP Hardware 104 XC2V2000-5Virtex 72 100GVA-250 V-II parameterizable, available RTL V-II XilinxAccelerator DSP Hardware Virtex-E LogiCOREGVA-270 V S V-II XCV100E-8 XCV100E-8 * XilinxAccelerator DSP Hardware Virtex-E V GVA-290 S LogiCORE XC2V80-5 V Xilinx XC2S150 Accelerator DSP Hardware Virtex-II V-IIGVA-300 Xilinx XCV100E-8 V S-II XCV100E-8 26% XC2S150 70% LogiCORELFSR, V-II Shift Register Linear Feedback S-II 3GPP/UMTS compliant, V LogiCORE * 2Mbps data rate Buffer *Time-Skew Nonsymmetric 16-Deep LogiCORE S V-II Buffer 79Time-Skew 147Nonsymmetric 32-Deep LogiCORE 3GPP/UMTS compliant, >2Mbps data rate Xilinx GV 62% Numerically Controlled Oscillator GV Xilinx GV V 65%Arithmetic FIR Filter Xilinx Distributed Parallel * 3GPP/UMTS compliant, V-II GV upto 4 interleaver laws GVArithmetic FIR FilterSerial Distributed 80% LogiCORE GV AllianceCORE XC2V250 37% V XCV50-4 S-II Buffer VTime-Skew Symmetric 16 Deep AllianceCORE * 56 AllianceCORE V LogiCORE XilinxMath Functions LogiCORE AllianceCORE 54% AllianceCORE V-II 1001s and 2s Complement S-II Xilinx AllianceCORE V-II S-II Error correction, V-IIAccumulator wireless, Xilinx Xilinx DSL V * LogiCORE V-IIAdder Subtracter XCV50-6 SPHY, V V 38% V VConstant Coefficient Multiplier S LogiCORE XC2V250 S-II V XilinxConstant Coefficient Multiplier - Pipelined LogiCORE LogiCORE Error correction, length(k)=7, Constraint wireless S-II G0=171, G1=133 Xilinx to Integer ConverterDFP2INT Floating Point S-II Error correction, Xilinx wireless Adder Floating Point DFPADD V-II Xilinx Error correction, wireless LogiCORE ComparatorDFPCOMP Floating Point S Divider VDFPDIV Floating Point LogiCORE LogiCORE MultiplierDFPMUL Floating Point S LogiCORE Square Root Floating Point DFPSQRT S-II Puncturing, architecture, serial & parallel NA NA ConverterDINT2FP Integer to Floating Point Xilinx NA Digital NADynamic Constant Coefficient Multiplier NA S NA V XilinxIntegrator NA NA AllianceCORE Xilinx NAAccumulator (MAC)Multiply LogiCORE S NA NA V-IIMultiply Generator S-II NA S DigitalArea Optimized Multipliers LogiCOREParallel LogiCORE Digital V XilinxPipelined Divider Xilinx Digital S AllianceCORE S Registered Adder * * Digital Digital Digital *AdderRegistered Loadable S-II AllianceCORE V-II S * AllianceCORE Xilinx * LogiCORE * LogiCORE S V-II AllianceCORE V AllianceCORE V-II AllianceCORE V-II V-II V-II V V-II 32 bits data width, V-II change from 8 to 16384 rate LogiCORE V S-II V 39% V V V V S-II 8-65K samples, 32-bits output precision, phase dithering/offset S-II S Xilinx Xilinx S-II S-II S-II S-II 66 S-II S Virtex-E, 2 Spartan-II FPGAs, 1 CPLD,Virtex-II, 2 support, Virtex-E Matlab I/F 4096 taps, Spartan-II FPGAs, 2 FPGAs, input, S serial/parallel 1 CPLD, V ZBT SRAMs Matlab I/F 4096 bits width 16% LogiCORE LogiCORE Xilinx 39% XC2V250-5 37% Xilinx 2 FPGAs, 2 SRAMs V-II 91 Ext SRAM I/F, 2 FPGA's Ext SRAM I/F Xilinx 39% 44% 99% 66 Xilinx V LogiCORE 168 input width

96 Xcell Journal Spring 2002 Reference IP/Cores s face ions ations, modems nce, industrial control nce, industrial control applications, modems ctions, State mach, Coprocessor 32 bit processing, DSP Processor, I/O interface Processor, I/O interface Embedded systems, telecom Embedded systems, telecom Serial data applications, modems Serial data applications, modems video, embedded computing , networking Embedded systems, telecom, video Simple microcontroller applications Event counterr, generator baud rate Real-time interrupt based uP designs Real-time interrupt based uP designs Telecom, industrial, high speed control DSP,Telecom, industrial, high speed control Internet appliance, industrial control, multimedia, HAVi set top boxes data bus Processor I/O interface tandard 8051 Embedded systems, telecom, video C dev. tools ter than standard 8051 Embedded systems, telecom, video set, 35 instructions Embedded systems, telecom, audio and video et, 33 instructionset, 33 instructions Embedded systems, telecom, audio and video Embedded systems, telecom, audio and video rface, dual data pointer Low cost embedded systems, telecom d data interrupts. 16X clock Serial data applications, modems 1-256 bits, 2-13K words 1-256 bits, 2-128K words Input width up to 256 bits hree 8-bit peripheral ports,hree 8-bit peripheral I/O lines, 24 programmable 8-bit bidi data bus Processor I/O inter hree 8-bit parallel ports,hree 8-bit parallel IO lines, 24 programmable 8-bit bidi data bus ports,hree 8-bit parallel IO lines, 24 programmable 8-bit bidi data bus 1-256 bits, 15-65535 words, DRAM or BRAM, independent I/O clock domains 1-1024 bit, 16-65536 word, RAM/ROM/SRL16, opt output regs and pipelining Status feedback, counter latch, mode, square wave binary/BCD count, LSB/MSB R/W bit I/O, 3 counters, timer, 27-bit watchdog 3-priority interrupt controller, SFR interface vectored priority interrupts, e.g., all 8259/A modes programmable- mask, special buffer Prog. Data width, parity, stop bits. 16X internal clock, FIFO mode, false start bit detection Avg 12X faster and code compatible v. legacy 8051, verification bus monitor, SFR interface DDR SDRAM burst length support for 2,4, 8 per access, supports data 16, 32, 64, 72 Digital Avg 8X faster & code compatible v. legacy 8051, verification bus monitor, SFR IF,DSP focused 8 vectored priority interrupts, – e.g., all 8259/A modes programmable special mask, buffer 80C31 instruction set,ALU, 8 bit 8 bit control, 32 bit I/O ports, two 16 bit timer/counters, SFR I/F 4 stage pipeline, 16 single cycle instructions10, 3 interrupt exception levels, 24 bit stack pointer Prog. Data width, parity, stop bits. 16X internal clock, FIFO mode, start bit detection false 80C31 instruction set, high speed multiplier, RISC architecture 6.7X faster than standard 8051 Device Features Key Application Examples Implementation Example Occupancy MHz endor NameType IP Virtex-II Virtex Spartan-II Spartan Function V Math Functions (continued) Registered Loadable SubtracterAdderRegistered Scaled AdderRegistered Serial Registered SubtracterScaled-by-One-Half AccumulatorTableSine Cosine Look Up Square Root ComplementerTwos Asynchronous FIFO XilinxAddressable Memory (CAM)Content Distributed Memory Block MemoryDual-Port LogiCORE XilinxPipelined Delay Element Xilinx XilinxRegistered ROM RAMRegistered Single Port Xilinx LogiCORE Xilinx Block MemorySingle-Port LogiCORE LogiCORESynchronous FIFOSynchronous FIFO LogiCORE Xilinx LogiCOREMicroprocessors, & Peripherals Controllers Xilinx10/100 Ethernet MAC V-IITable Registered Look Up 16-Word-Deep Xilinx LogiCORE200 MHz SDRAM Controller Core V LogiCORE RISC ProcessorARC 32-bit Configurable Xilinx S V-IIAX1610 16-bit RISC Processor LogiCORE Xilinx V-II S-II XilinxC16450 UART V Xilinx with FIFOsC16550 UART LogiCORE Xilinx S VC165X MicroController S S LogiCORE S-II S C2901 Microprocessor Slice LogiCORE Xilinx V-II Xilinx LogiCORE S-II ControllerC2910a Microprogram Xilinx S V-II LogiCOREC68000 Microprocessor V-II V ARCC8051 MicroController LogiCORE LogiCORE V Xilinx Rapid VC8250 UART LogiCORE S-II XilinxTimer/Counter Interval C8254 Programmable V-II Xilinx AllianceCORE S-II InterfaceC8255A Peripheral S-II AllianceCORE Loarant LogiCORE V Interrupt ControllerC8259A Programmable S LogiCORECompact UART LogiCORE AllianceCORE of D80530 MicrocontrollerVersion Compact S-II V-II V V-II MicroEngine CardsCPU + FPGA (Virtex/Spartan-II) CAST V-II V CAST MicroEngine CardsCPU + FPGA (Virtex-II) CAST V CAST S V CAST S-IICZ80CPU Microprocessor V S S-II CAST AllianceCORED80530 8-bit Microcontroller AllianceCORE CAST AllianceCORE S-II S-IIDDR SDRAM Controller Core AllianceCORE S-II S AllianceCORE NMI CAST RISC MicroControllerDFPIC125X Fast S AllianceCORE CAST V-II RISC MicroControllerDFPIC1655X Fast CAST AllianceCORE RISC MicroController VDFPIC165X Fast 89% AllianceCORE AllianceCORE CAST V S V AllianceCORE VDI2CM I2C Bus Controller Master NMI V AllianceCORE V-II 12%DI2CM I2C Bus Controller Slave S-II 37 V S-II AllianceCORE S-IIDI2CSB I2C Bus Controller Slave Base CAST S-II V V S-II AllianceCOREDR8051 RISC MicroController 3-10 bit in, 4-32 bit out, 91 distributed/block ROM V S-IIDR8051BASE RISC MicroController V V-II S AllianceCORE S-II V XC2S150-6 DR8052EX RISC MicroController Digital CAST S-II DigitalTimer/Counter Interval e8254 Programmable CAST V MemecCore CAST S-II 13% XC2V500-5 60% Interfacee8255 Peripheral S-II 38% Digital 19% AllianceCORE AllianceCORE AllianceCOREEP520 SDRAM Controller AllianceCORE S-II AllianceCORE 29% AllianceCORE 1-512 bits, 63 V 2-10K words, V-IIFlip805x-PR Core SRL16 V-II 134 Digital 66 V-II AllianceCORE 28% 36Flip805x-PS Microprocessor 51 V-II Digital Virtex-II 90% V V V-IIIIC NA Digital 60 S-II 88% V einfochips AllianceCORE VIntelliCore Prototyping System 52% 47 V AllianceCORE XC2V80-5 XCV50-6 V V Processor Core Java Configurable LavaCORE S-II 32 Digital S-II XCV100E-8 V-II AllianceCORE 10% AllianceCORE NA S-II Digital XC2S50-6 51 44 opcode, XC2S50-6 Processor Core V-II Java Configurable 64-K word data,LavaCORE S-II program, arch. Harvard S-II 68 V-II V-II XC2S50-6 Digital NA Processor CoreLightfoot 32-bit Java S-II V AllianceCORE 227 V XC2S50-6TransmitterAsynchronous Receiver M16450 Universal AllianceCORE V XC2V500-5 V V-II S with FIFOsM16550A UART AllianceCORE S-II XC2S150-6 V-II NATimer S-II XCV200E-8 M8254 Programmable 49%ALU, einfochips Eight function 4 status flags- Carry, 7% NA Overflow, 8 Zero and Negative Derivation 79% V-II V S-II S-II Independently controlled transmit, Interface Peripheral M8255 Programmable receive and data interrupts. XCV50E-8 Virtual 16X clock 55% 7% V Derivation S AllianceCORE Interrupt Controller 98 Interfaces through OPB to MicroBlaze 1-256 bits,M8259 Programmable Eureka 49% 16-256 words, 126 distributed/block RAM AllianceCORE S V 133 140 S-IIMicroBlaze Soft RISC Processor 32 bit I/O, 81% 3 counters, Dolphin Control fun S controller, interrupt V-II AllianceCORE inte SFR AllianceCORE S-II 72 VAutomation 142 V-IIArbiter 58%OPB 126 AllianceCORE NA 15% S-II V-II ports, 8-bit peripheral Three AllianceCORE IO lines, 24 programmable OPB GPIO 8-bit bidi V AllianceCORE Dolphin 66 28% V Digital XCV50E-8 XC2V80-5 XC2V1000-4 Microchip 16C5X PIC like 1%OPB Interrupt Controller 143 XC2V80-5 Serial data V V-IIAMD 2910a Based on 187OPB Memory Interface (Flash, XC2V500-5 SRAM) S-II XCV50-6 AllianceCORE 157 Virtual XC2V80-5 46% AllianceCORE 175 68% V V Virtual XCV200E-8 generator, & Baud rate UART 16X clock generator, V-II loopback & echo modes 80–90 XC2V50-5 99% AllianceCORE MC68000 Compatible Virtual XC2V50-5 PIC 12c4x like, S/W compatible with PIC16C55X, 2X faster, 12-bit wide instruction s 14-bit instruction Networking, S-II S-II 73 communications, Virtual AllianceCORE processor apps XC2V50-5 V 32 XC2V1000-5 V 71 Xilinx PIC 12c4x li Variable Parallel Virtex MultiplierVirtex Parallel Variable Elements Memories & Storage Xilinx LogiCORE V S-II

Spring 2002 Xcell Journal 97 Reference Support

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