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A História Da Família Powerpc

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A História Da Família Powerpc A História da família PowerPC ∗ Flavio Augusto Wada de Oliveira Preto Instituto de Computação Unicamp fl[email protected] ABSTRACT principal atingir a marca de uma instru¸c~ao por ciclo e 300 Este artigo oferece um passeio hist´orico pela arquitetura liga¸c~oes por minuto. POWER, desde sua origem at´eos dias de hoje. Atrav´es deste passeio podemos analisar como as tecnologias que fo- O IBM 801 foi contra a tend^encia do mercado ao reduzir ram surgindo atrav´esdas quatro d´ecadas de exist^encia da dr´asticamente o n´umero de instru¸c~oes em busca de um con- arquitetura foram incorporadas. E desta forma ´eposs´ıvel junto pequeno e simples, chamado de RISC (reduced ins- verificar at´eos dias de hoje como as tend^encias foram segui- truction set computer). Este conjunto de instru¸c~oes elimi- das e usadas. Al´emde poder analisar como as tendencias nava instru¸c~oes redundantes que podiam ser executadas com futuras na ´area de arquitetura de computadores seguir´a. uma combina¸c~ao de outras intru¸c~oes. Com este novo con- junto reduzido, o IBM 801 possuia metade dos circuitos de Neste artigo tamb´emser´aapresentado sistemas computacio- seus contempor^aneos. nais que empregam comercialmente processadores POWER, em especial os videogames, dado que atualmente os tr^es vi- Apesar do IBM 801 nunca ter se tornado um chaveador te- deogames mais vendidos no mundo fazem uso de um chip lef^onico, ele foi o marco de toda uma linha de processadores POWER, que apesar da arquitetura comum possuem gran- RISC que podemos encontrar at´ehoje: a linha POWER. des diferen¸cas de design. Descendente direto do 801, a arquitetura POWER (Perfor- Diferen¸cas de design que n~ao implicam na n~ao conformidade mance Optimization With Enhanced RISC) surgiu em 1990, com a PowerPC ISA, que ´eo conjunto de instru¸c~oes da arqui- dando origem a uma s´eries de processadores que equipariam tetura PowerPC. Este conjunto que ´eaberto e mantido por desde workstations at´egrandes servidores. O seu objetivo uma institui¸c~ao ao inv´esde uma ´unica empresa. Permitindo era fornecer complementos ao 801 que era bastante simples assim que qualquer empresa fabrique chips compat´ıveis com e faltava unidades aritm´eticas de ponto flutuante e proces- a arquitetura POWER. samento paralelo. E desta forma o artigo permite que o leitor conhe¸ca os deta- Baseado na arquitetura POWER e fruto da alian¸ca Apple- lhes de arquitetura, pol´ıtico e historicos da fam´ılia POWER. IBM-Motorola (AIM), surgiu a linha de processadores PowerPC (POWER Performance Computing). Projetado para ser em- 1. INTRODUÇÃO pregado desde de dispositivos embarcados at´egrandes ser- Na d´ecada de 70 um dos maiores problemas computacio- vidores e mainframes teve sua primeira apari¸c~ao comercial nais era o chaveamento de liga¸c~oes telef^onicas. Entretando no Power Macintosh 6100. nesta ´epoca a grande maioria dos computadores eram CISC (complex instruction set computer) e possuiam um conjunto Desde 1993, quando o PowerPC foi criado, o ecossistema de instru¸c~oes extenso, complexo e muitas vezes redundante. que o abriga evoluiu continuamente, dando origem a pro- Essa tend^encia de computadores CISCs decorria do fato do dutos mais modernos, ao mesmo tempo que as empresas do surgimento do transistor e do circuito integrado. Para re- ecossistema se alteravam. A Apple atualmente n~ao est´amais solver o problema de chaveamento telef^onico a IBM iniciou envolvida no projeto e hoje em dia emprega processadores o desenvolvimento do IBM 801, que tinha como objetivo X86 em sua linha de produtos. J´aa Motorola separou sua divis~ao de semicondutores numa nova empresa: a Freescale ∗RA032883 Semiconductors. Entretanto, uma grande vantagem que mantem vivo o ecos- sistema da arquitetura PowerPC ´eo fato dela ser aberta. Ou seja o ISA (Instruction Set Architecture) ´edefinido por um cons´orcio e disponibilizada para que qualquer um possa pro- jetar e fabricar um processador compat´ıvel com o PowerPC. Outra grande vantagem competitiva da arquitetura PowerPC ´eque sua simplicidade herdada do 801 permite que o core do CPU seja extremamente pequeno, liberando espa¸co no mais elevados devido a evolu¸c~ao nos processos de fabrica¸c~ao circuito para que seja adicionado outros componentes que o de semicondutores, chegando at´e62.5 Mhz. desenvolvedor desejar, como por exemplo coprocessadores, cache e controladores de mem´oria. A arquitetura do POWER1 ´ebaseada em um CPU de 32- bits superscalar de duas vias. Cont´emtr^esunidades de exe- Isso tudo resultou numa das mais bem sucedidas linhas de cu¸c~ao, uma de aritm´etica de ponto-fixo (FXU), uma de arit- processadores que nos dias de hoje pode ser encontrado m´etica deponto flutuante (FPU) e uma de branch (BU). O desde os videogames mais vendidos at´eos mais potentes su- espa¸co de endera¸camento f´ısico era de 32-bits, entretanto o per computadores existente. endere¸camento virtual era de 52 bits para beneficiar o de- sempenho das aplica¸c~oes. O cache contava com 8 KB e um 2. A HISTÓRIA DO POWERPC 2-way set associative para instru¸c~oes e 32 ou 64 KB em 4- way set associative com 128 bytes por linha para dados. 2.1 O projeto 801 Em 1974 a IBM inicou um projeto para um processador ca- paz de lidar com o roteamento de at´e300 liga¸c~oes telef^onicas 2.2.2 POWER2 por minuto. Para este n´umero era estimado que fosse neces- O processador POWER2 foi lan¸cado em 1993 com um pro- s´ario cerca de 20000 instru¸c~oes por liga¸c~ao, e por consequ^en- jeto aprimorado do POWER1. Com clocks que variavam cia para 300 liga¸c~oes seria necess´ario um processador de 12 de 55 at´e71.5 Mhz e uma unidade aritm´etica de ponto fixo MIPS. Este valor era extremamente alto para a ´epoca, en- adicional e uma unidade de ponto flutuante adicional. Um tretanto foi notado que os processadores existentes possuiam cache maior e algumas instru¸c~oes novas. A implementa¸c~ao diversas instru¸c~oes que nunca eram usadas ou eram usadas usada para o POWER2 era de multi-chip, sendo composto muito raramente. de 8 chips. Apesar de 1975 o projeto de telefonia ter sido cancelado Em 1996 foi lan¸cado o POWER2 Super Chip, ou simples- sem sequer ter produzido um prot´otipo, A id´eia de um pro- mente P2SC, como uma implementa¸c~ao em apenas um chip cessador com um conjunto de instru¸c~oes bastante reduzido do POWER2. Al´em detsa altera¸c~ao, tambem foram melho- mostrou-se bastante promissora. De modo que os traba- rados os caches e o clock chegou a 135 MHz. Essa vers~ao lhos de pesquisa continuaram sobre o codinome \Cheetah" foi empregada para constru¸c~ao do super-computador de 30 no pr´edio n´umero 801 do Thomas J. Watson Research Cen- cores, Deep Blue da IBM, que derrotou o campe~ao mundial ter. de xadrex, Garry Kasparov, em 1997. Os pesquisadores estavam tentando determinar se era vi´avel 2.2.3 POWER3 uma m´aquina RISC manter m´ultiplas instru¸c~oes por ciclo Foi o primeiro multiprocessador sim´etrico (SMP) 64-bits e e quais altera¸c~oes deveriam ser feitas sobre o projeto 801 mesmo assim totalmente compat´ıvel com o conjunto de ins- original. Para isso, foi imaginado unidades separadas para tru¸c~oes POWER. O POWER3 foi lan¸cado em 1998 depois branch, artim´etica de ponto fixo e aritim´etica de ponto flu- de um longo atraso de quase 3 anos. tuante. Dispon´ıvel inicialmente com o clock de 200 MHz, possuia Em 1985 iniciou o projeto de uma segunda arquitetura RISC tr^esunidades de ponto-fixo e duas e unidades de ponto- no Thomas J. Watson Research Center de codinome\AMERIC" flutuantes capazes de realizar opera¸c~oes de multiplica¸c~ao e para ser usada nas series RS/6000. Este projeto resultou na adi¸c~ao em apenas um ciclo para uma dada precis~ao. Com arquitetura POWER[2]. um design super-escalar capaz de executar instru¸c~oes fora de ordem em seu pipeline 7 est´agios para inteiros e 8 est´agios 2.2 POWER para load/store. Apresentado como o processador RISC da s´erie RS/6000[1] em fevereiro de 1990. Iniciava-se a´ıuma longa saga de pro- Para otimizar possuia registradores ocultos para efetuar re- cessadores POWER at´eos dias de hoje. gister renaming tanto para opera¸c~oes de prop´osito geral como opera¸c~oes em ponto flutuante. Al´emde um cache otimizado A arquitetura fortemente baseada na 801, com um design para aplica¸c~oes cient´ıficas e t´ecnicas. Com uma capacidade RISC, buscava superar as limita¸c~oes de seu predecessor. dobrada que agora atingia 64Kb com linhas de 128-bytes. Para isso deveria incluir uma unidade de ponto flutuante, um sistema de pipeline para execu¸c~ao de mais de uma ins- 2.2.4 POWER4 tru¸c~ao ao mesmo tempo. Com um clock que rompeu a barreira de 1Ghz, em seu lan- ¸camento em 2001 era considerado o chip mais poderoso do Inicialmente com 32 registradores de 32 bits, e posterior- mercado. Com uma arquitetura que herdava todas as ca- mente os modelos 64 bits incluiam mais 32 registradores de racter´ısticas do POWER3, incluindo a compatibilidade com 64 bits e armazenamento de dados no formato big-endian. o conjunto de instru¸c~oes PowerPC, por´emem um design totalmente diferente.
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