DOCSLIB.ORG

Dell EMC Openmanage SNMP Reference Guide Version 9.0.1 Notes, Cautions, and Warnings

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Dell EMC Openmanage SNMP Reference Guide Version 9.0.1 Notes, Cautions, and Warnings Dell EMC OpenManage SNMP Reference Guide Version 9.0.1 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. Copyright © 2017 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 2017 - 06 Rev. A00 Contents 1 Introduction..................................................................................................................... 7 Supported SNMP Versions................................................................................................................................................. 7 Managed Object Used in This Document............................................................................................................................7 Server Administrator Instrumentation MIB..........................................................................................................................8 Server Administrator Baseboard Management Controller, ASF MIB....................................................................................9 Server Administrator Storage Management MIB................................................................................................................ 9 Server Administrator Field Replaceable Unit MIB.............................................................................................................. 10 Server Administrator Change Management MIB...............................................................................................................10 Basic Terminology.............................................................................................................................................................. 11 Frequently Used Terms in Variable Names......................................................................................................................... 11 Tables.................................................................................................................................................................................11 SNMP Tables............................................................................................................................................................... 11 Section Organization.........................................................................................................................................................13 Other Documents You May Need......................................................................................................................................13 Introduction to the Server Administrator SNMP Subagent................................................................................................13 Management Information Base Object Identifiers........................................................................................................14 SNMP Security...........................................................................................................................................................15 SNMP Traps................................................................................................................................................................15 2 Server Administrator Group........................................................................................... 16 Instrumentation MIB Version Group.................................................................................................................................. 16 Management Information Base Major Version Number............................................................................................... 16 Management Information Base Minor Version Number............................................................................................... 17 Management Information Base Maintenance Version Number.................................................................................... 17 Systems Management Software Group.............................................................................................................................17 Systems Management Software................................................................................................................................. 17 Systems Management Software Variable Values........................................................................................................20 System State Group..........................................................................................................................................................21 System State Group Table...........................................................................................................................................21 Chassis Information Group............................................................................................................................................... 35 Chassis Information Group Tables...............................................................................................................................35 Chassis Information Group Variable Values.................................................................................................................60 Operating System Group..................................................................................................................................................69 Operating System Memory Table............................................................................................................................... 69 System Resource Group....................................................................................................................................................71 System Resource Group Tables.................................................................................................................................. 72 System Resource Group Variable Values.................................................................................................................... 84 Power Group....................................................................................................................................................................86 Power Group Tables................................................................................................................................................... 86 Power Group Variable Values.................................................................................................................................... 109 Thermal Group.................................................................................................................................................................116 3 Thermal Group Tables................................................................................................................................................116 Thermal Group Variable Values..................................................................................................................................125 Remote Flash BIOS Group.............................................................................................................................................. 126 Remote Flash BIOS Group Table............................................................................................................................... 126 Remote Flash BIOS Variable Values...........................................................................................................................128 Port Group......................................................................................................................................................................130 Port Group Tables..................................................................................................................................................... 130 Port Group Variable Values....................................................................................................................................... 150 Device Group..................................................................................................................................................................153 Device Tables............................................................................................................................................................153 Device Group Variable Values....................................................................................................................................195 Slot Group...................................................................................................................................................................... 216 System Slot Group Table...........................................................................................................................................216 System Slot Variable Values...................................................................................................................................... 219 Memory Group...............................................................................................................................................................224
Load more

Recommended publications
  • United States Patent (10) Patent N0.: US 7,290,102 B2 Lubbers Et A]
    US007290102B2 (12) United States Patent (10) Patent N0.: US 7,290,102 B2 Lubbers et a]. (45) Date of Patent: Oct. 30, 2007 (54) POINT IN TIME STORAGE COPY 5,184,281 A 2/1993 Samarov et al. 5,513,314 A 4/1996 Kandasamy et al. (75) Inventors: Clark E. Lubbers, Colorado Springs, 5,815,371 A 9/ 1998 Jeiffies et a1~ CO (US); James M. Reiser, Colorado 5,815,649 A 9/1998 Utter et al' Springs’ CO (Us); Anuja Korgaonkars 5,822,777 A 10/1998 Les-hem et al. Colorado Springs CO Randy L 5,832,222 A 11/1998 DZladosZ et al. Roberson New £30m Richeg/ FL (US)_' 5,835,700 A 11/1998 Carbonneau et al. ’ ’ ’ 5,923,876 A 7/1999 Teague Robert G- Bean, Monument, CO (Us) 5,987,622 A 11/1999 L0 Verso et al. 5,996,089 A 11/1999 Mann et a1. (73) Assignee: Hewlett-Packard Development 6,033,639 A 3/2000 Schmidt et a1, Company, LP, Houston, TX (US) (Continued) ( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 OTHER PUBLICATIONS U-S-C- 154(1)) by 360 days- Smart Storage Inc., “SmartStor In?NetTM; Virtual Storage for Today’s E-economy,” Sep. 2000. (21) Appl. N0.: 11/081,061 _ (Contlnued) (22) Filed: Mar‘ 15’ 2005 Primary ExaminerAiary Portka (65) Prior Publication Data (57) ABSTRACT US 2005/0160243 A1 Jul. 21, 2005 A storage system permits Virtual storage of user data by Related US. Application Data implementing a logical disk mapping structure that provides (63) Continuation of application NO‘ 10/080 961 ?led on access to user data stored on physical storage media and Oct 22 2001 HOW Pat NO 6 915 392 Winch is a methods for generating point-in-time copies, or snapshots, con?nue’ltion_il’l_ an of 2'‘ li'cat’ion ’NO ’09/872 597 of logical disks.
    [Show full text]
  • Nubus Physical Designs
    Macintosh Technical Notes ® Developer Technical Support #234: NuBus Physical Designs—Beware Revised by: Rich Collyer December 1989 Written by: Rich Collyer June 1989 This Technical Note discusses the possible problems you might run into while designing a NuBus™ card. It covers some of the specifications which, if not followed, will have problems with current Macintosh machines, and possibly future machines. Changes since June 1989: Added warnings about the no component area and full-size NuBus cards. If you are making a NuBus card for the Macintosh II family of computers, then you have to be very careful to follow the physical specifications which are listed in the NuBus specifications (IEEE P1196). There are two areas where some developers have run into problems. The first problem has to do with not positioning the external connector properly. The result is that some products have problems with the external hole on the back of the Macintosh IIcx. The second problem has to do with developers who run ribbon cables over the top of their boards to connect two boards. If a slot is not cut into the top of the board to allow the ribbon cable to sit below the top of the card, then the boards will have problems in our machines. External Connector The NuBus specification allows for an external connector plastics opening of only 74.55 mm x 11.90 mm. The Macintosh II and IIx allowed a significantly larger hole than the specification (80.00 mm x 17.00 mm) and some developers incorrectly assumed that Apple would continue to allow for this larger size.
    [Show full text]
  • Dell EMC Openmanage CIM Reference Guide Version 9.1 Notes, Cautions, and Warnings
    Dell EMC OpenManage CIM Reference Guide Version 9.1 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. Copyright © 2017 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 2017 - 12 Rev. A00 Contents 1 Introduction....................................................................................................................................................6 Server Administrator..........................................................................................................................................................6 Documenting CIM Classes and Their Properties........................................................................................................... 6 Base Classes................................................................................................................................................................. 7 Parent Classes.............................................................................................................................................................. 7 Classes That Describe Relationships........................................................................................................................
    [Show full text]
  • Local, Compressed
    General Processor Information Copyright 1994-2000 Tom Burd Last Modified: May 2, 2000 (DISCLAIMER: SPEC performance numbers are the highest rated for a given processor version. Actual performance depends on the computer configuration, and may be less, even significantly less than, the numbers given here. Also note that non-italicized numbers may be company esti- mates of perforamnce when actual numbers are not available) SPEC-92 Pipe Cache (i/d) Tec Power (W) Date Bits Clock Units / Vdd M Size Xsistor Processor Source Stages h e (ship) (i/d) (MHz) Issue (V) (mm2) (106) int fp int/ldst/fp kB Assoc (um) t peak typ 5 - - 8086 [vi] 78 v/16 8 - - 1/1 1/1/na - - 5.0 3.0 0.029 10 - - 5 - - 8088 [vi] 79 v/16 1/1 1/1/na - - 5.0 3.0 0.029 8 - - 80186 [vi] 82 v/16 - - 1/1 1/1/na - - 5.0 1.5 6 - - 80286 [vi] 82 v/16 10 - - 1/1 1/1/na - - 5.0 1.5 0.134 12 - - Intel 85 16 x86 1.5 87 20 i386DX [vi] v/32 1/1 - - 5.0 0.275 88 25 6.5 1.9 89 33 8.4 3.0 1.0 2 [vi,41] 88 16 2.4 0.9 1.5 89 20 3.5 1.3 2 i386SX v/32 1/1 4/na/na - - 5.0 0.275 [vi] 89 25 4.6 1.9 1.0 92 33 6.2 3.3 ~2 43 90 20 3.5 1.3 i386SL [vi] v/32 1/1 4/na/na - - 5.0 1.0 2 0.855 91 25 4.6 1.9 SPEC-92 Pipe Cache (i/d) Tec Power (W) Date Bits Clock Units / Vdd M Size Xsistor Processor Source Stages h e (ship) (i/d) (MHz) Issue (V) (mm2) (106) int fp int/ldst/fp kB Assoc (um) t peak typ [vi] 89 25 14.2 6.7 1.0 2 i486DX [vi,45] 90 v/32 33 18.6 8.5 2/1 5/na/5? 8 u.
    [Show full text]
  • Cortex-A9 Single Core Microarchitecture
    Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 18-600 Foundations of Computer Systems Lecture 10: “The Memory Hierarchy” John P. Shen & Gregory Kesden October 2, 2017 ➢ Required Reading Assignment: • Chapter 6 of CS:APP (3rd edition) by Randy Bryant & Dave O’Hallaron ➢ Recommended Reference: • Sec. 1 & Sec. 3: Bruce Jacob, “The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It,” Synthesis Lectures on Computer Architecture 2009. 10/02/2017 (© John Shen) 18-600 Lecture #10 1 18-600 Foundations of Computer Systems Lecture 10: “The Memory Hierarchy” A. Memory Technologies B. Main Memory Implementation a. DRAM Organization b. DRAM Operation c. Memory Controller C. Disk Storage Technologies 10/02/2017 (© John Shen) 18-600 Lecture #10 2 From Lec #9 … Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Three Flow Paths of Superscalar Processors ➢ Wide Instruction Fetching ➢ Dynamic Branch Prediction I-cache Branch Instruction FETCH Flow Predictor Instruction ➢ Register Renaming Buffer ➢ Dynamic Scheduling DECODE ➢ Load Bypassing & Forwarding ➢ Speculative Memory Disamb. DISPATCH Integer Floating-point Media Memory Reservation Stations Memory Data EXECUTE Flow Reorder Buffer Register (ROB) Data COMMIT Flow Store D-cache Queue 10/02/2017 (© John Shen) 18-600 Lecture #10 3 From Lec #9 … Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Integrating Map Table with the ARF 9/27/2017 (©J.P. Shen) 18-600 Lecture #9 4 From Lec #9 … Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Reservation Station Implementation + info for executing instruction (opcode, ROB entry, RRF entry…) • Reservation Stations: distributed vs.
    [Show full text]
  • Designing PCI Cards and Drivers for Power Macintosh Computers
    Designing PCI Cards and Drivers for Power Macintosh Computers Revised Edition Revised 3/26/99 Technical Publications © Apple Computer, Inc. 1999 Apple Computer, Inc. Adobe, Acrobat, and PostScript are Even though Apple has reviewed this © 1995, 1996 , 1999 Apple Computer, trademarks of Adobe Systems manual, APPLE MAKES NO Inc. All rights reserved. Incorporated or its subsidiaries and WARRANTY OR REPRESENTATION, EITHER EXPRESS OR IMPLIED, WITH No part of this publication may be may be registered in certain RESPECT TO THIS MANUAL, ITS reproduced, stored in a retrieval jurisdictions. QUALITY, ACCURACY, system, or transmitted, in any form America Online is a service mark of MERCHANTABILITY, OR FITNESS or by any means, mechanical, Quantum Computer Services, Inc. FOR A PARTICULAR PURPOSE. AS A electronic, photocopying, recording, Code Warrior is a trademark of RESULT, THIS MANUAL IS SOLD “AS or otherwise, without prior written Metrowerks. IS,” AND YOU, THE PURCHASER, ARE permission of Apple Computer, Inc., CompuServe is a registered ASSUMING THE ENTIRE RISK AS TO except to make a backup copy of any trademark of CompuServe, Inc. ITS QUALITY AND ACCURACY. documentation provided on Ethernet is a registered trademark of CD-ROM. IN NO EVENT WILL APPLE BE LIABLE Xerox Corporation. The Apple logo is a trademark of FOR DIRECT, INDIRECT, SPECIAL, FrameMaker is a registered Apple Computer, Inc. INCIDENTAL, OR CONSEQUENTIAL trademark of Frame Technology Use of the “keyboard” Apple logo DAMAGES RESULTING FROM ANY Corporation. (Option-Shift-K) for commercial DEFECT OR INACCURACY IN THIS purposes without the prior written Helvetica and Palatino are registered MANUAL, even if advised of the consent of Apple may constitute trademarks of Linotype-Hell AG possibility of such damages.
    [Show full text]
  • Power Macintosh 9500 Series
    K Service Source Power Macintosh 9500 Series Power Macintosh 9500/120, 9500/132, 9500/150, 9500/180MP, and 9500/200 K Service Source Basics Power Macintosh 9500 Series Basics Overview - 1 Overview The Power Macintosh 9500 Series computers are based on the PowerPC 604 microprocessor and support the industry-standard PCI (Peripheral Component Interconnect) bus specification. These computers are the most flexible, expandable, and highest-performance systems from Apple to date. The microprocessor for the Power Macintosh 9500 Series computers is on separate plug-in card, which allows for easy upgrades. The Power Macintosh 9500 family includes five versions: the 9500/120, the 9500/132, the 9500/150, the 9500/180MP (multi-processor), and the 9500/200. Basics Overview - 2 Features of the Power Macintosh 9500 Series include • 120, 132, 150, 180 (multi-processor) or 200 MHz PowerPC 604 microprocessor card with built-in FPU • Six PCI expansion slots • 10 MB per second internal SCSI channel, 5 MB per second external SCSI channel • 512K Level 2 cache • DRAM expansion up to 1536 MB using 168-pin, 70 ns, 64-bit DIMMs • A PCI Apple Accelerated Graphics card included with some configurations (the Power Macintosh 9500 Series does not include on-board video support) • Built-in AAUI and 10BASE-T Ethernet • AppleCD™ 600i 4x or1200i 8x CD-ROM drive • CD-quality stereo sound in/out • Mac™ OS system software 7.5.2, 7.5.3, or 7.5.3 Revision 2 Basics Configurations - 3 Configurations The Power Macintosh 9500/120 comes standard with • 120 MHz PowerPC 604 processor
    [Show full text]
  • Microprocessor Training
    Microprocessors and Microcontrollers © 1999 Altera Corporation 1 Altera Confidential Agenda New Products - MicroController products (1 hour) n Microprocessor Systems n The Embedded Microprocessor Market n Altera Solutions n System Design Considerations n Uncovering Sales Opportunities © 2000 Altera Corporation 2 Altera Confidential Embedding microprocessors inside programmable logic opens the door to a multi-billion dollar market. Altera has solutions for this market today. © 2000 Altera Corporation 3 Altera Confidential Microprocessor Systems © 1999 Altera Corporation 4 Altera Confidential Processor Terminology n Microprocessor: The implementation of a computer’s central processor unit functions on a single LSI device. n Microcontroller: A self-contained system with a microprocessor, memory and peripherals on a single chip. “Just add software.” © 2000 Altera Corporation 5 Altera Confidential Examples Microprocessor: Motorola PowerPC 600 Microcontroller: Motorola 68HC16 © 2000 Altera Corporation 6 Altera Confidential Two Types of Processors Computational Embedded n Programmable by the end-user to n Performs a fixed set of functions that accomplish a wide range of define the product. User may applications configure but not reprogram. n Runs an operating system n May or may not use an operating system n Program exists on mass storage n Program usually exists in ROM or or network Flash n Tend to be: n Tend to be: – Microprocessors – Microcontrollers – More expensive (ASP $193) – Less expensive (ASP $12) n Examples n Examples – Work Station
    [Show full text]
  • PCI Local Bus Specification Revision 3.0 June 2002Junedecember 5February 3, 20043 28, 2002
    PCI Local Bus Specification Revision 3.0 June 2002JuneDecember 5February 3, 20043 28, 2002 PCI LOCAL BUS SPECIFICATION, REV. 3.0 PCI SPECIFICATIONS REVISION REVISION HISTORY DATE 1.0 Original issue. 6/22/92 2.0 Incorporated connector and add-in card specification. 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter. 6/1/95 2.2 Incorporated ECNs and improved readability. 12/18/98 2.3 Incorporated ECNs, errata, and deleted 5 volt only keyed 3/29/02 add-in cards. 3.0 Incorporated ECNs, errata, and Rremoved support for the 212/305/ 5.0 volt keyed system board connector. Moved the 043 Expansion ROM description to the PCI Firmware Specification. The PCI Special Interest Group-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI-SIG Special Interest Group make a commitment to update the information contained herein. Contact the PCI-SIG Special Interest Group office to obtain the latest revision of the specification. Questions regarding the PCI specification or membership in the PCI-SIG Special Interest Grou may be forwarded to: PCI-SIG Special Interest Group 5440 SW Westgate Drive Suite 217 Portland, Oregon 97221 Phone: 800-433-5177 (Inside the U.S.) 503-291-2569 (Outside the U.S.) Fax: 503-297-1090 e-mail [email protected] http://www.pcisig.com DISCLAIMER This PCI Local Bus Specification is provided "“as is" ” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
    [Show full text]
  • LL5200 ISA to Vmebus LINK
    LL5200 ISA to VMEbus LINK FEATURES · High speed bus to bus link · Fiber Optic or Coax Cable · Up to 2Km system separation · Programmable address windows · Symmetrical Master/Slave operation · Both busses run independently · Remote Reset Function · 16/24/32 Bit VME, 24 Bit ISA addresses · Programmable byte swapping · VMEbus system controller functions SUMMARY APPLICATIONS LL5200 is an ISA to VMEbus link that allows the physical LL5200 and other Lextel Bus Links are being used to solve address space of an ISA bus based computer (PC/AT) to be these kinds of problems: mapped into that of the VMEbus, and vice-versa. Bus masters on either bus can have direct, random access to the other bus. BUS EXTENSION: When equipment needs to be Remote memory and IO devices appear to be within the local connected up to 2Km apart without machine, even though they may be physically located up to loss of throughput. 2Km away. BUS CONVERSION: When one bus architecture needs to Up to 4096 VMEbus address segments, or 'windows', can be be used with another. mapped into the ISA Bus address space. A single window of ISA address space can be mapped into the VMEbus. The size BUS EXPANSION: When more bus slots are needed and base address of the ISA window is programmable. In addition, the addresses can be translated as they pass across NOISE IMMUNITY: Fiber optics are immune to EMI, RFI the link. and crosstalk. Unlike a simple bus repeater, the LL5200 does not tie up both HIGH SPEED DATA: When a standard LAN isn't fast systems when one is in use.
    [Show full text]
  • Technical Report
    Technical Report Department of Computer Science University of Minnesota 4-192 EECS Building 200 Union Street SE Minneapolis, MN 55455-0159 USA TR 97-030 Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors by: Lynn Choi and Pen-Chung Yew Hardware and Compiler-Directed Cache Coherence 1n Large-Scale Multiprocessors: Design Considerations and Performance Study1 Lynn Choi Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 1308 West Main Street Urbana, IL 61801 Email: lchoi@csrd. uiuc. edu Pen-Chung Yew 4-192 EE/CS Building Department of Computer Science University of Minnesota 200 Union Street, SE Minneapolis, MN 55455-0159 Email: [email protected] Abstract In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf micro­ processors, such as the Cray T3D. The scheme can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is minimal and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data flow analysis, have been implemented on the Polaris parallelizing compiler [33]. From our simulation study using the Perfect Club benchmarks [5], we found that in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. Given its compa­ rable performance and reduced hardware cost, the proposed scheme can be a viable alternative for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data coherence.
    [Show full text]
  • Powerpc and Power Macintosh L Technical Information
    L Technical PowerPC and Information Power Macintosh Recently, both Apple Computer and IBM have introduced products based on the PowerPC™ microprocessor. The PowerPC microprocessor is a result of collaboration between three industry leaders: Apple, IBM, and Motorola. This cooperative project was announced in 1991. The project’s goal was to advance the evolution of the personal computer in five major areas: • PowerPC – Apple, IBM, and Motorola agreed to develop a family of RISC microprocessors. • Interoperability – IBM and Apple agreed to work together to ensure that Macintosh® computers work smoothly with large, networked IBM enterprise systems. This involves products in networking and communication. • PowerOpen® – IBM and Apple agreed to co-develop a new version of the UNIX® operating system that takes advantage of the strengths of the PowerPC microprocessor. • Kaleida – A new company called Kaleida was created to work on new standards for multimedia products. • Taligent – A new company called Taligent was created to develop an object-oriented operating system. While there have been advances in all of these areas, the announcement of the Power Macintosh has focused industry attention on the PowerPC chip. (Note: Microprocessors are often referred to as ‘chips’ or ‘computer chips’.) The PowerPC microprocessor The term PowerPC describes a family of microprocessors that may be used in a variety of computers. Apple Computer has introduced a series of computers based on this microprocessor which they will call Power Macintoshes™. IBM computers that contain the PowerPC microprocessor will be part of the RS6000 series. The RS6000 series is a high-end UNIX product. The Power Macintosh, on the other hand, is intended as a broad- based consumer product.
    [Show full text]