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 DRAM as building for main memory The  Caching in the memory hierarchy  Storage technologies and trends 15‐213 / 18‐213: Introduction to Computer Systems 10th Lecture, Feb 14, 2013

Instructors: Seth Copen Goldstein, Anthony Rowe, Greg Kesden

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Carnegie Mellon Carnegie Mellon

Byte‐Oriented Memory Organization Simple Memory Addressing Modes

 Normal (R) Mem[Reg[R]] • • • . Register R specifies memory address . Aha! Pointer dereferencing in

 Programs refer to by address movl (%ecx),%eax . Conceptually, envision it as a very large array of . In reality, it’s not, but can think of it that way . An address is like an index into that array  Displacement D(R) Mem[Reg[R]+D] . and, a pointer variable stores an address . Register R specifies start of memory region . Constant displacement D specifies offset  Note: system provides private address spaces to each “process” . Think of a process as a program being executed movl 8(%ebp),%edx . So, a program can clobber its own data, but not that of others

nd th From 2 lecture 3 From 5 lecture 4 Carnegie Mellon Carnegie Mellon Traditional Bus Structure Connecting Memory Read Transaction (1) CPU and Memory

 CPU places address A on the memory bus.  A bus is a collection of parallel wires that carry address, data, and control signals.

 Buses are typically shared by multiple devices. Load operation: movl A, %eax

ALU %eax CPU chip Main memory Register file I/O bridge A 0 Bus interface ALU x A

System bus Memory bus

I/O Main Bus interface bridge memory

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Carnegie Mellon Carnegie Mellon Memory Read Transaction (2) Memory Read Transaction (3)

 Main memory reads A from the memory bus, retrieves  CPU read word xfrom the bus and copies it into register word x, and places it on the bus. %eax.

Register file Register file Load operation: movl A, %eax Load operation: movl A, %eax

ALU ALU %eax %eax x

Main memory Main memory I/O bridge x 0 I/O bridge 0

Bus interface x A Bus interface x A

7 8 Carnegie Mellon Carnegie Mellon Memory Write Transaction (1) Memory Write Transaction (2)

 CPU places address A on bus. Main memory reads it and  CPU places data word yon the bus. waits for the corresponding data word to arrive.

Register file Store operation: movl %eax, A Register file Store operation: movl %eax, A

ALU ALU %eax y %eax y

Main memory Main memory I/O bridge A 0 I/O bridge y 0 Bus interface A Bus interface A

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Carnegie Mellon Carnegie Mellon Memory Write Transaction (3) Dynamic Random‐Access Memory (DRAM)

 Main memory reads data word yfrom the bus and stores  Key features it at address A. . DRAM is traditionally packaged as a chip . Basic storage unit is normally a cell (one bit per cell) register file Store operation: movl %eax, A . Multiple DRAM chips form main memory in most computers ALU %eax y  Technical characteristics main memory . Organized in two dimensions (rows and columns) I/O bridge 0 . To access (within a DRAM chip): select row then select column nd bus interface y A . Consequence: 2 access to a row faster than different column/row . Each cell stores bit with a capacitor; one transistor is used for access . Value must be refreshed every 10‐100 ms . Done within the hardware

11 12 Carnegie Mellon Carnegie Mellon Conventional DRAM Organization Reading DRAM Supercell (2,1) Step 1(a): Row access strobe (RAS) selects row 2.  dxwDRAM: Step 1(b): Row 2 copied from DRAM array to row buffer. . dw total bits organized as d supercells of size wbits

16 x 8 DRAM chip 16 x 8 DRAM chip cols Cols 0 123 0 123 RAS = 2 2 2 bits 0 / 0 / addr addr 1 1 rows Rows Memory Memory 2 supercell 2 controller controller (to/from CPU) (2,1) 3 8 3 8 bits / / data data

Internal row buffer Internal row buffer 13 14

Carnegie Mellon Carnegie Mellon Reading DRAM Supercell (2,1) Memory Modules

Step 2(a): Column access strobe (CAS) selects column 1. addr (row = i, col = j) Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually : supercell (i,j)

back to the CPU. DRAM 0 16 x 8 DRAM chip 64 MB memory module Cols DRAM 7 consisting of 0 123 CAS = 1 eight 8Mx8 DRAMs 2 / 0 addr To CPU 1 Rows bits bits bits bits bits bits bits bits Memory 56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7 controller 2

supercell 3 6356 55 48 47 40 39 32 3124 23 16 15 8 7 0 Memory (2,1) 8 / controller data 64-bit doubleword at main memory address A

supercell 64-bit doubleword Internal row buffer (2,1) 15 16 Carnegie Mellon Carnegie Mellon Aside: Nonvolatile Memories Issue: memory access is slow  DRAM and SRAM (caches, on Tuesday) are volatile memories

. Lose information if powered off  DRAM access is much slower than CPU cycle time  Most common nonvolatile storage is the hard disk . A DRAM chip has access times of 30‐50ns . Rotating platters (like )… plentiful capacity, but very slow . and, transferring from main memory into register  Nonvolatile memories retain value even if powered off . Read‐only memory (ROM): programmed during production can take 3X or more longer than that . Programmable ROM (PROM): can be programmed once . With sub‐nanosecond cycles times, . Eraseable PROM (EPROM): can be bulk erased (UV, X‐Ray) 100s of cycles per memory access . Electrically eraseable PROM (EEPROM): electronic erase capability . and, the gap grows over time . : with partial (sector) erase capability  . Wears out after about 100,000 erasings Consequence: memory access efficiency crucial to performance  Uses for Nonvolatile Memories . approximately 1/3 of instructions are loads or stores . Firmware programs stored in a ROM (BIOS, controllers for disks, network . both hardware and programmer have to work at it cards, graphics accelerators, security subsystems,…) . Solid state disks (replace rotating disks in thumb drives, smart phones, mp3 players, tablets, laptops,…) . Disk caches 17 18

Carnegie Mellon Carnegie Mellon The CPU‐Memory Gap Locality to the Rescue! The gap between DRAM, disk, and CPU speeds.

100,000,000.0 Disk The key to bridging this CPU‐Memory gap is a fundamental 10,000,000.0 property of computer programs known as locality 1,000,000.0 SSD 100,000.0

10,000.0 Disk seek time Flash SSD access time DRAM access time 1,000.0

ns SRAM access time DRAM CPU cycle time 100.0 Effective CPU cycle time

10.0

1.0

0.1 CPU

0.0 1980 1985 1990 1995 2000 2003 2005 2010

Year 19 20 Carnegie Mellon Carnegie Mellon Today Locality

 DRAM as building block for main memory  Principle of Locality: Programs tend to use data and  Locality of reference instructions with addresses near or equal to those they  Caching in the memory hierarchy have used recently  Storage technologies and trends

 Temporal locality: . Recently referenced items are likely to be referenced again in the near future

 Spatial locality: . Items with nearby addresses tend to be referenced close together in time

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Carnegie Mellon Carnegie Mellon Locality Example Qualitative Estimates of Locality

 Claim: Being able to look at code and get a qualitative sum = 0; for (i = 0; i < n; i++) sense of its locality is a key skill for a professional sum += a[i]; programmer. return sum;

 Data references  Question: Does this function have good locality with . Reference array elements in succession respect to array a? (stride‐1 reference pattern). Spatial locality . Reference variable sum each iteration. Temporal locality int sum_array_rows(int a[M][N]) {  Instruction references int i, j, sum = 0; . Reference instructions in sequence. Spatial locality . Cycle through loop repeatedly. Temporal locality for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum; }

23 24 Carnegie Mellon Carnegie Mellon Locality Example Today

 Question: Does this function have good locality with  DRAM as building block for main memory respect to array a?  Locality of reference  Caching in the memory hierarchy int sum_array_cols(int a[M][N])  Storage technologies and trends { int i, j, sum = 0;

for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum; }

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Carnegie Mellon Carnegie Mellon Memory Hierarchies An Example Memory Hierarchy

L0:  Some fundamental and enduring properties of hardware and CPU registers hold words retrieved Registers from L1 software: L1: L1 cache . Fast storage technologies cost more per , have less Smaller, (SRAM) L1 cache holds cache lines retrieved from L2 cache capacity, and require more power (heat!) faster, costlier L2: L2 cache per byte . The gap between CPU and main memory speed is widening (SRAM) L2 cache holds cache lines retrieved from main memory . Well‐written programs tend to exhibit good locality L3: Larger, Main memory (DRAM) Main memory holds disk blocks slower, retrieved from local disks  These fundamental properties complement each other cheaper per byte L4: Local secondary storage Local disks hold files beautifully (local disks) retrieved from disks on remote network servers

 They suggest an approach for organizing memory and Remote secondary storage L5: (tapes, distributed file systems, Web servers) storage systems known as a memory hierarchy

27 28 Carnegie Mellon Carnegie Mellon Caches General Cache Concepts

 Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Smaller, faster, more expensive  Fundamental idea of a memory hierarchy: Cache 84 9 1410 3 memory caches a subset of . For each k, the faster, smaller device at level kserves as a cache for the the blocks larger, slower device at level k+1. Data is copied in block‐sized  Why do memory hierarchies work? 104 transfer units . Because of locality, programs tend to access the data at level kmore often than they access the data at level k+1. Larger, slower, cheaper memory . Thus, the storage at level k+1 can be slower, and thus larger and Memory 0 1 2 3 viewed as partitioned into “blocks” cheaper per bit. 4 5 6 7  Big Idea: The memory hierarchy creates a large pool of 8 9 10 11 storage that costs as much as the cheap storage near the 12 13 14 15 bottom, but that serves data to programs at the rate of the fast storage near the top. 29 30

Carnegie Mellon Carnegie Mellon General Cache Concepts: Hit How locality induces cache hits

Request: 14 Data in block b is needed  Temporal locality: Block b is in cache: . 2nd through Nth accesses to same Cache 8 9 14 3 Hit! location will be hits

 Spatial locality: . Cache blocks contains multiple words, so 2nd to Nth word accesses can be hits Memory 0 1 2 3 on cache block loaded for 1st word 4 5 6 7 . Row buffer in DRAM is another example 8 9 10 11 12 13 14 15

31 32 Carnegie Mellon Carnegie Mellon General Caching Concepts: General Cache Concepts: Miss Types of Cache Misses

Request: 12 Data in block b is needed  Cold (compulsory) miss Block b is not in cache: . The first access to a block has to be a miss 8 129 14 3 Cache Miss! . Most cold misses occur at the beginning, because the cache is empty  Conflict miss Block b is fetched from Request: 12 . Most caches limit blocks at level k+1 to a small subset (sometimes a 12 memory singleton) of the block positions at level k . E.g., Block iat level k+1 must be placed in block (i mod 4) at level k Block b is stored in cache Memory 0 1 2 3 • Placement policy: . Conflict misses occur when the level kcache is large enough, but multiple 4 5 6 7 determines where b goes data objects all map to the same level kblock • Replacement policy: 8 9 10 11 . E.g., Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every time determines which block 12 13 14 15 gets evicted (victim)  Capacity miss . Occurs when the set of active cache blocks () is larger than the cache

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Carnegie Mellon Carnegie Mellon Examples of Caching in the Hierarchy Memory hierarchy summary

 The speed gap between CPU, memory and mass storage Cache Type What is Cached? Where is it Cached? Latency (cycles) Managed By continues to widen Registers 4‐8 bytes words CPU core 0 Compiler TLB Address translations On‐Chip TLB 0 Hardware  Well‐written programs exhibit a property called locality L1 cache 64‐bytes block On‐Chip L1 1 Hardware L2 cache 64‐bytes block On/Off‐Chip L2 10 Hardware  4‐KB page Main memory 100 Hardware + OS Memory hierarchies based on caching close the gap by Buffer cache Parts of files Main memory 100 OS exploiting locality Disk cache Disk sectors Disk controller 100,000 Disk firmware Network buffer Parts of files Local disk 10,000,000 AFS/NFS client cache Browser cache Web pages Local disk 10,000,000 Web browser

Web cache Web pages Remote server disks 1,000,000,000 Web proxy server

35 36 Carnegie Mellon Carnegie Mellon Today What’s Inside A Disk Drive?

 DRAM as building block for main memory Spindle Arm Platters  Locality of reference  Caching in the memory hierarchy  Storage technologies and trends Actuator

Electronics (including a SCSI and memory!) connector

Image courtesy of Seagate Technology

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Carnegie Mellon Carnegie Mellon Disk Geometry Disk Geometry (Muliple‐Platter View)

 Disks consist of platters, each with two surfaces.  Aligned tracks form a cylinder.  Each surface consists of concentric rings called tracks. Cylinder k  Each track consists of sectors separated by gaps. Surface 0 Platter 0 Surface 1 Tracks Surface 2 Surface Platter 1 Surface 3 Track k Gaps Surface 4 Platter 2 Surface 5

Spindle Spindle

Sectors

39 40 Carnegie Mellon Carnegie Mellon Disk Capacity Computing Disk Capacity

 Capacity: maximum number of bits that can be stored. Capacity = (# bytes/sector) x(avg. # sectors/track) x . Vendors express capacity in units of (GB), where (# tracks/surface) x(# surfaces/platter) x 1 GB = 109 Bytes (Lawsuit claims deceptive advertising). (# platters/disk)  Capacity is determined by these technology factors: Example: . Recording density (bits/in): number of bits that can be squeezed . 512 bytes/sector into a 1 inch segment of a track. . 300 sectors/track (on average) . Track density (tracks/in): number of tracks that can be squeezed . 20,000 tracks/surface into a 1 inch radial segment. . 2 surfaces/platter . . Areal density (bits/in2): product of recording and track density. 5 platters/disk

 Modern disks partition tracks into disjoint subsets called Capacity = 512 x 300 x 20000 x2 x5 recording zones = 30,720,000,000 . Each track in a zone has the same number of sectors, determined = 30.72 GB by the circumference of innermost track. . Each zone has a different number of sectors/track

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Carnegie Mellon Carnegie Mellon Disk Operation (Single‐Platter View) Disk Operation (Multi‐Platter View)

Read/write heads The disk surface move in unison The read/write head spins at a fixed from cylinder to cylinder is attached to the end rotational rate of the arm and flies over the disk surface on a thin cushion of air. Arm spindle

spindle spindle spindle Spindle

By moving radially, the arm can position the read/write head over any track.

43 44 Carnegie Mellon Carnegie Mellon Disk Structure ‐ top view of single platter Disk Access

Surface organized into tracks

Tracks divided into sectors

Head in position above a track

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Carnegie Mellon Carnegie Mellon Disk Access Disk Access –Read

Rotation is counter-clockwise About to read blue sector

47 48 Carnegie Mellon Carnegie Mellon Disk Access –Read Disk Access –Read

After BLUE read After BLUE read

After reading blue sector Red request scheduled next

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Carnegie Mellon Carnegie Mellon Disk Access – Seek Disk Access –Rotational Latency

After BLUE read Seek for RED After BLUE read Seek for RED Rotational latency

Seek to red’s track Wait for red sector to rotate around

51 52 Carnegie Mellon Carnegie Mellon Disk Access –Read Disk Access – Service Time Components

After BLUE read Seek for RED Rotational latency After RED read After BLUE read Seek for RED Rotational latency After RED read

Complete read of red Data transfer Seek Rotational Data transfer latency

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Carnegie Mellon Carnegie Mellon Disk Access Time Disk Access Time Example

 Average time to access some target sector approximated by :  Given: . Taccess = Tavg seek + Tavg rotation + Tavg transfer . Rotational rate = 7,200 RPM  Seek time (Tavg seek) . Average seek time = 9 ms. . Time to position heads over cylinder containing target sector. . Avg # sectors/track = 400. . Typical Tavg seek is 3—9 ms  Derived:  Rotational latency (Tavg rotation) . Tavg rotation = 1/2 x(60 secs/7200 RPM) x 1000 ms/sec = 4 ms. . Time waiting for first bit of target sector to pass under r/w head. . Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms . Tavg rotation = 1/2 x1/RPMs x60 sec/1 min . Taccess = 9 ms + 4 ms + 0.02 ms . Typical Tavg rotation = 7200 RPMs  Important points:  Transfer time (Tavg transfer) . Access time dominated by seek time and rotational latency. . Time to read the bits in the target sector. . First bit in a sector is the most expensive, the rest are free. . Tavg transfer = 1/RPM x1/(avg # sectors/track) x60 secs/1 min. . SRAM access time is about 4 ns/doubleword, DRAM about 60 ns . Disk is about 40,000 times slower than SRAM, . 2,500 times slower then DRAM. 55 56 Carnegie Mellon Carnegie Mellon Blocks I/O Bus CPU chip  Modern disks present a simpler abstract view of the Register file

complex sector geometry: ALU . The set of available sectors is modeled as a sequence of b‐sized System bus Memory bus logical blocks (0, 1, 2, ...)  Mapping between logical blocks and actual (physical) I/O Main Bus interface sectors bridge memory . Maintained by hardware/firmware device called disk controller. . Converts requests for logical blocks into (surface,track,sector) triples. I/O bus Expansion slots for  Allows controller to set aside spare cylinders for each other devices such zone. USB Graphics Disk as network adapters. controller . Accounts for the difference in “formatted capacity” and “maximum adapter controller capacity”. Mouse Keyboard Monitor Disk

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Carnegie Mellon Carnegie Mellon Reading a Disk Sector (1) Reading a Disk Sector (2) CPU chip CPU chip Register file CPU initiates a disk read by writing a Register file Disk controller reads the sector and command, logical block number, and performs a direct memory access ALU destination memory address to a port ALU (DMA) transfer into main memory. (address) associated with disk controller.

Main Main Bus interface Bus interface memory memory

I/O bus I/O bus

USB Graphics Disk USB Graphics Disk controller adapter controller controller adapter controller

mouse keyboard Monitor Mouse Keyboard Monitor Disk Disk 59 60 Carnegie Mellon Carnegie Mellon Reading a Disk Sector (3) Solid State Disks (SSDs) I/O bus CPU chip When the DMA transfer completes, Register file the disk controller notifies the CPU Requests to read and write logical disk blocks ALU with an interrupt (i.e., asserts a Solid State Disk (SSD) special “interrupt” pin on the CPU) Flash translation layer

Main Flash memory Bus interface memory Block 0 Block B-1 Page 0 Page 1 … Page P-1 … Page 0 Page 1 … Page P-1 I/O bus

 Pages: 512KB to 4KB, Blocks: 32 to 128 pages USB Graphics Disk  Data read/written in units of pages. controller adapter controller  Page can be written only after its block has been erased Mouse Keyboard Monitor  A block wears out after 100,000 repeated writes. Disk 61 62

Carnegie Mellon Carnegie Mellon SSD Performance Characteristics SSD Tradeoffs vs Rotating Disks

 Advantages Sequential read tput 250 MB/s Sequential write tput 170 MB/s . No moving parts  faster, less power, more rugged Random read tput 140 MB/s Random write tput 14 MB/s Rand read access 30 us Random write access 300 us  Disadvantages . Have the potential to wear out  Why are random writes so slow? . Mitigated by “wear leveling logic” in flash translation layer . Erasing a block is slow (around 1 ms) . E.g. Intel X25 guarantees 1 petabyte (1015 bytes) of random . Write to a page triggers a copy of all useful pages in the block writes before they wear out . Find an used block (new block) and erase it . In 2010, about 100 times more expensive per byte . Write the page into the new block (Now more like 10‐15x) . Copy other pages from old block to the new block  Applications . MP3 players, smart phones, laptops . Beginning to appear in desktops and servers

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Storage Trends CPU Clock Rates Inflection point in computer history when designers hit the “Power Wall” SRAM Metric 1980 1985 1990 1995 2000 2005 2010 2010:1980 1980 1990 1995 2000 2003 2005 2010 2010:1980 $/MB 19,200 2,900 320 256 100 75 60 320 access (ns) 300 150 35 15 3 2 1.5 200 CPU 8080 386 Pentium P-III P-4 Core 2 Core i7 ---

DRAM (MHz) 1 20 150 600 3300 2000 2500 2500 Metric 1980 1985 1990 1995 2000 2005 2010 2010:1980 Cycle $/MB 8,000 880 100 30 1 0.1 0.06 130,000 time (ns) 1000 50 6 1.6 0.3 0.50 0.4 2500 access (ns) 375 200 100 70 60 50 40 9 typical size (MB) 0.064 0.256 4 16 64 2,000 8,000 125,000 Cores11111244 Disk Effective Metric 1980 1985 1990 1995 2000 2005 2010 2010:1980 cycle 1000 50 6 1.6 0.3 0.25 0.1 10,000 time (ns) $/MB 500 100 8 0.30 0.01 0.005 0.0003 1,600,000 access (ms) 87 75 28 10 8 4329 typical size (MB) 1 10 160 1,000 20,000 160,000 1,500,0001,500,000 65 66

Carnegie Mellon Carnegie Mellon Random‐Access Memory (RAM) SRAM vs DRAM Summary

 Key features . RAM is traditionally packaged as a chip. . Basic storage unit is normally a cell (one bit per cell). Trans. Access Needs Needs . Multiple RAM chips form a memory. per bit time refresh? EDC? Cost Applications  Static RAM (SRAM) . Each cell stores a bit with a four or six‐transistor circuit. SRAM 4 or 6 1X No Maybe 100x Cache memories . Retains value indefinitely, as long as it is kept powered. DRAM 1 10X Yes Yes 1X Main memories, . Relatively insensitive to electrical noise (EMI), radiation, etc. frame buffers . Faster and more expensive than DRAM.  Dynamic RAM (DRAM) . Each cell stores bit with a capacitor. One transistor is used for access . Value must be refreshed every 10‐100 ms. . More sensitive to disturbances (EMI, radiation,…) than SRAM. . Slower and cheaper than SRAM. 67 68 Carnegie Mellon Carnegie Mellon Enhanced DRAMs Locality Example

 Basic DRAM cell has not changed since its invention in 1966.  Question: Can you permute the loops so that the function . Commercialized by Intel in 1970. scans the 3‐d array a with a stride‐1 reference pattern  DRAM cores with better interface logic and faster I/O : (and thus has good spatial locality)? . Synchronous DRAM (SDRAM) . Uses a conventional clock signal instead of asynchronous control int sum_array_3d(int a[M][N][N]) . Allows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS) { int i, j, k, sum = 0;

. Double data‐rate synchronous DRAM (DDR SDRAM) for (i = 0; i < M; i++) . Double edge clocking sends two bits per cycle per pin for (j = 0; j < N; j++) for (k = 0; k < N; k++) . Different types distinguished by size of small prefetch buffer: sum += a[k][i][j]; – DDR (2 bits), DDR2 (4 bits), DDR4 (8 bits) return sum; . By 2010, standard for most server and desktop systems } . Intel Core i7 supports only DDR3 SDRAM

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