Qoriq T2081 Data Sheet
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NXP Semiconductors Document Number T2081 Data Sheet: Technical Data Rev. 3, 03/2018 T2081 QorIQ T2081 Data Sheet Features • 8 SerDes lanes at up to 10 GHz • 4 e6500 cores built on Power Architecture® • 6 Ethernet interfaces, supporting combinations of: technology sharing a 2 MB L2 cache – Up to two 10 Gbps Ethernet MACs – Up to six 1 Gbps Ethernet MACs • 512 KB CoreNet platform cache (CPC) – Up to two 2.5Gbps Ethernet MACs • Hierarchical interconnect fabric – IEEE Std 1588™ support – CoreNet fabric supporting coherent and non- • High-speed peripheral interfaces coherent transactions with prioritization and – Four PCI Express controllers (two support PCIe 2.0 bandwidth allocation amongst CoreNet end-points and two support PCIe 3.0) – Queue Manager (QMan) fabric supporting packet- level queue management and quality of service • Additional peripheral interfaces scheduling – Two high-speed USB 2.0 controllers with integrated PHY • One 32-/64-bit DDR3 SDRAM memory controller – Enhanced secure digital host controller (SD/MMC/ – DDR3 and DDR3L with ECC and interleaving eMMC) support – Enhanced Serial peripheral interface (eSPI) – Memory pre-fetch engine – Four I2C controllers • Data Path Acceleration Architecture (DPAA) – Four 2-pin UARTs or two 4-pin UARTs incorporating acceleration for the following functions: – Integrated flash controller supporting NAND and – Packet parsing, classification, and distribution NOR flash (Frame Manager 1.1) • Three 8-channel DMA engines – Queue management for scheduling, packet sequencing, and congestion management (Queue • 780 FC-PBGA package, 23 mm x 23 mm, 0.8mm pitch Manager 1.1) – Hardware buffer management for buffer allocation and de-allocation (Buffer Manager 1.1) – Cryptography Acceleration (SEC 5.2) – RegEx Pattern Matching Acceleration (PME 2.1) – Decompression/Compression Acceleration (DCE 1.0) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Table of Contents 1 Overview.............................................................................................. 3 3.16 JTAG controller.........................................................................86 2 Pin assignments....................................................................................3 3.17 I2C interface.............................................................................. 89 2.1 784 ball layout diagrams........................................................... 4 3.18 GPIO interface...........................................................................92 2.2 Pinout list...................................................................................10 3.19 High-speed serial interfaces (HSSI).......................................... 94 3 Electrical characteristics.......................................................................39 4 Hardware design considerations...........................................................128 3.1 Overall DC electrical characteristics.........................................39 4.1 System clocking........................................................................ 128 3.2 Power sequencing......................................................................45 4.2 Power supply design..................................................................133 3.3 Power-down requirements.........................................................48 4.3 Decoupling recommendations...................................................142 3.4 Power characteristics.................................................................48 4.4 SerDes block power supply decoupling recommendations.......142 3.5 Power-on ramp rate................................................................... 53 4.5 Connection recommendations................................................... 143 3.6 Input clocks............................................................................... 54 4.6 Thermal......................................................................................149 3.7 RESET initialization..................................................................58 4.7 Recommended thermal model...................................................150 3.8 DDR3 and DDR3L SDRAM controller.................................... 59 4.8 Thermal management information............................................ 150 3.9 eSPI interface.............................................................................65 5 Package information.............................................................................152 3.10 DUART interface...................................................................... 68 5.1 Package parameters for the FC-PBGA......................................152 3.11 Ethernet interface, Ethernet management interface 1 and 2, 5.2 Mechanical dimensions of the FC-PBGA................................. 152 IEEE Std 1588........................................................................... 69 6 Security fuse processor.........................................................................154 3.12 USB interface............................................................................ 77 7 Ordering information............................................................................154 3.13 Integrated flash controller..........................................................79 7.1 Part numbering nomenclature....................................................154 3.14 Enhanced secure digital host controller (eSDHC).....................82 7.2 Orderable part numbers addressed by this document................155 3.15 Multicore programmable interrupt controller (MPIC).............. 86 8 Revision history....................................................................................157 QorIQ T2081 Data Sheet, Rev. 3, 03/2018 2 NXP Semiconductors Overview 1 Overview The T2081 QorIQ integrated multicore communications processor combines 4 dual- threaded cores built on Power Architecture® technology with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/ datacom, wireless infrastructure, and military/aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, gateways, and general-purpose embedded computing systems. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also simplifying board design. This figure shows the block diagram of the chip. Power Architecture Power Architecture Power Architecture Power Architecture e6500 e6500 e6500 e6500 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache 2 MB Banked L2 512 KB 64-bit DDR3/3L Plat Cache with ECC Pre-Fetch MPIC CoreNet TM PreBoot Loader Coherency Fabric Security Monitor PAMU PAMU PAMU (peripheral access management unit) Internal BootROM Power mgmt FMan Real-time SEC QMan debug SDXC/eMMC Parse, classify, distribute DMAx3 Watch point eSPI Buffer cross- BMan trigger PME DCB 2 x DUART Perf Trace Monitor DCE 1GE 1GE 1GE 4x I2C 2x 2.5/10G 1GE 1GE 1GE PCle PCle PCle IFC PCIe 2 x USB2.0 w/PHY 8 lanes up to 10 GHz SerDes Clocks/Reset GPIO CCSR Figure 1. Block diagram 2 Pin assignments QorIQ T2081 Data Sheet, Rev. 3, 03/2018 NXP Semiconductors 3 Pin assignments 2.1 784 ball layout diagrams This figure shows the complete view of the T2081 ball map diagram. Figure 3, Figure 4, Figure 5, and Figure 6 show quadrant views. QorIQ T2081 Data Sheet, Rev. 3, 03/2018 4 NXP Semiconductors Pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A A B B C C D D E E F SEE DETAIL A SEE DETAIL B F G G H H J J K K L L M M N N P P R R T T U U V V W W Y SEE DETAIL C SEE DETAIL D Y AA AA AB AB AC AC AD AD AE AE AF AF AG AG AH AH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DDR Interface 1 IFC DUART I2C eSPI eSDXC MPIC LP Trust Trust System Control ASLEEP SYSCLK DDR Clocking RTC Debug DFT JTAG Analog Signals Serdes 1 USB PHY 1 and 2 IEEE1588 Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1 Ethernet Cont. 2 DMA Power Ground No Connects Figure 2. Complete BGA Map for the T2081 QorIQ T2081 Data Sheet, Rev. 3, 03/2018 NXP Semiconductors 5 Pin assignments 1 2 3 4 5 6 7 8 9 1011121314 IRQ_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ A GND001 OUT_B AD00 AD02 AD04 AD05 AD07 AD09 AD10 AD12 AD14 AD15 IFC_BCTL A RESET_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ B GND004 ASLEEP REQ_B GND005 AD01 AD03 GND006 AD06 AD08 GND007 AD11 AD13 GND008 TE B IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ C EVT2_B EVT3_B EVT4_B EVT1_B A16 A17 A19 A21 A23 A25 A27 A29 CS0_B PAR1 C IFC_ D IRQ03 GND016 IRQ01 IRQ04 IRQ05 EVT0_B IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_ NDDDR_ D A18 A20 A22 A24 A28 A30 WE0_B CLK USB1_ E USB_ USB_ USB_ VBUS GND020 CLK_ GND021 HRESET_ IRQ02 GND022 IFC_ IFC_ GND023 IFC_ E AGND01 AGND02 AGND03 CLMP OUT B A26 A31 PERR_B USB1_ USB1_ F USB1_ USB1_ USB_ USB1_ PWR DRV IRQ00 USBCLK SCAN_ TH_ PROG_ PROG_ PORESET_ NC01 F UDP UDM AGND04 UID FAULT VBUS MODE_B TPA MTR SFP B USB_ USB_ USB_ USB_ IBIAS_ USB_ NC02 GND030 TEST_ TH_ AVDD_ AVDD_ AVDD_ GND031 NC03 G AGND05 AGND06 AGND07 AGND08 SEL_B VDD PLAT CGA1 CGA2 G REXT USB2_ USB2_ USB_ USB2_ USB2_ H PWR NC05 GND035 GND036 GND037 GND038 GND039 GND040 GND041 GND042 H UDP UDM AGND09 UID FAULT USB2_ USB2_ J USB_ USB_ USB_ VBUS DRV NC06 GND050 USB_ USB_ USB_ OVDD01 OVDD02 OVDD03 OVDD04 J AGND10 AGND11 AGND12 CLMP VBUS