Qoriq: High End Industrial and Networking Processing

TechDays 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, trademarks of Freescale Semiconductor, Inc. All other product or service names are the BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, TM property of their respective owners. © 2012 Freescale Semiconductor, Inc. 1 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All . other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. 2013 2011 QorIQ Qonverge QorIQ next-generation platform launch platform based T series 28nm on Layerscape architecture 2008 QorIQ Multicore Platform launch (P series) Accelerating the P series 45nm Network’s IQ 2004 Dual-core processor MPC8641D with e600 core

2002 90nm Host Processors QorIQ MPC744X with e600 core The smarter approach 20 Years of Networking 1995 to multicore PowerQUICC Ingenuity from processors launch the #1 Leader in Communications Processing

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. TM 2 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc.

• LS3 (future) High-performance Tier • T4240/T4160 • Up to 2.4 GHz • P5040/P5021 • 1 to 24 cores • P5020/P5010 • Large L2 caches • P4080/P4040 Service Provider Network Storage Routers Admission Control Networks

Mid-performance Tier • LS2 (future) • Up to 1.8 GHz • T2080/T2081 • Highly-parallelized workloads • P3041 • 48 Gbps IP forwarding • P20x(4) • High amount of off-load Metro Carrier Aerospace Access Edge Router & Defense Gateway

Value-performance Tier • LS1 families • Up to 1.8 GHz • T1040/T1042 • 3W fanless designs • T1020/T1022 • Broadest portfolio of power- • P101x(8), P102x(5), efficient SoCs UTM Security Industrial Computing Enterprise Appliances & Networking Routers/Switches

Processor Power Architecture™ • e500v2, 32b, 533 - 800 MHz e500v2 Core • 36-bit physical addressing 16/32-bit • Memory SubSystem 32KB 32KB 256KB DDR3/3L • 256KB Frontside L2 cache w/ECC D-Cache I-Cache Platform Cache Memory Controller • 32-bit DDR3/3L, 800 MHz data rate Security Fuse Proc Coherent System Bus • 16-bit DDR3/3L, 800 MHz data rate w/ECC Security Monitor High Speed Serial IO Real Time Debug USB 2.0 w/PHY SEC • 2 PCIe 1.1 Controllers (2.5GHz) 4.4 DMA

IFC, TDM JTAG • 2 SATA 2.0 3Gb/s

(XOR,

Power Management

CRC) 2.0

2.0 • 1 USB 2.0 with PHY

SD/MMC • Host/Device support

2x DUART

eTSEC

eTSEC eTSEC

PCIe

PCIe FlexCAN

FlexCAN • 2 FlexCAN 2.0b Controllers SATA SATA 2x I2C SATA Network IO SPI, GPIO • 3 eTSECs (10/100/1000) 6-Lanes 3.125GHz • Software fastpath acceleration SERDES • 1588v2 support Device • Up to 2 with SGMII • 45nm SOI Process Misc IO • 425-pin TEPBGA I • TDM • 19 x19mm, 0.8mm pitch • Flash Controller supporting NOR, SLC and MLC Power based NAND devices • <3W • SD/MMC card controller • -40C to +105C Tj • 2x DUARTs, 2x I2Cs Acceleration • SEC 4.4 - crypto acceleration 2Gbps • Secure Boot

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 4 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Not on P1012 Dual e500v2 Power Architecture cores Not on P1016 • 533-800 MHz Security DDR2/DDR3, • 256 KB frontside L2 cache w/ECC, HW cache Accel e500 e500 SDRAM 32b Controller coherent XOR Cores 256 KB Core • 36-bit physical addressing, DP-FPU 16b Enhanced Local System unit L2 Bus 32 KB 32 KB 32 KB 32 KB • 32-bit DDR2/DDR3, 667 MHz data rate w/ECC I- D- I- D- Perf Mon, Cache Cache Cache Cache • Integrated SEC 3.3 security engine DUART, MPIC 2x I2C, Timers • Open programmable interrupt controller, perf mon, 2x I2C, timers, 16 GPIOs, DUART USB2.0 Coherency Module • 16-bit enhanced local bus supports booting from NAND Flash SD/MMC • USB 2.0 controllers host/device support SystemSystem Bus Bus SPI • SPI controller supporting booting from SPI serial Flash • SD/MMC card controller supporting booting from QUICC Flash cards Engine 3x On-Chip Network GE • Three 10/100/1000 Ethernet controllers (VeTSEC) PCI PCI UTOPIA, MAC DMA w/jumbo frame support, SGMII interface Express Express TDM, MII • IEEE1588 v2 support • QUICC Engine for protocol offload and legacy interfaces x4 SerDes • TDM interfaces with HDLC support • UTOPIA-L2 interface for ATM support • Two PCI Express 1.0a controllers operating up to 2.5 Gbps • P1025/P1016 product option available in small foot print package • Power management Process and package • Supports 400-667 MHz operation • 45nm SOI, 0.95V+/-50mV, -40C to 125C Tj • DDR3 only for lowest possible power • 689-pin TePBGAII • 561-pin TePBGA-1, 23 mm x 23 mm <5W max for 800 MHz

Apps

Media Energy

Medical

Industrial Transport Stacks Enterprise IP Routing / Firewall / VPN Java VM Gateway OS

Power QorIQ Kinetis i.MX QUICC

Wired and Wireless Sensors Backhaul

Software: ® MSRP: $199 • Linux 3.0 SDK Launch: April 2012 • MQX™ RTOS First Deliveries: May 2012 • CodeWarrior IDE

• Demo kit with 5x Tower System end applications • 100% compliant with Tower System infrastructure

Physical RS-485 PHY • PROFIBUS development services Layer 1 Customer Third-Party or Customer Freescale

Freescale www.freescale.com/PROFIBUS • QorIQ and PowerQUICC processors • Tower System with Linux® OS • email: [email protected]

freescale.com/PROFIBUS

Manufacturing/Power/Building Gateway Safety Gateway Non Real Time Real Non

Programmable Logic Controller [PLC] Human Machine Transport Motion Logic Interface Control Control Safety [HMI] Reliable Safe Drive Control Latency Safety

> 3M (2011) Time Real > 3M (2011) Motor Actuator Sensor Button Bulb Sensor Button Bulb Button Bulb

> 35M (2011)

Industrial Ethernet (2009) January 2011

Certified on Ported to QorIQ SerialQorIQ Multi* Drop Field bus Compatibility Industrial Ethernet protocols

Master / Slave* Siemens   Slave Siemens Rockwell   Rockwell

Many   Beckhoff (Master)

− The standard defines a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a distributed system

− Intended for local area networks using multicast communications (including Ethernet)

− IEEE 1588 was designed to work within a building or factory

. Intended typically for industrial automation and test and measurement systems (e.g. synchronized printing presses)

− Targeted accuracy of microsecond to sub-microsecond

− Version 1 approved September 2002 and published November 2002

− Version 2 approved March 2008 and published August 2008

− Available from the IEEE 1588 web site (http://ieee1588.nist.gov)

NETWORK NETWORK

Node A: Node B: Node C: Node A: Node B: Node C: Time = 9:04 Time = 9:29 Time = 9:28 Time = 9:04 Time = 9:04 Time = 9:04

eOpenPIC High speed interconnect CoreNet • 3 PCIe 2.0 Controllers PreBoot Loader Coherency Fabric • 2 sRapidIO 2.1 Controllers Peripheral Security Monitor PAMU PAMU PAMU PAMU PAMU Access Mgmt Unit . Type 9 and 11 messaging Internal BootROM • 2 SATA 2.0

Power Mgmt CoreNet switch fabric Frame Manager Real Time SD/MMC DMA Debug Ethernet eLBC SEC Queue

x2 Watchpoint SPI 4.0 Mgr. Parse, Classify, • 5 x 10/100/1000 Ethernet controllers 16b Distribute Cross Trigger . Or 4x 2.5 Gbps SGMII 2x DUART

Pattern Buffer • 1 x 10GE controller

Perf CoreNet

Rapid 4x I 2 C Match Buffer 1GE Monitor Trace • All w/ classification, H/W queuing, policing,

1GE 2.0 SATA IO 2.0 SATA

Engine Mgr.

PCIe PCIe

10GE 1GE PCIe

2x USB 2.0 PHY RMan 2.0 buffer management, checksum offload, SRIO 1GE SRIO Aurora 1GE QoS, lossless flow control, IEEE® 1588 Clocks/Reset • Up to 5 SGMII or 2.5 Gbps SGMII, 2 RGMII GPIO 10-Lane 5 GHz SerDes Data path acceleration CCSR • SEC 4.0 • PME 2.0 Device Qualification Rev 1.1: Jun 2012 • 45nm SOI process • 783-pin package Qualification Rev 2.0: Apr 2013 . 23 x 23 mm, 0.8 mm pitch . Pin compatible with P2040 • 12.5W thermal max (est) w/o I/O at 1.2 GHz

Data path acceleration architecture Power Arch™ Power Arch™ Power Arch™ Power Arch™ • FMan parse/class/distribute/policing Powere6500 Arch™ Powere6500 Arch™ Powere6500 Arch™ Powere6500 Arch™ 2133+ MT/s Powere6500 Arch Powere6500 Arch Powere6500 Arch Powere6500 Arch • QMan queuing, scheduling, shaping e6500 • BMan buffer manager e6500 e6500 e6500 512 KB 64b DDR3 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB Plat Cache w/ECC • Rman RapidIO® manager D-Cache32 KB I-Cache32 KB D-Cache32 KB I-Cache32 KB D-Cache32 KB I-Cache32 KB D-Cache32 KB I-Cache32 KB • PME Reg-ex pattern matcher 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache 512 KB 64b DDR3 • SEC wireless, SSL and IPSec D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache Plat Cache w/ECC encryption 2MB Banked L2 • DCE data compression engine 512 KB 64b DDR3 • TCP/IP offload 2MB Banked L2 Plat Cache w/ECC 2 MB Banked L2 • 40 Gbps IPv4 @ 64B • 20 Gbps IPSec @ IMIX eOpenPIC • 10 Gbps RegEx @ IMIX CoreNet • 20 Gbps compression @ 4KB PreBoot Loader Coherency Fabric Peripheral Security Monitor PAMU PAMU PAMU Access Mgmt Unit Internal BootROM FMan Complex Power Mgmt FMan FMan Real Time SEC QMan 1 Debug

SD/MMC Parse, Classify, Parse, Classify, -

DMAx2 Watchpoint Distribute Distribute Cross SPI BMan PME Buffer Buffer Trigger 2x DUART Perf CoreNet

Monitor Trace

Pre- 1G 1G 1G SATA2.0

1G 1G 1G 2.0 SATA

RMan

2x I 2C Fetch RMAN 1/10G 1/10G 1/10G 1/10G Interlaken LA Interlaken

1G 1G 1G 1G 1G 1G Aurora

sRIO

PCIe3

PCIe3 PCIe3 IFC DCE 2 x USB2.0 w/PHY 32 Lanes up to 10GHz SerDes Clocks/Reset GPIO Up to 24 Gbps per FMan Power target: <50W TDP CCSR

• 64-bit Power Architecture® ISA v2.06 core

T T T T T T T T

• Dual threads provide 1.7 times the

PMC PMC PMC e6500 e6500 e6500 e6500 PMC performance of a single thread • Clustered L2 cache allowing strict allocation 32KB 32KB 32KB 32KB 32KB 32KB 32KB 32KB or full sharing 2MB 16-way Shared L2 Cache, 4 Banks • 128-bit AltiVec SIMD unit ─ 192 GFLOP aggregate CoreNet Interface 40-bit Address Bus 256-bit Rd & Wr Data Busses Large Memory Space CoreNet Double Data Processor Port • 40-bit physical address Core Performance CoreMarkTM Benchmarks Increase Productivity 3x 1.4x • Core Virtualization • Hypervisor • Logical to Real Address Translation

Energy Efficiency • 1.4 to 2 times more power efficient than the nearest competition • Drowsy: core, cluster, AltiVec

Dual 6C/12T server 32 core 12C/24T processors processor T4240 @2.266GHz * @1.5GHz* @1.8GHz CoreMarkTM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, TM Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreMark / Watt TM 13 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. *Source: www.coremark.org Instruction Unit Memory Unit Backside e6500 L2 Cache Instruction Queue Fetch Stages 128K-1MB 32-Kbyte I Cache

Tags Tag & Status Branch Prediction Unit L1 Instruction MMU High-Performance, Low-Power Arrays CTR B 8-Entry 64-Entry LR 512 TEntry L1 VSP L1 TLB 4K Decode B

L2 MMU Characteristics Load/Store Unit (64/32 bit) 64-Entry TLB 512-Entry Array (TLB 1) TLB Array • 128-bit vector size (TLB 0) Data Store Load Miss • Separate register file with 32 registers Queue Queue L1 Data MMU Array Classic • Vector-element datatype of 8, 16, 32-bit signed/unsigned int, Branch Vector Complex Simple Simple 8-Entry 64-Entry Single / Execution Execution Integer Integer Integer Double L1 VSP L1 TLB 4K Unit Units Unit Unit 1 Unit 2 FPU and IEEE SP float Data Line Fill Buffer Data Write Tags VP FP GPR Buffer • 162 instructions R R 32-Kbyte D Cache Rename Buffers • Intra and inter-element arithmetic instructions • Intra and inter-element conditional instructions CoreNet Bus Architecture 36-bit Address Bus 128-bit Rd & Wr Data Buses CoreNet • Powerful Permute, Shift and Rotate, Splat, Pack/Unpack and Merge instructions • Saturation or modulo arithmetic • Four-operand, non-destructive instruction format • Modeless operation for zero-overhead use of AltiVec VA instructions VB • Simultaneous dispatch of one ALU-class vector and one VC permute-class vector, or either paired with a vector load/store • All instructions fully pipelined with single-cycle throughput

op op op op op op op op Vdd Vdd VT e6500 -300 e6500 -300 Core mV0V Core mV

Altivec is a vector architecture allows the simultaneous processing of multiple data Lowered Vdd Power Gating items in parallel. Operations are performed on Technique (Drowsy w/ State (Shut Down) multiple data elements by a single instruction. Retention) This is referred to as Single Instruction Products Applications Multiple Data (SIMD) parallel processing. Use Cases w/o AltiVec with periodic AltiVec

Idle LeakageFreescale, Power the Freescale logo, AltiVec, C-5, CodeTEST,5mW CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions28mW logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM (mW/Core,14 T4240)Package, Processor Expert, QorIQ Qonverge,(90% Qorivva, savings) QUICC Engine, SMARTMOS, TurboLink, VortiQa and(50% Xtrinsic are trademarkssavings) of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Aerospace & Defense Civil Radar Military Radar Counter-measures Avionics Flight computers Flight control systems Displays

Industrial & Communication Image Analysis Multi-axis control Robotics

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. TM 15 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. P Series T Series • DPAA is designed to balance the performance of D$ D$ I$ I$ D$ D$ I$ I$ Accelerators with seamless Integration e500mce500mc … e6500e6500 L2$ L2$ D$ Core D$ I$Core I$ L2$ L2$ D$ Core D$ I$Core I$ … − ANY packet to ANY core to ANY accelerator or network

interface efficiently WITHOUT locks or semaphores. D$ D$ I$ I$ D$ D$ I$ I$ • ―Infrastructure‖ components − Queue Manager (QMan) CoreNet™ Coherency Fabric − Buffer Manager (BMan) • ―Worker‖ Components − Cores DCE DCB − Frame Manager (FMan) RMan RE − RapidIO Message Manager (RMan)

− Cryptographic accelerator (SEC) Sec 4.x PME 2 − Pattern matching engine (PME) − Decompression/Compression Engine (DCE) Queue Buffer Manager Mgr − DCB (Data Center Block) − RAID Engine (RE) Frame Manager Frame Manager 1GE 1GE • CoreNet 10GE Parse, Classify, 1GE 1GE … Distribute … − Provides the interconnect between the cores and the Buffer DPAA infrastructure as well as access to memory. 1G 1G 1G 1/10G 1/10G 1G 1G 1G

APP Layer

EPI Layer

® General Purpose Processing Layer (GPPL) • Core-agnostic (Power Architecture or ARM ® cores)

• Consistent APIs/libraries with tools

Mem. abstract hardware changes CPU(s) Caches Cont. • Single framework for programming

GPPL/APPL

Accelerated Packet Processing Layer (APPL) • Capable of fully autonomous offload Load Pattern L2-L7 Decomp Security Packet • Synchronous run to completion Balance Match Switch Engine Engine Buffer Engine Engine Engine model

System Control System Accelerated Packet Processor • True programmability System InterfacesSystem

Express Packet I/O Layer (EPIL) • Deterministic performance System Visualization (Debug/Tuning) Visualization System Ethernet • Scalability from 1G-100G 100/40/10/1G RapidIO PCI-Express Interlaken • Packetized I/O between all SERDES interfaces supporting L2+ switching

• Performance insights for real-time network adjustments

Package & Board: Package: 525-pin, 19x19mm, 0.8mm pitch Key System Integration Features: Power: ~3.7W @1.0GHz Typical • Low-cost NAND/NOR flash systems Temp: -40C to 105C Tj • DDR3L/4 interface with ECC support Boards: Tower low-cost board • USB3 SuperSpeed Freescale Linux BSPs • Audio networking and motor control

(FMC, QEMU, LXC...)

USDPAA Apps Linux Apps

Linux Kernel (UIO, KVM,...)

Tooling

Debugger

Performance Performance Trace Tooling Trace Linux Networking Drivers (DPAA)

CodeWarrior Tooling Eclipse party

Workbench rd Development Development Host 3 FMan / PCD BMan / QMan MAC / GHS / other tooling other / GHS Driver Driver Port Lib

Eclipse Workbench Runtime environment(s) Runtime FSL Embedded Hypervisor SDK Yocto Build Framework / GNU tools Boot loader (U-Boot) (gcc, gdb, eglibc, binutils)

rd CodeWarrior / 3 Party Platform trust (Secure boot) Debug / Trace Probe Execution targets (boards, simulators) Book ‘E’ Debug

Watchpoint Core Cross Debug Trigger

JTAG/Aurora Perf CoreNet Monitor Trace

Aurora Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 19 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Unified SDK for QorIQ Processors SDK SDK SDK SDK QorIQ T-series, P1-P5, 1.2 1.3 1.4 1.5 select PQ3

Linux 3.0.34 Linux 3.0.51 Linux 3.8.13 Linux 3.8.x

GCC 4.6.2 GCC 4.6.2 GCC 4.7.2 GCC 4.7.2 Yocto 1.x Yocto 1.1 Yocto 1.2 Yocto 1.4

SDK for QorIQ Processors SDK SDK SDK 1.3.2 : with DPAA 1.0 1.1 QorIQ P3-P5 T4240, B4860

Linux 2.6.34 Linux 3.0

GCC 4.5.1 GCC 4.5.2

SDK for QorIQ Processors Current Release without DPAA SDK QorIQ P1-P2, select PQ3 1.0.1 System Builder-based Linux 2.6.35

GCC 4.5.1 Yocto-based

3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 2011 2012 2013

• A no-cost configuration tool for QorIQ platforms based on Freescale’s Processor Expert framework • Generates source files for use in board initialization code • A pure Java solution : − works on Windows, Linux, Solaris, Mac OS,... • Available as an Eclipse plug-in for :

• CodeWarrior Development Studio for Power Architecture v10.x

• Generic Eclipse 3.5.1 or 3.6.1 C/C++ environment

• Available for download now : http://www.freescale.com/qcs

− Pre-Boot Loader (PBL) tool

− DDR configuration tool

− DPAA tool : graphical editor for data path flow configuration

− Device Tree editor : supports references, synchronous GUI & XML editing, node validation based on specification bindings.

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 22 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 23 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, TM 24 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. SW Dev Tools Runtime Software HW and SW Engineering Services Training

Application Specific Software and Solution Integrators

Occasional (SSI)

Middleware Embedded IDH ODM Training Board Partners Solutions

HW Dev Tools Operating Systems

Semiconductors

PowerQUICC Qonverge QorIQ Qorivva

PX Series Common

Communities

For more partner options: Freescale.com/partners