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MPC8560WP2:Powerquicc III Overview: Family of Next Freescale Semiconductor, Inc. White Paper MPC8560WP2 Rev. 1.0, 12/2003 PowerQUICC III™ Overview: Family of Next Generation Integrated Communications Processors NCSD Business Users of communications processors, including system architects and hardware and software . Development engineers, have stated that their platform needs hinge on increasing processing power as well . as increasing interconnect performance while lowering their overall system cost. Significant c enhancements to control and data plane processing, memory, and interconnects are required n to be able to serve the future needs of the imaging, networking, storage, wired and wireless I , communications, and general-purpose computing markets. r With the PowerQUICC III™ family of integrated communications processors, Motorola o t unveils the PowerQUICC III System-on-a-Chip (SoC) architecture, its latest solution c designed for the needs of the embedded markets. The PowerQUICC III family of integrated u communications processors alleviates bottlenecks by combining a high performance core with d high-performance I/O. n o This paper provides an overview of the PowerQUICC III product family and describes how it c delivers enhanced integration together with performance headroom for intensive control plane i processing tasks and increased forwarding plane bandwidth. This paper also highlights market m and technical trends, gives a technical summary of the initial PowerQUICC III offerings, and e provides specific applications examples using the PowerQUICC III as a complete solution. S The following topics are addressed: e Topic Page l a Section 1, “Introduction” 2 c Section 2, “Market Overview” 2 s Section 3, “Feature Introduction” 3 e e Section 4, “Applications” 10 r Section 5, “Summary” 18 F For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Introduction 1 Introduction Motorola, the industry leader in communications processors with more than 5000 design wins and over 82% market share in communications processors (Gartner Dataquest), now offers its next generation integrated communications processor, the PowerQUICC III. The PowerQUICC III is the third generation PowerQUICC family, building on the success of the PowerQUICC I and PowerQUICC II families. In addition to the comprehensive functionality offered by the first members of this family, the advanced, flexible architecture enables easy integration of value-added intellectual property (IP) for future market-specific products. Motorola’s next generation integrated communications processor is positioned to be the premier integrated processor solution in many markets including wireless infrastructure, multiservice access platforms, DSLAM, edge routers, storage, switches, and media gateway. The PowerQUICC III employs a host of leading industry standards and innovative Motorola technologies including the high-performance e500 core that implements the PowerPC™ Book E architecture, RapidIO™ interconnect technology, Motorola’s . OCeaN crossbar switch fabric, dual gigabit Ethernet interfaces, double data rate SDRAM (DDR SDRAM), c and 64-bit PCI-X/PCI interface controllers. n I As a testament to its flexible architecture and System-On-a-Chip (SoC) design, the PowerQUICC III family , provides two different configurations of highly integrated communications processors. The MPC8540 r provides dual gigabit Ethernet interfaces, a dual universal asynchronous receiver transmitter (DUART), a o t four-channel direct memory access (DMA), a multi-channel interrupt controller, one 10/100-Mbit Ethernet c interface, a double data rate (DDR) SDRAM memory controller, a 64-bit PCI-X/PCI controller, and a u RapidIO interconnect. Raising the bar even higher, the MPC8560 offers a full feature set including an d enhanced PowerQUICC II compatible communications processor module (CPM) in addition to all of the n features of the MPC8540. PowerQUICC III’s CPM is a higher performance version of its predecessor in the o PowerQUICC II family operating at speeds of up to 333 MHz and incorporating support for new microcode c i packages. The CPM features three fast serial communications controllers (FCCs), two multi-channel controllers (MCCs), four serial communications controllers (SCCs), one serial peripheral interface (SPI), m 2 and one I C interface. The CPM is software compatible with the PowerQUICC II family, providing the e opportunity to leverage previous investments in Motorola’s PowerQUICC architecture. S e l 2 Market Overview a c Trends in the networking and telecommunications markets are driving the need for more processing s capability to handle more complex algorithms, larger and faster memory subsystems, and higher bandwidth e communications as the amount of data to be processed and forwarded increases. Also, there is an increasing e r demand for tailored services and interworking capability as IP, TDM, ATM, and other protocols are F leveraged across existing core networks. Communications protocols are becoming more complex and are demanding higher performance in communications processors. Traffic engineering techniques in the enterprise routing realm are becoming more complex in order to better control the flow of packets inside an IP network. More complex encapsulation protocols such as multi-protocol label switching (MPLS) provide explicit flow control, but require greater processor involvement. These techniques as well as continuing growth in infrastructure networks will cause a predicted increase in the size of routing tables by 20% in the next year. New routers must support features like multicast, quality of service (QoS), voice, and security, all of which increase the complexity of IP forwarding. As the number of wireless subscribers double, going from one billion today to a predicted two billion in 2005, the demand for customized and tiered applications and services will become more apparent. Services 2 PowerQUICC III Overview: MOTOROLA Family of Next Generation Integrated Communications Processors For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Feature Introduction have become the differentiator for service providers, and thus, they have the challenge of personalizing their service packages. Consolidating IP functionality and voice over IP (VoIP) gateway functionality in DSLAMs will, for example, allow more services to be offered in the DSL market. Today there are several types of networks that communicate via a range of different protocols such as frame relay, IP, TDM, and ATM based standards. Since no single protocol yet dominates the communication industry across all markets and support for existing infrastructure investments will be needed into the foreseeable future, interworking between protocols and equipment will continue to be essential. The following discusses how the PowerQUICC III addresses many of the above concerns facing companies developing solutions for communications markets. Answering the high performance needs of the industry, the Book E architecture e500 core performance yields up to 2.3 MIPs/MHz (est. Dhrystone 2.1) and also contains a signal processing engine (SPE) designed to perform some DSP signal processing tasks such as FFT, FIR, matrix operations, 64-bit load/store operations, and more. The PowerQUICC III core complex also includes a 256-Kbyte second-level (L2) . cache, configurable as high-speed local SRAM that can facilitate content-aware IP forwarding by allowing . c fast examination, storing, and accessing of IP buffer descriptors. This fast memory is located close to the n core to reduce latency issues. The integrated double data rate memory controller will yield higher memory I bandwidth overall allowing data rates of up to 333 MHz. , r The CPM contains a dedicated RISC processor optimized for handling communications and protocol o handling tasks. The functionality supported by this on-chip resource allows implementation of critical t c protocols like ATM Adaptation Layer 2 (AAL2) for important functions such as VoIP and can be modified u via downloadable microcode as well. The CPM functionality enables interworking between different d protocols. n To support the system need for high bandwidth, high reliability, low latency connections between the o various critical components (either on a single board or between boards in a chassis), the PowerQUICC III c i is equipped with a high-speed point-to-point interface called RapidIO. This technology is specifically m designed for high-performance embedded markets. RapidIO, in conjunction with dual gigabit Ethernet e controllers and legacy support such as PCI and 64-bit 133 MHz PCI-X, ensures that the PowerQUICC III S family provides high performance interconnect capability in conjunction with standard programmable interfaces for easy interoperability. e l Simply stated, the PowerQUICC III with its 1 GHz-capable core, 166 MHz (333 MHz data rate) DDR a memory bus, 333 MHz CPM, and a host of other key features empowers the networking and c s communications industry to address the technical challenges facing industry today and in the future. e e r 3 Feature Introduction F Motorola's leading PowerQUICC III architecture integrates two main processing blocks as shown in Figure 1. One block is a high-performance embedded e500 core; the other is the communications processor module (CPM). A description of the e500 core and its performance enhancements follows. Next, the DDR SDRAM memory controller, integrated 10/100/1000 Ethernet controllers, 64-bit PCI-X/PCI controller, RapidIO
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