Vybrid Controllers Technical Overview

June 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • Overview of Vybrid Family • Vybrid Tower Board • Vybrid System Modules • QuadSPI Flash • Vybrid Clock System • Vybrid Power System • Vybrid Boot Operation • High Assurance Boot • Vybrid Trusted Execution • LinuxLink and MQX Embedded Software • DS-5 compiler

TimeSys Linux BSP, Full featured - Mixed signal integration with flexible Freescale MQX RTOS and Eclipse- high-speed12-bit ADCs, 12-bit DACs. based Tools such as ARM DS5, as - Integrated power management well as IAR, and other ARM -Multimedia, Audio, Video Interface ecosystem providers help speed time along with Open VG GPU to market - Exceptional Security Capabilities - External Peripherals and Memory

Rich HMI and Real time Control

40 nm low power process -Real time control enabled with inclusion of ARM Cortex M4. -1.5MB on-chip RAM to enable dual -Static leakage is 2x less than 65nm TFT display without external DRAM -Static leakage is 3x less than 90nm - Sophisticated HMI and multiple -Enables more integration for a given connectivity options 5 Scalable Families power envelope. - Safe, Secure and predictable operation First available broad-market MPU that integrates ARM Cortex-A5 and Cortex-M4!

Industry’s most scalable Real-time, highly integrated Industry’s most versatile solutions ultra-low-power, mixed-signal solutions with best-in-class 2D for multimedia and display MCU solutions based on the graphics to enable your system applications, with multicore ARM® Cortex™-M to control, interface, connect, scalability and market-leading architecture. secure and scale. power, performance & integration.

Consumer Consumer Consumer

Industrial Automotive Automotive Industrial Industrial

Freescale has the industry’s broadest range of solutions built on ARM® technology for automotive, industrial and consumer applications. Find your ideal solution at the price, performance and power level you desire, and leverage the extensive software and tool bundles available to speed and ease your design process.

Cortex-A5 + Cortex-M4 Multicore VF6xx - ARM Cortex-A5 up to 500 MHz + Cortex-M4 up to 167 MHz Dual Heterogeneous Cores, Dual XGA LCD, Camera Interface, Stereo Cortex-A5 Only Audio, DDR, Secure Boot, Tamper Detect, Dual USB OTG w/HS PHY,

Single Core Dual Ethernet, L2 Switch

VF5xx - ARM Cortex-A5 up to 500 MHz SVGA LCD, Camera Interface, Stereo Audio, DDR, Secure

Boot, Tamper Detect, Dual USB OTG w/HS PHY, Dual Ethernet, L2 Switch Feature Integration Feature

VF3xx – ARM Cortex-A5 up to 266 MHZ WQVGA LCD, Audio, Secure Boot, Tamper Detect, USB OTG w/HS PHY, Dual Ethernet, L2 Switch, Dual Quad-SPI, NAND Flash Controller

Performance

Analog and Digital

)

CRC 12-bit ADC

Det

Bundled IDE

I C 12-bit DAC LCD

Controller

Bus

Interface

Host w/PHY Host

Bundled OS touch screen)touch

CRC Secure JTAG Switch

HAB,Tamper

USB OTG w/PHY OTG USB Camera ADC Video USB Segment LCD TFT (w/ Ethernet L2 Security ( External

Family DDR

Programmable Application Secure Fuses VF6xx [Heterogeneous Dual Core] Software Delay Block Cortex A5 up to 500 MHz Y Y Y Y Y 2 2 Y Y Y Timers Cortex M4 up to 167 MHz Ind. Protocols,

Flash Controller 364-pin MAPBGA Peripheral Drivers, HMI, USB, VoIP Secure RAM UARTS VF5xx Broad Third- Cortex A5 up to 500 MHz Y Y Y Y 1 2 Y Y Y Party Ecosystem eSDHC 364-pin MAPBGA Support Low Voltage, Low Power Modular Tower DMA VF3xx Hardware Multiple Operating Cortex A5 up to 266 MHz Y Y Y 1 2 Y Y Y Development Modes, Clock 176-pin LQFP System Gating SRAM TWR-VF65GS10 (1.71 to 3.6V) TWR-VFGS10-KIT TWR-BG65GS10-DS5 ESAI

Core • Up to 266 Hz ARM Cortex-A5 with TrustZone HMI • TFT LCD up to WVGA • Segment LCD Memory • 32 KB I and D L1 Cache • 1.5 MB SRAM • NAND flash controller with 32b ECC Analog • 2 x 12-bit ADC (12-ch), 2 x 12-bit DAC Communication • 4 x UART, 2 x CAN, 3 X SPI, 2 X I2C • 2 Ethernet MAC with IEEE1588 and L2 Switch • USB2.0 OTG with PHY Audio • 3 x SAI for full-duplex serial interfaces like I2S, AC97 • Enhanced serial audio interface (ESAI) Video • Video Interface unit with parallel camera interface Security • Tamper detect, high assurance boot • True RNG Power Management • Internal regulator (PMIC) Package • 176-pin LQFP • Industrial Qualification(-40 to +85C)

Core • Up to 500MHz ARM™ Cortex-A5 with TrustZone HMI • Dual TFT LCD up to XGA resolution Memory • 32KB I and D L1 Cache • 1.5MB SRAM . ECC support on 512KB • 512KB of SRAM convertible to 512KB of L2 Cache • LPDDR2/DDR3 DRAM controller • NAND Flash Controller Analog • 2 x 12-bit ADC(16-Ch), 2 x 12-bit DAC Communication • 6 x UART, 2 x CAN, 4 X SPI, 4 X I2C • 2 Ethernet MAC with IEEE1588 and L2 Switch • Dual USB2.0 HOST and OTG with PHY Audio • 4 x SAI for full-duplex serial interfaces like I2S, AC97 • ESAI – Enhanced Serial Audio Interface • SPDIF Video • Video Interface unit with parallel camera interface Security • Tamper Detect, High Assurance Boot • True RNG Power Management • Internal regulator (PMIC) Package • 17x17 0.8mm pitch 364-pin MAPBGA • Industrial Qualification(-40 to 85C)

Changes from previous family

Core • Up to 500MHz ARM™ Cortex-A5 with TrustZone • Up to 167MHz ARM™ Cortex-M4 HMI • Dual TFT LCD up to XGA resolution Memory • 32KB I and D L1 Cache for A5, 16KB I and D for M4 • 1.5MB SRAM . ECC support on 512KB • 512KB of SRAM convertible to 512KB of L2 Cache • 64KB TCM for M4 • LPDDR2/DDR3 DRAM controller • NAND Flash Controller Analog • 2 x 12-bit ADC (16-Ch), 2 x 12-bit DAC Communication • 6 x UART, 2 x CAN, 4 X SPI, 4 X I2C • 2 Ethernet MAC with IEEE1588 and L2 Switch • Dual USB2.0 HOST and OTG with PHY Audio • 4 x SAI for full-duplex serial interfaces like I2S, AC97 • ESAI – Enhanced Serial Audio Interface • SPDIF Video • Video Interface unit with parallel camera interface and analog input Security • Tamper Detect, High Assurance Boot • True RNG Power Management • Internal regulator (PMIC) Package • 17x17 0.8mm pitch 364-pin MAPBGA • Industrial qualification (-40 to +85C) Changes from previous family

M V F 5 0N S 15 1 C MK 40

Qualification Status Speed (A5 core) P = engineering samples 26 = 266MHz M = qualified 40 = 400MHz 50 = 500MHz Brand: V = Vybrid Package Series: F = current KU = 176LQFP MK = 364BGA Family 3 = Standard (A5 Only) 5 = Advanced (A5 Only) Temp Spec 6 = Dual Core (A5 & M4) C = -40 to +85C Ta

Option 0N = Standard Revision 1N = L2 Cache 1 = Rev 1.1 2N = M4 Primary

Security Memory Size N = No Security 15 = 1.5MB S = Security Enabled

Not all combinations are available. Please refer to part number list

Sample Part Number Part Number Package Description (Superset)

MVF30NN151CKU26 PVF30NN151CKU26 LQFP-EP 176 24*24*1.6 A5-266, No Security, 176LQFP

MVF30NS151CKU26 PVF30NS151CKU26 LQFP-EP 176 24*24*1.6 A5-266, Security, 176LQFP

MVF50NN151CMK40 PVF60NN151CMK50 MAP 364 17*17*1.5 P0.8 A5-400, No Security, 364BGA

MVF50NS151CMK40 PVF60NS151CMK50 MAP 364 17*17*1.5 P0.8 A5-400, Security, 364BGA

MVF50NN151CMK50 PVF60NN151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, No Security, 364BGA

MVF50NS151CMK50 PVF60NS151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, Security, 364BGA

MVF51NN151CMK50 PVF61NN151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, L2 Cache, No Security, 364BGA

MVF51NS151CMK50 PVF61NS151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, L2 Cache, Security, 364BGA

MVF60NN151CMK40 PVF60NN151CMK50 MAP 364 17*17*1.5 P0.8 A5-400, M4, No Security, 364BGA

MVF60NS151CMK40 PVF60NS151CMK50 MAP 364 17*17*1.5 P0.8 A5-400, M4, Security, 364BGA

MVF60NN151CMK50 PVF60NN151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, M4, No Security, 364BGA

MVF60NS151CMK50 PVF60NS151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, M4, Security, 364BGA

MVF61NN151CMK50 PVF61NN151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, M4, L2 Cache, No Security, 364BGA

MVF61NS151CMK50 PVF61NS151CMK50 MAP 364 17*17*1.5 P0.8 A5-500, M4, L2 Cache, Security, 364BGA

MVF62NN151CMK40 PVF62NN151CMK40 MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, No Security, 364BGA

Part numbers highlighted bold are supersets

VF5xxR - Cortex A5+M4, 400MHz, 364BGA OpenVG, TFT, MLB, USBx2, VideoADC, DDR3

VF3xxR - Cortex A5+M4, 266MHz, 176LQFP Feature Integration Feature OpenVG, TFT , MLB, USB, VideoADC

PerformanceProduction

Feature 3xxR Family 5xxR Family

266MHz Cortex-A5 400MHz Cortex-A5 CPU 133MHz Cortex-M4 133MHz Cortex-M4 1.5MB (512K ECC) On-chip memory 1.5MB (512K ECC) OR 1MB & 512K L2 cache

Serial Flash interface Dual QuadSPI Dual QuadSPI

Yes (8-bit) Yes (16-bit) NAND Up to 32-bit HW ECC Up to 32-bit HW ECC FlexBus interface Yes, (addr / data mux’d plus 8-bit Yes (addr / data mux’d) (parallel NOR) dedicated data)

DRAM interface No 16-bit LPDDR2/DDR3

TFT & 40x4 Segmented LCD OR TFT & 40x4 Segmented LCD OR Display interface 2x TFT up to WQVGA 2x TFT up to WVGA

2x Composite 4x Composite Video ADC / Camera Input 24-bit parallel 24-bit parallel

10/100 Ethernet w/ IEEE1588 1 2

10-channel 12-bit ADC Yes Yes

USB 1x USB OTG HS 2x USB OTG HS

SAI x3 (i2s x3) SAI x4 (i2s x4) Audio interface ESAI x1 (2 Tx, 4 Tx or Rx) ESAI x1 (2 Tx, 4 Tx or Rx)

UART, DSPI, I2C 4, 3, 4 6, 4, 4

SD/MMC interface 1 2

CAN 2x FlexCAN 2x FlexCAN

MOST 1x MLB50 1x MLB50

GPIO Up to 115 Up to 136

Package 176LQFP 364BGA

S V F 3 1 1 R 3 K1 C MK 2

Qualification Status Speed (A5 core) P = engineering samples 2 = 266MHz S = automotive qualified 4 = 400MHz

Brand: V = Vybrid Package Series: F = current KU = 176LQFP MK = 364BGA Family 3 = Standard 5 = Advanced Temp Spec Core C = -40 to +85C Ta 1 = Cortex A5 2 = Cortex A5 + M4 Revision 3 = M4 Primary K1 = Rev 1.1 Graphics 1 = No Open VG Memory Option 2 = Open VG 3 = Standard (1.5MB SRAM) Version 2 = Optional (1MB SRAM and 512K L2 Cache) R = Auto

Not all combinations are available. Please refer to part number list

Sample Part Number Part Number Package Description (Superset)

SVF311R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, 176LQFP-EP

SVF312R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, OpenVG GPU, 176LQFP-EP

SVF321R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4, 176LQFP-EP

SVF322R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4, OpenVG GPU, 176LQFP-EP A5-266, M4 Primary, OpenVG GPU, 176LQFP- SVF332R3K1CKU2 PVF332R3K1CKU2 LQFP-EP 176 24*24*1.6 EP SVF511R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, 364BGA

SVF512R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, OpenVG GPU, 364BGA

SVF521R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4, 364BGA

SVF522R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4, OpenVG GPU, 364BGA

SVF532R3K1CMK4 PVF532R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, OpenVG GPU, 364BGA

SVF522R2K1CMK4 N/A MAP 364 17*17*1.5 P0.8 A5-400, M4, L2 Cache, OpenVG GPU, 364BGA

Part numbers highlighted bold are supersets

TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 18 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 19 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Tower System Module TWR-VF65GS10* = $199 Available Date: Q2 2013 *Includes 256k code-size, 1yr FREE ARM® DS-5™ for Vybrid Tower System

Tower System KIT TWR-VF65GS10-KIT* = $269 (Includes TWR-SER, TWR-ELEV) Available Date: Q2 2013 System on Module (SOM) *Includes 256k code-size, 1yr FREE ARM DS-5 for Vybrid Tower System EmCraft VF3xx Phytec Tower System PRO Device Solutions TWR-VF65GS10-PRO* = $399 F& S (Includes TWR-SER2, TWR-LCD-RGB, TWR-ELEV) Seco Available Date: Q2 2013 *Includes 256k code-size, 1yr FREE ARM DS-5 for Vybrid Tower System

Tower System DS-5 TWR-VF65GS10-DS5* = $1500 (Includes TWR-SER2, TWR-LCD-RGB, TWR-ELEV) Available Date: Q2 2013 Includes 1MB code-size, 1yr ARM DS-5 for Vybrid Toolkit, CMSIS-DAP

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 22 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • ARM Cortex-A5 processor core • Supports ARMv7-A instruction set architecture − Includes FPU (VFPv3-D16) definition . Single & Double precision, add, sub, mult, div, mac, sqrt − NEON Media Processing Engine (MPE) . Extends FPU capability with advanced SIMD instructions for media and signal processing functions over 8, 16, 32bit integer and 32bit floating point data types • 8-stage single issue pipeline implementation operating at 500MHz − 1.57 DMIPS per MHz integer performance − 4-stage load/store pipeline − 5-stage FPU/MPE pipeline • Processor-local Memories − 2 way set-associative 32 Kbyte Instruction Cache with 32 byte line size − 4 way set-associative 32 Kbyte Data Cache with 32 byte line size − Optional 512K L2 Cache − Standard CA5 Memory Management Unit 64-bit AXI System Bus Interface supporting multiple outstanding transactions

− Operating at 1:1 clock ratio compared to platform

. Core frequencies = 133.3 – 166.7 MHz • 3-stage pipeline provides 1.25 DMIPS per MHz performance

− Includes single precision FPU, DSP & SIMD ISA extensions • 16K Code and 16K System Caches with 32-byte cache line size • 64 Kbytes of Tightly-Coupled Memory split equally across TCM{L,U} • Modified Harvard 64-bit AHB system bus interface

− 64-bit AHB backdoor port to TCMs • CoreSight debug and trace system • Nested Vector Interrupt Controller (NVIC)

• The MPE extends the Cortex-A5 Floating Point Unit (FPU) an additional register set supporting a rich set of SIMD operations over 8-, 16-, and 32-bit integer and 32-bit Floating-Point data types.

TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 28 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • Slave peripheral module implements 16 hardware semaphores − Further assists in software serialization for shared data spaces • Semaphore module supports 16 gates for dual CPU config − Gates appear as a 16-entry byte-size array in memory map . Processor locks a gate by writing “processor_number+1” to it • Must read back gate value to verify lock operation was successful . Once locked, the gate is unlocked by zero write from locking processor . Each gate appears as a 3-state, 2-bit state machine • If gate = 0b00, then state = unlocked • If gate = 0b01, then state = locked by processor 0 • If gate = 0b10, then state = locked by processor 1 . Optional IRQ notification after a failed write indicates gate is unlocked . Secure reset mechanism to clear individual gates or notification logic + ability to clear all

− CP0 = CA5 running Linux (Linux) (MQX)

− CP1 = CM4 running MQX IPC API IPC API

• MCC takes place between Transport Transport

transport layers of 2 MCAPI Layer Datapath Layer OS Specific OS Specific implementations via shared Driver Datapath Driver memory Shared Memory • Communication is transparent

to application layer Core 0 Core 1 Linux • Implemented like a socket or Multi-core MQX Communication message queue

Shared Memory Region System Memory

A5 core configures clocks, DDR, and other basic init

A5 core enables M4 clock

A5 code continues M4 Code Starts

. CA5, GPU, 2D-ACE: 64-bit AXI interface − Optimised Master to Slave connections . Configurable at integration . Reduces power and area of NIC301

− Optimised for Data Bandwidth, not Data Latency − NIC301 has read/write buffering to improve throughput on larger data transfers − Typ. 5 cycle latency for access between Master & Internal RAM

• Supports variable sized queues and circular queues

• Source and destination address registers are independently configured to post-increment or remain constant

• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request

• Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer

• DMA transfers possible between system memories, General Purpose I/Os (GPIOs) and Slave Peripherals that support DMA

• Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to a total of 64 potential request sources

Quad Mode SDR Read Command Sequence:

− Flash is memory mapped and all XBAR read accesses are automatically carried out

− Read, program and erase operations can be carried out over peripheral bus.

− DMA and interrupt support to read RX Buffer data via AMBA AHB bus (64-bit width interface) or IP registers space (32 bit access).

(Acquired )

• The QuadSPI module is flexible enough to support all commands from all manufacturers • Using its flexible core engine

• Slow − 128kHz IRC − 32kHz XOSC

• 1KHz internal LPO (Low Power Oscillator) – used as glitch filter in PORT

• External Audio clock • External Ethernet clock

• What PLLs are available? − PLL1 (480-528 MHz) − PLL2 (480-528 MHz) − PLL3 (480-528 MHz)

• What PFDs? − PLL1 (1-4) − PLL2 (1-4) − PLL3 (1-4)

− Primary Fractional Dividers

The rest are configurable…..

• DAC • I2C • PDB • UART • PIT • LCD • LPTMR • VIU • SPI

GPU SPI − Platform Clock NFC I2C SPDIF UART VADC LCD SAI VIU Ethernet SNVS FlexCAN SWO * Examples on next page Trace

PLL7 USB1 PLL 480 MHz Yes No No

• Low Power Modes − Low Power Run (LPRUN) Mode – PLLs OFF, Sys clock is 24 MHz − Ultra Low Power Run (ULPRUN) Mode – PLLs OFF, Sys clock is 32 kHz − WAIT Mode – Both the CA5 and CM4 cores are halted . Optionally can keep core clocked to debug in WAIT mode − STOP Mode – Cores halted, Peripheral clocks are gated off, Optional Regulator Power down, Deep Sleep option

• Power Gated Modes − LPSTOP[3-1] - Peripheral clocks are gated off, power domains are de- energized, and some (or all) SysRam is lost

e.g., CCM_CCGR0: FlexCAN0 CCM_CCGRx Register definition

Enable Well Bias Mode – reduce leakage current

Power down HPREG

Deep Sleep – periphery power down, maintain memory contents, outputs pulled low

Assert Standby Pin • For External Power Mgmt IC

Setup Modules or Reset for Wakeup

Module Options through WKPU • Pins(17 total), LPTIMER, SNVS_LP, ADC0/1, or PIT

*Option to run from device directly

BOOTMOD_1 (PTE0) BOOTMOD_0 (PTE1) Boot from Fuses 0 0 Serial Downloader 0 1 RCON Boot 1 0 Reserved 1 1

Check CPU ID CPUID != 0

CPUID == 0

Use Wakeup Check Wakeup Check Reset Wakeup From Handler and Handler in valid Type Low Power Mode argument from Address Range SRC Register No

Normal Mode

Valid Range Check Boot Mode (using fuses and/ Serial Check CPU ID or GPIOs) CPUID == 0

Internal System Reset using Watchdog Download Initial boot Image (primary or secondary Fail depending on CPUID != 0 persistent bit set)

Primary Boot Device is I2C /DSPI Update Wakeup Pass Error Status No Register Yes No

Authenticate Download and Fail Primary Image? Send Wakeup Image Authenticate Error Interrupt Image from Serial PASS EEPROM

Yes Fail

Set Secondary Wait for Reset Image Persistent Download and Fail Pass bit and perform Authenticate SW Reset Image using USB/ UART

Pass Initiate System Reset using Watchdog Execute Image

IVT and DCD Section of the Application must be located within first 4KB.

TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 73 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 74 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Field Description header Barker Code (0x412000D1) entry Absolute address of the first instruction to execute from the image reserved1 Reserved and should be zero dcd Absolute address of the image DCD. The DCD is optional so this field may be set to NULL if no DCD is required. boot_data Absolute address of the Boot Data self Absolute address of the IVT. Used internally by the ROM csf Absolute address of Command Sequence File (CSF) used by the HAB library. This field must be set to NULL when not performing a secure boot reserved2 Reserved and should be zero

Field Description start Absolute Address of Image length Size of Program Image plugin Plug-in Flag

U-Boot SPI Flash SDCard NAND NOR QuadSPI Flash with boot header – u-boot.imx

BootROM retrieves code to SRAM, BootROM changes Program then change program counter to Counter to NOR/QuadSPI region. U- SRAM for U-Boot to start executing Boot starts executing there.

Set up clocks, timers

Set up console

Set up DDR

U-Boot relocates itself from SRAM to high DRAM region and change program to DRAM to match were it left off in SRAM

Retrieve saved environment variables from storage U-Boot prompt – Misc drivers waiting for user inputs startup

• Important to keep in mind that the BootROM may modify default register reset values − CA5 Clock at 264 MHz − Registers modified depend on boot interface . UART by default modified

• Also be aware of code executing before debug connection and execution

SW Image Compare Reload Image X

Hash

Public Verify Key Hash OTP (CMS/RSA) SRK Sign Private (CMS/RSA) Key

SW Image + SW Image + Signature Signature

Build Environment Decrypted SW Image Device SW Image Boot

Secret Key Decrypt OTP (AES) Secret OTP Key Key Key Encrypt CAAM Decrypt

(AES) (AES) (AES)

Key Key Blob

Manufacturing

Key Blob Key Encrypted Encrypted SW Image SW Image

Trusted execution protects against • Attacks from compromised platform SW • Access to protected peripherals and memory • Backdoors using untrusted DMA masters • Starvation of resources available to security-critical services

• Memory isolation Rich OS Trusted OS Privileged − Virtual & physical Mode • Peripheral isolation

− Master & slave General General Protected Trusted Hardware Peripheral DMA Peripheral DMA • Interrupt separation General RAM Protected RAM • Watchdog protection

General Trusted SW SW

HW Firewall

General RAM Protected RAM

General Trusted SW SW

HW Firewall

General General Protected Trusted Peripheral DMA Peripheral DMA

Master’s Privilege (User/Sprv; TZ/non-TZ) “What slaves can be accessed”

CSU

Slave’s Access Permissions (TZ/non-TZ; Read/Write etc.) “What Masters can access”

LinuxLink (Timesys SDK)

Network Freescale MQX Software Serial

Timesys / Freescale MCC USB Linux Workstation (or virtual)

ARM DS-5

TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 93 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 94 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 95 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Vybrid TWR-VF65GS10 Support

• U-Boot – uSD, NFS, NAND supported • API to control DMA, high res timers (1us resolution), GPIO API, reboot & shutdown API, CCM, PIT, serial, FlexTimer, eDMA • FEC (IPv4) 100-Mbps IEEE via RMII • Display: TWR-LCD-RGB support, portrait or landscape, Virtual console support • Touchscreen: TWR-LCD-RGB using ADC and GPIO, resistive touch • UART, keypad GPIO, pushbuttons, I2C v2.1 (except multi-master) up to 400Kbps • NAND: NFC supported through MTD • USB: OTG, OTG host, MSC class (gadget AND host). OTG2 in host mode, HID class (host mode), Ethernet-over-USB class, Audio class (host mode), Video host class

• Audio (stereo codec) • MMC/SD/SDIO • QuadSPI • DSPI • WATCHDOG • ASRC (Asynchronous Sample Rate Converter) • System Power Management – Currently LPRUN & STOP (Vybrid: LPRUN, ULPRUN, STOP, WAIT LPSTOP1-3) • ADC driver (/dev/mvf-adc.0) • CAAM support included • FlexCAN (untested) • MCC – Multi-Core Communication via predefined shared memory

TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 97 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • MQX • Linux − O/S components are libraries − Kernel is a bare-metal executable, linked with your application to but isn’t enough. create a single bare-metal − Your application (except possibly device drivers) is built separately and runs execution image. (launched) from a file system. − Source distributed as DS-5 − Therefore a root file system (RFS) is a (Eclipse) projects in a single required component of Linux. source tree. − Timesys Factory (on web or desktop) builds the RFS. It will build the Kernel − Built with ARM bare-metal and your Application, but they can be compiler. also built “outside” as well. • (advanced) − Built with (Timesys) gcc compiler. − A single address space – no • (advanced) memory protection, mapping, − Linux utilizes the memory management or transformations between unit (MMU) of the A5 core. All processes hardware I/O, O/S components, are hardware protected from stepping on application. each other’s memory. − Programs are tasks each in their − Programs run as a process – which can have many threads. own thread.

− End-to-end development, from SoC bring-up to ARM Development Studio 5 application debug Eclipse • Powerful ARM Ltd. Compiler

− Best code size and performance Compiler Debugger Analyzer

• Intuitive DS-5 Debugger Device Configuration Database − Flexible graphical user interface Simulation Hardware Debug − DSTREAM probe with 4GB trace buffer

− Example distribution and applications

• Streamline™ Performance Analyzer

− System-wide analysis of Linux systems

− Timeline and profiling reports

Products:

• Specific low cost editions available for Vybrid (see upcoming slides for more details on Vybrid Editions) • DS-5 Professional Edition (armcc): $6600 (30-day evaluations and floating Options are available for most license types)

Linux/Timestorm Project

MQX Project

User App User App (tasks) process(es) API shared library Interrupts API library

Kernel Module Driver Hardware Semaphore

Endpoint 0,0,1 Endpoint 0,2,3 Endpoint 1,0,1 Endpoint 1,0,2

Free buffer pool

Shared SRAM

From board bring up, firmware development through to application optimization Development Studio 5 for Freescale Vybrid is the right tool for your customer’s development needs

• Node-locked • Node-locked • 12-month • 12-month • Only supports Vybrid Tower • Supports all Vybrid devices and Tower • 256 KB code size limit System • Simple Download at ARM.com • 1 MB code size limit • Serial Number required for download at ARM.com

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Freescale Semiconductor: SVF312R3K1CKU2 SVF522R3K1CMK4 SVF322R3K1CKU2 SVF522R2K1CMK4 SVF511R3K1CMK4 SVF512R3K1CMK4 SVF521R3K1CMK4 SVF532R3K1CMK4 SVF311R3K1CKU2 SVF321R3K1CKU2