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Vxworks Architecture Supplement, 6.2
VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction -
SIMD Extensions
SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel. -
Download MEN G501 Manual
20G501-00 E2 – 2011-06-20 G501 – 3U CompactPCI Serial® SATA HDD/SSD Shuttle User Manual Embedded Solutions ® G501 – 3U CompactPCI® Serial SATA HDD/SSD Shuttle G501 – 3U CompactPCI® Serial SATA HDD/SSD Shuttle The G501 is a CompactPCI® Serial hard disk drive carrier board. It is designed to carry a 2.5" SATA hard disk drive (RAID level depending on the CPU) or a solid state drive. The unit's front panel features four LEDs for the board's SGPIO status (used for the hot plug functionality) and the status of the internal controller's power supply. Block Diagram LEDs SGPIO Controller +3.3V P1 Hard Power Drive +5V Supply +12V SATA MEN Mikro Elektronik GmbH 2 20G501-00 E2 – 2011-06-20 Technical Data Technical Data Mass Storage • Serial ATA (SATA) - One port for onboard 2.5" hard disk drive or solid state drive - Transfer rates depending on HDD/SSD - RAID level depends on CPU board External Interfaces • 4 LEDs at front panel - 3 for the SGPIO status (for hot plug functionality) - 1 for the internal controller's supply voltage status CompactPCI Serial • Compliance with CompactPCI Serial PICMG CPCI-S.0 Specification • Peripheral slot • Host interface: one SATA and one SGPIO interface Electrical Specifications • Supply voltage - +12V (-25%/+10%), power consumption depending on HDD/SSD Mechanical Specifications • Dimensions: conforming to CPCI-S.0 specification for 3U boards • Hot plug functionality (depending on CPU board). • Weight: 125 g (without HDD/SSD) Environmental Specifications • Temperature range (operation): - -40..+85°C (depending on HDD or SSD; please refer to the HDD/SSD speci- fications for possible limits) - Airflow: min. -
Compactpci Serial ...The Smart Solution
CompactPCI® Serial ... ... the Smart Solution © EKF •www. ekf.com CompactPCI® Serial Systems Designed for performance • 40 x PCI® Express • 8 x Gigabit Ethernet • 8 x SATA • 8 x USB3 CompactPCI® Serial - the Smart Solution www.ekf.com/s/serial.html © EKF •www. ekf.com CompactPCI® Serial Systems CPCI Serial backplanes for optimum throughput CompactPCI® Serial - the Smart Solution Sample Backplanes CompactPCI® Serial The CompactPCI® Serial system slot is located either most left or most right © EKF •www. ekf.com CompactPCI® Serial Systems Reverse order backplanes (system slot right aligned) for CPU cards with 4HP to 12HP front panel CompactPCI® Serial - the Smart Solution www.ekf.com/s/serial.html © EKF •www. ekf.com CompactPCI® Serial Systems CPCI® Serial BLUBRICK series - ultra rugged CompactPCI® Serial - the Smart Solution www.ekf.com/s/srs/srs1201/srs1201.html SRS-1201-BLUBRICK CompactPCI® Serial © EKF • www.ekf.com CompactPCI® Serial Systems CPCI Serial BluBoxx series - small and economic www.ekf.com/s/srs/srs3201/srs3201.html CompactPCI® Serial - the Smart Solution SRS-3201-BLUBOXX CompactPCI® Serial © EKF •www. ekf.com CompactPCI® Serial Systems CPCI Serial rugged system racks www.ekf.com/s/srs/srs4401/srs4401.html CompactPCI® Serial - the Smart Solution SRS-4401-SERIAL CompactPCI® Serial © EKF •www. ekf.com CompactPCI® Serial Systems CPCI® Serial racks 84HP CompactPCI® Serial - the Smart Solution www.ekf.com/s/srs/srs8401/srs8401.html SRS-8401-SERIAL CompactPCI® Serial © EKF •www. ekf.com Embedded Blue® CPCI® Serial boxed solutions • fixed & custom configuration CompactPCI® Serial - the Smart Solution www.ekf.com/b/bc200/bc200.html BC200 Embedded Blue® © EKF •www. -
SEWIP Program Leverages COTS P 36 P 28 an Interview with Deon Viergutz, Vice President of Cyber Solutions at Lockheed Martin Information Systems & Global Solutions
@military_cots John McHale Obsolescence trends 8 Special Report Shipboard displays 44 Mil Tech Trends Predictive analytics 52 Industry Spotlight Aging avionics software 56 MIL-EMBEDDED.COM September 2015 | Volume 11 | Number 6 RESOURCE GUIDE 2015 P 62 Navy SEWIP program leverages COTS P 36 P 28 An interview with Deon Viergutz, Vice President of Cyber Solutions at Lockheed Martin Information Systems & Global Solutions Military electronics market overview P 14 Volume 11 Number 6 www.mil-embedded.com September 2015 COLUMNS BONUS – MARKET OVERVIEW Editor’s Perspective 14 C4ISR funding a bright spot in military 8 Tech mergers & military electronics electronics market obsolescence By John McHale, Editorial Director By John McHale Q&A EXECUTIVE OUTLOOK Field Intelligence 10 Metadata: When target video 28 Defending DoD from cyberattacks, getting to data is not enough the left of the boom By Charlotte Adams 14 An interview with Deon Viergutz, Vice President of Cyber Solutions at Lockheed Martin Information Mil Tech Insider Systems & Global Solutions 12 Broadwell chip boosts GPU performance for COTS SBCs 32 RF and microwave innovation drives military By Aaron Frank radar and electronic warfare applications An interview with Bryan Goldstein, DEPARTMENTS General Manager of the Aerospace and Defense, Analog Devices 22 Defense Tech Wire By Mariana Iriarte SPECIAL REPORT 60 Editor’s Choice Products Shipboard Electronics 112 University Update 36 U.S. Navy’s electronic warfare modernization On DARPA’s cybersecurity radar: 36 effort centers on COTS Algorithmic and side-channel attacks By Sally Cole, Senior Editor By Sally Cole 114 Connecting with Mil Embedded 44 Key to military display technologies: Blog – The fascinating world of System integration By Tom Whinfrey, IEE Inc. -
Power Architecture® ISA 2.06 Stride N Prefetch Engines to Boost Application's Performance
Power Architecture® ISA 2.06 Stride N prefetch Engines to boost Application's performance History of IBM POWER architecture: POWER stands for Performance Optimization with Enhanced RISC. Power architecture is synonymous with performance. Introduced by IBM in 1991, POWER1 was a superscalar design that implemented register renaming andout-of-order execution. In Power2, additional FP unit and caches were added to boost performance. In 1996 IBM released successor of the POWER2 called P2SC (POWER2 Super chip), which is a single chip implementation of POWER2. P2SC is used to power the 30-node IBM Deep Blue supercomputer that beat world Chess Champion Garry Kasparov at chess in 1997. Power3, first 64 bit SMP, featured a data prefetch engine, non-blocking interleaved data cache, dual floating point execution units, and many other goodies. Power3 also unified the PowerPC and POWER Instruction set and was used in IBM's RS/6000 servers. The POWER3-II reimplemented POWER3 using copper interconnects, delivering double the performance at about the same price. Power4 was the first Gigahertz dual core processor launched in 2001 which was awarded the MicroProcessor Technology Award in recognition of its innovations and technology exploitation. Power5 came in with symmetric multi threading (SMT) feature to further increase application's performance. In 2004, IBM with 15 other companies founded Power.org. Power.org released the Power ISA v2.03 in September 2006, Power ISA v.2.04 in June 2007 and Power ISA v.2.05 with many advanced features such as VMX, virtualization, variable length encoding, hyper visor functionality, logical partitioning, virtual page handling, Decimal Floating point and so on which further boosted the architecture leadership in the market place and POWER5+, Cell, POWER6, PA6T, Titan are various compliant cores. -
Foundation Overview February 2014
OpenPOWER Overview May 2015 Keith Brown Director, IBM Systems Technical Strategy & Product Security [email protected] http://openpowerfoundation.org/ © 2015 OpenPOWER Foundation What is the OpenPOWER Ecosystem? Cloud Software Existing ISV community of 800+ Standard Operating Open Environment Source All major Linux distros (System Mgmt) Software Communities Operating Open sourced Power8 System / KVM firmware stack New OSS Firmware OpenPOWER Resources for porting and Firmware Community optimizing on Hardware OpenPOWER OpenPOWERFoundation.org Technology 2 © 2015 OpenPOWER Foundation A Fast Start for OpenPOWER! The year • Collaborative solutions, standards, and reference designs available • Independent members solutions and systems ahead • Sector growth in technical computing and cloud • Global growth with increasing depth in all layers • Broad adoption across hardware, software, and end users 3 © 2015 OpenPOWER Foundation Fueling an Open Development Community 4 © 2015 OpenPOWER Foundation Critical workloads run on Linux on Power Web, Java Apps and Infrastructure Analytics & Research HPC applications for Life Sciences • Highly threaded • Compute intensive • Throughput oriented • High memory bandwidth • Scale out capable • Floating point • High quality of service • High I/O rates Business Applications Database • High quality of service • Handle peak workloads • Scalability • Scalability • Flexible infrastructure • High quality of service • Large memory footprint • Resiliency and security 5 © 2015 OpenPOWER Foundation IBM, Mellanox, and NVIDIA -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Multi-Platform Auto-Vectorization
H-0236 (H0512-002) November 30, 2005 Computer Science IBM Research Report Multi-Platform Auto-Vectorization Dorit Naishlos, Richard Henderson* IBM Research Division Haifa Research Laboratory Mt. Carmel 31905 Haifa, Israel *Red Hat Research Division Almaden - Austin - Beijing - Haifa - India - T. J. Watson - Tokyo - Zurich LIMITED DISTRIBUTION NOTICE: This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. I thas been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g ,. payment of royalties). Copies may be requested from IBM T. J. Watson Research Center , P. O. Box 218, Yorktown Heights, NY 10598 USA (email: [email protected]). Some reports are available on the internet at http://domino.watson.ibm.com/library/CyberDig.nsf/home . Multi-Platform Auto-Vectorization Dorit Naishlos Richard Henderson IBM Haifa Labs Red Hat [email protected] [email protected] Abstract. The recent proliferation of the Single Instruction Multiple Data (SIMD) model has lead to a wide variety of implementations. These have been incorporated into many platforms, from gaming machines and em- bedded DSPs to general purpose architectures. In this paper we present an automatic vectorizer as implemented in GCC - the most multi-targetable compiler available today. We discuss the considerations that are involved in developing a multi-platform vectorization technology, and demonstrate how our vectorization scheme is suited to a variety of SIMD architectures. -
A Bibliography of Publications in IEEE Micro
A Bibliography of Publications in IEEE Micro Nelson H. F. Beebe University of Utah Department of Mathematics, 110 LCB 155 S 1400 E RM 233 Salt Lake City, UT 84112-0090 USA Tel: +1 801 581 5254 FAX: +1 801 581 4148 E-mail: [email protected], [email protected], [email protected] (Internet) WWW URL: http://www.math.utah.edu/~beebe/ 16 September 2021 Version 2.108 Title word cross-reference -Core [MAT+18]. -Cubes [YW94]. -D [ASX19, BWMS19, DDG+19, Joh19c, PZB+19, ZSS+19]. -nm [ABG+16, KBN16, TKI+14]. #1 [Kah93i]. 0.18-Micron [HBd+99]. 0.9-micron + [Ano02d]. 000-fps [KII09]. 000-Processor $1 [Ano17-58, Ano17-59]. 12 [MAT 18]. 16 + + [ABG+16]. 2 [DTH+95]. 21=2 [Ste00a]. 28 [BSP 17]. 024-Core [JJK 11]. [KBN16]. 3 [ASX19, Alt14e, Ano96o, + AOYS95, BWMS19, CMAS11, DDG+19, 1 [Ano98s, BH15, Bre10, PFC 02a, Ste02a, + + Ste14a]. 1-GHz [Ano98s]. 1-terabits DFG 13, Joh19c, LXB07, LX10, MKT 13, + MAS+07, PMM15, PZB+19, SYW+14, [MIM 97]. 10 [Loc03]. 10-Gigabit SCSR93, VPV12, WLF+08, ZSS+19]. 60 [Gad07, HcF04]. 100 [TKI+14]. < [BMM15]. > [BMM15]. 2 [Kir84a, Pat84, PSW91, YSMH91, ZACM14]. [WHCK18]. 3 [KBW95]. II [BAH+05]. ∆ 100-Mops [PSW91]. 1000 [ES84]. 11- + [Lyl04]. 11/780 [Abr83]. 115 [JBF94]. [MKG 20]. k [Eng00j]. µ + [AT93, Dia95c, TS95]. N [YW94]. x 11FO4 [ASD 05]. 12 [And82a]. [DTB01, Dur96, SS05]. 12-DSP [Dur96]. 1284 [Dia94b]. 1284-1994 [Dia94b]. 13 * [CCD+82]. [KW02]. 1394 [SB00]. 1394-1955 [Dia96d]. 1 2 14 [WD03]. 15 [FD04]. 15-Billion-Dollar [KR19a]. -
Compactpci Express for Control Applications H
WEP038 Proceedings of ICALEPCS2009, Kobe, Japan COMPACTPCI EXPRESS FOR CONTROL APPLICATIONS H. Kleines, M. Ramm, M. Drochner,W. Erven, Zentralinstitut für Elektronik, Forschungszentrum Jülich, Jülich, Germany Abstract The PCIMG standardized ATCA (PICMG 3.x) and CompactPCI (CPCI) is well established in control MicroTCA (PICMG MTCA.0) . ATCA was mainly driven applications as a standard for industrial PCs and as a by the Telecom industry. MicroTCA is a more cost standard for front-end instrumentation, e.g. by means of efficient spin off from ATCA based on AMC, the ATCA the transparent optical PCI/CPCI Bridge MXI-4 from mezzanine card standard. With company National National Instruments. In both application areas increasing Instruments as the main driving force, PICMG also performance requirements ask for a replacement of the defined CompactPCI Express (PICMG EXP.0) as a parallel CPCI bus by a backplane based on high speed downward compatible extension of CompactPCI. On the serial links, similar to the replacement of PCI by PCIe in initiative of several vendors of CompactPCI CPUs, the desktop environment. CompactPCI Express and its PICMG has started a new not yet finished standardization derivative PXI Express both provide a smooth and cost- activity for the CompactPCI Plus standards PICMG 2.30 efficient transition path from CPCI to high speed serial PlusIO and CPLUS.0. CompactPCI Plus also aims at a links on the backplane. follow up system to CompactPCI, which is downward Forschungszentrum Jülich has developed a compatible. As a consequence, CompactPCI Plus is a CompactPCI Express carrier board for CMC daughter direct competitor of CompactPCI. CompactPCI Plus modules that is compatible to the SIS1100-CMC/cCMC defines also USB, SATA and Gigabit Ethernet links on the boards from company Struck Innovative Systeme. -
Compiler-Based Data Prefetching and Streaming Non-Temporal Store Generation for the Intel R Xeon Phitm Coprocessor
Compiler-based Data Prefetching and Streaming Non-temporal Store Generation for the Intel R Xeon PhiTM Coprocessor Rakesh Krishnaiyer†, Emre K¨ult¨ursay†‡, Pankaj Chawla†, Serguei Preis†, Anatoly Zvezdin†, and Hideki Saito† † Intel Corporation ‡ The Pennsylvania State University TM Abstract—The Intel R Xeon Phi coprocessor has software used, and generating them. In this paper, we: TM prefetching instructions to hide memory latencies and spe- • Present how the Intel R Xeon Phi coprocessor soft- cial store instructions to save bandwidth on streaming non- ware prefetch and non-temporal streaming store instructions temporal store operations. In this work, we provide details on R compiler-based generation of these instructions and evaluate are generated by the Intel Composer XE 2013, TM their impact on the performance of the Intel R Xeon Phi • Evaluate the impact of these mechanisms on the overall coprocessor using a wide range of parallel applications with performance of the coprocessor using a variety of parallel different characteristics. Our results show that the Intel R applications with different characteristics. Composer XE 2013 compiler can make effective use of these Our experimental results demonstrate that (i) a large mechanisms to achieve significant performance improvements. number of applications benefit significantly from software prefetching instructions (on top of hardware prefetching) that I. INTRODUCTION are generated automatically by the compiler for the Intel R TM TM The Intel R Xeon Phi coprocessor based on Intel R Xeon Phi coprocessor, (ii) some benchmarks can further Many Integrated Core Architecture (Intel R MIC Architec- improve when compiler options that control prefetching ture) is a many-core processor with long vector (SIMD) units behavior are used (e.g., to enable indirect prefetching), targeted for highly parallel workloads in the High Perfor- and (iii) many applications benefit from compiler generated mance Computing (HPC) segment.